Commit Graph

34 Commits

Author SHA1 Message Date
Stefan Kalkowski
c850462f43 hw: replace kernel's object id allocators
Instead of having an ID allocator per object class use one global allocator for
all. Thereby artificial limitations for the different object types are
superfluent. Moreover, replace the base-hw specific id allocator implementation
with the generic Bit_allocator, which is also memory saving.

Ref #1443
2015-04-17 16:13:20 +02:00
Stefan Kalkowski
a168c9d6ce core: remove global capability id counter
The global capability ID counter is not used by NOVA and Fiasco.OC
and in the future not needed by base-hw too. Thereby, remove the static
counter variable from the generic code base and add it where appropriated.

Ref #1443
2015-04-17 16:13:19 +02:00
Martin Stein
60e392f0c0 hw: support Wandboard Quad (i.MX6)
The port uses the Cortex-A9 private timer for the kernel and an EPIT as
user timer. It was successfully tested on the Wandboard Quad and the CuBox-i
with the signal test. It lacks L2-cache and Trustzone support by now.

Thanks to Praveen Srinivas (IIT Madras, India) and  Nikolay Golikov (Ksys Labs
LLC, Russia). This work is partially based on their contributions.

Fix #1467
2015-04-09 16:04:43 +02:00
Adrian-Ken Rueegsegger
544148bc24 hw_x86_64: Add I/O port allocator to platform
Add the entire I/O port range to the I/O port allocator on x86. Do nothing
on ARM platforms since there are no I/O port resources.
2015-03-27 11:53:32 +01:00
Reto Buerki
5765398741 hw_x86_64: Add x86 platform services to core
Use the x86-specific platform_services.cc file and register the I/O port
session component.
2015-03-27 11:53:32 +01:00
Reto Buerki
a21959fc26 hw_x86_64: Implement APIC-based PIC driver
The implementation initializes the Local APIC (LAPIC) of CPU 0 in xapic
mode (mmio register access) and uses the I/O APIC to remap, mask and
unmask hardware IRQs. The remapping offset of IRQs is 48.

Also initialize the legacy PIC and mask all interrupts in order to
disable it.

For more information about LAPIC and I/O APIC see Intel SDM Vol. 3A,
chapter 10 and the Intel 82093AA I/O Advanced Programmable Interrupt
Controller (IOAPIC) specification

Set bit 9 in the RFLAGS register of user CPU context to enable
interrupts on kernel- to usermode switch.
2015-03-27 11:53:31 +01:00
Reto Buerki
e3332c6c53 hw_x86_64: Drop obsolete isr.s assembly file 2015-03-27 11:53:24 +01:00
Adrian-Ken Rueegsegger
2af5aaa54d hw_x86_64: Add Tss class
The class Genode::Tss represents a 64-bit Task State Segment (TSS) as
specified by Intel SDM Vol. 3A, section 7.7.

The setup function sets the stack pointers for privilege levels 0-2 to
the kernel stack address. The load function loads the TSS segment
selector into the task register.
2015-03-27 11:53:23 +01:00
Reto Buerki
c7cadf52a6 hw_x86_64: setup ISR and IDT
* Add isr.s assembler file:
    The file declares an array of Interrupt Service Routines (ISR) to handle
    the exception vectors from 0 to 19, see Intel SDM Vol. 3A, section
    6.3.1.
* Add Idt class:
  * The class Genode::Idt represents an Interrupt Descriptor Table as
    specified by Intel SDM Vol. 3A, section 6.10.
  * The setup function initializes the IDT with 20 entries using the ISR
    array defined in the isr.s assembly file.
* Setup and load IDT in Genode::Cpu ctor:
    The Idt::setup function is only executed once on the BSP.
* Declare ISRs for interrupts 20-255
* Set IDT size to 256
2015-03-27 11:53:18 +01:00
Norman Feske
a974726e26 hw: skeleton for building on x86_64
This patch contains the initial code needed to build and bootstrap the
base-hw kernel on x86 64-bit platforms. It gets stuck earlier
because the binary contains 64-bit instructions, but it is started in
32-bit mode. The initial setup of page tables and switch to long mode is
still missing from the crt0 code.
2015-03-27 11:53:16 +01:00
Alexander Boettcher
1f8fad8fa1 base: refactor signal_transmitter::submit
Move it to platform specific .cc file, so that it may get re-implemented
platform specifically if needed.

Issue #1446
2015-03-19 09:32:52 +01:00
Stefan Kalkowski
657646e76e hw: adjust core bootstrap to fit generic process
* Introduce hw-specific crt0 for core that calls e.g.: init_main_thread
* re-map core's main thread UTCB to fit the right context area location
* switch core's main thread's stack to fit the right context area location

Fix #1440
2015-03-19 08:57:19 +01:00
Stefan Kalkowski
7582396e9c hw_arndale: enable ARM virtualization extensions
* enables world-switch using ARM virtualization extensions
* split TrustZone and virtualization extensions hardly from platforms,
  where it is not used
* extend 'Vm_session' interface to enable configuration of guest-physical memory
* introduce VM destruction syscall
* add virtual machine monitor for hw_arndale that emulates a simplified version
  of ARM's Versatile Express Cortex A15 board for a Linux guest OS

Fixes #1405
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
07c8d1652e hw_arndale: setup ARM hypervisor mode
To enable support of hardware virtualization for ARM on the Arndale board,
the cpu needs to be prepared to enter the non-secure mode, as long as it does
not already run in it. Therefore, especially the interrupt controller and
some TrustZone specific system registers need to be prepared. Moreover,
the exception vector for the hypervisor needs to be set up properly, before
booting normally in the supervisor mode of the non-secure world.

Ref #1405
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
a40932a324 hw: refactor irq controllers
* name irq controller memory mapped I/O regions consistently
  in board descriptions
* move irq controller and timer memory mapped I/O region descriptions
  from cpu class to board class
* eliminate artificial distinction between flavors of ARM's GIC
* factor cpu local initialization out of ARM's GIC interface description,
  which is needed if the GIC is initialized differently e.g. for TrustZone

Ref #1405
2015-02-27 11:43:56 +01:00
Martin Stein
3a40c27c26 hw_vea9x4: quickfix slow RAM access
Setting the ACTLR.SMP bit also without SMP support fastens RAM access
significantly. A proper solution would implement SMP support which must enable
the bit anyway.

Fixes #1353
2015-02-17 14:18:16 +01:00
Stefan Kalkowski
322be1b4fb hw: LPAE for Cortex a15 (fix #1387) 2015-02-16 13:40:37 +01:00
Martin Stein
5dea0b40aa hw: don't use ARM CPU-state stuff in generic code
Fixes #1404
2015-02-16 13:40:36 +01:00
Martin Stein
63f8a38b5a hw: default boot-modules vpath is generic
Ref #1404
2015-02-16 13:40:36 +01:00
Stefan Kalkowski
a3abf74d1e hw: remove code duplication related to Exynos5 SoC
Fixes #1396
2015-02-16 13:40:36 +01:00
Stefan Kalkowski
901bff813d imx31: remove platform completely (fix #1360) 2015-01-12 14:24:15 +01:00
Martin Stein
9a4a0448be hw vea9x4: remove trustzone support
When building Genode for VEA9X4 as micro-hypervisor protected by the ARM
TrustZone hardware we ran into limitations regarding our basic daily
testing routines. The most significant is that, when speaking about RAM
partitioning, the only available options are to configure the whole SRAM
to be secure and the whole DDR-RAM to be non-secure or vice versa. The
SRAM however provides only 32 MB which isn't enough for both a
representative non-secure guest OS or a secure Genode that is still
capable of passing our basic tests. This initiated our decision to
remove the VEA9X4 TrustZone-support.

Fixes #1351
2015-01-08 13:28:42 +01:00
Martin Stein
b8ba3a7a22 hw: rename Kernel::Processor Kernel::Cpu
Kernel::Processor was a confusing remnant from the old scheme where we had a
Processor_driver (now Genode::Cpu) and a Processor (now Kernel::Cpu).
This commit also updates the in-code documentation and the variable and
function naming accordingly.

fix #1274
2014-11-28 12:02:35 +01:00
Martin Stein
b3655902ed hw & arm_v7: provide run/hw_info
The run test 'hw_info' prints the content of the basic ARMv7 identification and
feature registers in a pretty readable format. It is a kernel-internal test
because many of these registers are restricted to privilege level 1 or higher.

fix #1278
2014-11-28 12:02:35 +01:00
Martin Stein
0ab5310b8a hw: enable kernel-internal tests via run tool
Kernel tests are done by replacing the implementation of an otherwise
empty function 'Kernel::test' that gets called once at the primary CPU
as soon as all kernel initialization is done. To achieve this, the test
binary that implements 'Kernel::test' must be linked against the core
lib and must then replace the core binary when composing the boot image.
The latter can be done conveniently in a run script by setting the new
argument 'core_type' of the function 'build_boot_image' to the falue
'test'. If no kernel test is needed the argument does not have to be
given - it is set to 'core' by default which results in a "normal"
Genode image.

ref #1225
2014-11-28 12:02:34 +01:00
Martin Stein
b3bc9bd549 hw: idle execution context is no thread anymore
Previously, Idle_thread inherited from Thread which caused an extra
processor_pool.h and processor_pool.cc and also made class models for
processor and scheduling more complex. However, this inheritance makes
not much sense anyway as an idle context doesn't trigger most of the code
in Thread.

ref #1225
2014-11-28 12:02:34 +01:00
Stefan Kalkowski
f0fae2a5f2 hw: set TTBR0 according to CPU facilities
Fixes #1195
2014-10-10 13:02:30 +02:00
Martin Stein
9da42dde2f hw & arm_v7: mode transition via transit ttbr0
Previously, we did the protection-domain switches without a transitional
translation table that contains only global mappings. This was fine as long
as the CPU did no speculative memory accesses. However, to enabling branch
prediction triggers such accesses. Thus, if we don't want to invalidate
predictors on every context switch, we need to switch more carefully.

ref #474
2014-08-15 10:19:48 +02:00
Martin Stein
d48d0e7b43 hw: rename processor CPU
fix #1217
2014-08-15 10:19:48 +02:00
Martin Stein
1cba71208f hw: cpu_support to kernel/thread_base
ref #1217
2014-08-15 10:19:48 +02:00
Martin Stein
a5cf09fa6e hw: re-organize file structure
fix #1197
2014-08-15 10:19:48 +02:00
Martin Stein
6cb9559feb hw: core as library
The build config for core is now provided through libraries to enable
implicit config composition through specifiers and thereby avoid
consideration of inappropriate targets.

fix #1199
2014-07-24 10:18:06 +02:00
Christian Prochaska
078883fda3 base: interface for D- and I-cache synchronization
On ARM, when machine instructions get written into the data cache
(for example by a JIT compiler), one needs to make sure that the
instructions get written out to memory and read from memory into
the instruction cache before they get executed. This functionality
is usually provided by a kernel syscall and this patch adds a generic
interface for Genode applications to use it.

Fixes #1153.
2014-05-27 11:14:45 +02:00
Norman Feske
ca971bbfd8 Move repositories to 'repos/' subdirectory
This patch changes the top-level directory layout as a preparatory
step for improving the tools for managing 3rd-party source codes.
The rationale is described in the issue referenced below.

Issue #1082
2014-05-14 16:08:00 +02:00