hw_x86_64: Implement APIC-based PIC driver
The implementation initializes the Local APIC (LAPIC) of CPU 0 in xapic mode (mmio register access) and uses the I/O APIC to remap, mask and unmask hardware IRQs. The remapping offset of IRQs is 48. Also initialize the legacy PIC and mask all interrupts in order to disable it. For more information about LAPIC and I/O APIC see Intel SDM Vol. 3A, chapter 10 and the Intel 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) specification Set bit 9 in the RFLAGS register of user CPU context to enable interrupts on kernel- to usermode switch.
This commit is contained in:
Reto Buerki
Christian Helmuth
parent
557c96a9cb
commit
a21959fc26
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@ -14,6 +14,7 @@ SRC_S += spec/x86_64/kernel/crt0.s
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SRC_S += spec/x86_64/crt0.s
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# add C++ sources
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SRC_CC += spec/x86/pic.cc
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SRC_CC += spec/x86_64/kernel/thread_base.cc
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SRC_CC += spec/x86_64/idt.cc
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SRC_CC += spec/x86_64/tss.cc
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@ -14,6 +14,8 @@
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#ifndef _PIC_H_
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#define _PIC_H_
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#include <board.h>
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#include <util/mmio.h>
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namespace Genode
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{
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@ -24,14 +26,119 @@ namespace Genode
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}
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class Genode::Pic
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class Genode::Pic : public Mmio
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{
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private:
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/* Registers */
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struct EOI : Register<0x0b0, 32, true> { };
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struct Svr : Register<0x0f0, 32>
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{
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struct APIC_enable : Bitfield<8, 1> { };
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};
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/*
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* ISR register, see Intel SDM Vol. 3A, section 10.8.4. Each of the 8
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* 32-bit ISR values is followed by 12 bytes of padding.
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*/
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struct Isr : Register_array<0x100, 32, 8 * 4, 32> { };
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class Ioapic : public Mmio
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{
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private:
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uint8_t _irt_count;
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enum {
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/* Number of Redirection Table entries */
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IRTE_COUNT = 0x17,
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IRTE_BIT_POL = 13,
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IRTE_BIT_TRG = 15,
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IRTE_BIT_MASK = 16,
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/* Register selectors */
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IOAPICVER = 0x01,
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IOREDTBL = 0x10,
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};
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/* Create redirection table entry for given IRQ */
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uint64_t create_irt_entry(unsigned irq)
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{
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uint32_t entry = Board::VECTOR_REMAP_BASE + irq;
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if (irq > 15) {
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/* Use level-triggered, high-active mode for non-legacy
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* IRQs */
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entry |= 1 << IRTE_BIT_POL | 1 << IRTE_BIT_TRG;
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}
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return entry;
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}
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public:
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Ioapic() : Mmio(Board::MMIO_IOAPIC_BASE)
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{
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/* Remap all supported IRQs */
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for (unsigned i = 0; i <= IRTE_COUNT; i++) {
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write<Ioregsel>(IOREDTBL + 2 * i);
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write<Iowin>(create_irt_entry(i));
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}
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};
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/* Set/unset mask bit of IRTE for given vector */
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void toggle_mask(unsigned const vector, bool const set)
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{
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if (vector < Board::VECTOR_REMAP_BASE ||
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vector > Board::VECTOR_REMAP_BASE + IRTE_COUNT)
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return;
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write<Ioregsel>(IOREDTBL + (2 * (vector -
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Board::VECTOR_REMAP_BASE)));
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uint32_t val = read<Iowin>();
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if (set) {
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val |= 1 << IRTE_BIT_MASK;
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} else {
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val &= ~(1 << IRTE_BIT_MASK);
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}
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write<Iowin>(val);
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}
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/* Registers */
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struct Ioregsel : Register<0x00, 32> { };
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struct Iowin : Register<0x10, 32> { };
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};
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Ioapic _ioapic;
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/**
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* Determine lowest pending interrupt in ISR register
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*
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* \return index of first ISR bit set starting at index one, zero if no
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* bit is set.
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*/
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inline unsigned get_lowest_bit(void)
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{
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unsigned bit, vec_base = 0;
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for (unsigned i = 0; i < 8 * 4; i += 4) {
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bit = __builtin_ffs(read<Isr>(i));
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if (bit) {
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return vec_base + bit;
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}
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vec_base += 32;
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}
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return 0;
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}
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public:
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enum {
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/*
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* FIXME: dummy ipi value on non-SMP platform, should be removed
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* when SMP is an aspect of CPUs only compiled where necessary
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* when SMP is an aspect of CPUs only compiled where
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* necessary
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*/
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IPI = 255,
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NR_OF_IRQ = 256,
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@ -40,24 +147,23 @@ class Genode::Pic
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/**
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* Constructor
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*/
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Pic() { }
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Pic();
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void init_cpu_local() { }
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bool take_request(unsigned &irq);
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bool take_request(unsigned &irq) { return false; }
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void finish_request() { }
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void finish_request();
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void mask() { }
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void unmask(unsigned const i, unsigned) { }
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void unmask(unsigned const i, unsigned);
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void mask(unsigned const i) { }
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void mask(unsigned const i);
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/*
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* Dummies
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*/
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void init_cpu_local() { }
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bool is_ip_interrupt(unsigned, unsigned) { return false; }
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void trigger_ip_interrupt(unsigned) { }
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};
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@ -0,0 +1,67 @@
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#include <port_io.h>
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#include "pic.h"
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using namespace Genode;
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enum {
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PIC_CMD_MASTER = 0x20,
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PIC_CMD_SLAVE = 0xa0,
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PIC_DATA_MASTER = 0x21,
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PIC_DATA_SLAVE = 0xa1,
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};
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Pic::Pic() : Mmio(Board::MMIO_LAPIC_BASE)
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{
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/* Start initialization sequence in cascade mode */
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outb(PIC_CMD_MASTER, 0x11);
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outb(PIC_CMD_SLAVE, 0x11);
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/* ICW2: Master PIC vector offset (32) */
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outb(PIC_DATA_MASTER, 0x20);
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/* ICW2: Slave PIC vector offset (40) */
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outb(PIC_DATA_SLAVE, 0x28);
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/* ICW3: Tell Master PIC that there is a slave PIC at IRQ2 */
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outb(PIC_DATA_MASTER, 4);
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/* ICW3: Tell Slave PIC its cascade identity */
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outb(PIC_DATA_SLAVE, 2);
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/* ICW4: Enable 8086 mode */
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outb(PIC_DATA_MASTER, 0x01);
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outb(PIC_DATA_SLAVE, 0x01);
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/* Disable legacy pic */
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outb(PIC_DATA_SLAVE, 0xff);
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outb(PIC_DATA_MASTER, 0xff);
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/* Set bit 8 of the APIC spurious vector register (SVR) */
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write<Svr::APIC_enable>(1);
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}
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bool Pic::take_request(unsigned &irq)
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{
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irq = get_lowest_bit();
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if (!irq) {
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return false;
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}
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irq -= 1;
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return true;
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}
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void Pic::finish_request()
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{
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write<EOI>(0);
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}
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void Pic::unmask(unsigned const i, unsigned)
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{
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_ioapic.toggle_mask(i, false);
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}
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void Pic::mask(unsigned const i)
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{
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_ioapic.toggle_mask(i, true);
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}
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@ -204,9 +204,8 @@
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pushq $0x23
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pushq SP_OFFSET(%rax)
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/* Set I/O privilege level to 3 */
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orq $0x3000, FLAGS_OFFSET(%rax)
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btrq $9, FLAGS_OFFSET(%rax) /* XXX: Drop once interrupt handling is done */
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/* Set I/O privilege level to 3 and enable interrupts */
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orq $0x3200, FLAGS_OFFSET(%rax)
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pushq FLAGS_OFFSET(%rax)
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pushq $0x1b
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