hw: rename Kernel::Processor Kernel::Cpu

Kernel::Processor was a confusing remnant from the old scheme where we had a
Processor_driver (now Genode::Cpu) and a Processor (now Kernel::Cpu).
This commit also updates the in-code documentation and the variable and
function naming accordingly.

fix #1274
This commit is contained in:
Martin Stein 2014-10-10 16:13:52 +02:00 committed by Christian Helmuth
parent b3655902ed
commit b8ba3a7a22
48 changed files with 563 additions and 670 deletions

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@ -265,26 +265,21 @@ class Genode::Core_start_info
{
private:
unsigned _processor_id;
unsigned _cpu_id;
public:
/**
* Set-up valid core startup-message
*
* \param processor_id kernel name of the processor to start on
* Set-up valid core startup-message for starting on 'cpu'
*/
void init(unsigned const processor_id)
{
_processor_id = processor_id;
}
void init(unsigned const cpu) { _cpu_id = cpu; }
/***************
** Accessors **
***************/
unsigned processor_id() const { return _processor_id; }
unsigned cpu_id() const { return _cpu_id; }
};
class Genode::Native_utcb

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@ -54,7 +54,7 @@ SRC_CC += kernel/vm.cc
SRC_CC += kernel/signal_receiver.cc
SRC_CC += kernel/irq.cc
SRC_CC += kernel/pd.cc
SRC_CC += kernel/processor.cc
SRC_CC += kernel/cpu.cc
# add assembly sources
SRC_S += boot_modules.s

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@ -5,4 +5,4 @@
#
# configure multiprocessor mode
CC_OPT += -Wa,--defsym -Wa,PROCESSORS=$(PROCESSORS) -DPROCESSORS=$(PROCESSORS)
CC_OPT += -Wa,--defsym -Wa,NR_OF_CPUS=$(NR_OF_CPUS) -DNR_OF_CPUS=$(NR_OF_CPUS)

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@ -8,7 +8,7 @@
SPECS += hw platform_arndale
# configure multiprocessor mode
PROCESSORS = 2
NR_OF_CPUS = 2
# add repository relative paths
REP_INC_DIR += include/exynos5_uart

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@ -8,7 +8,7 @@
SPECS += hw platform_imx31 epit
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# set address where to link the text segment at
LD_TEXT_ADDR ?= 0x82000000

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@ -8,7 +8,7 @@
SPECS += hw platform_imx53 epit
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# set address where to link the text segment at
LD_TEXT_ADDR ?= 0x70010000

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@ -8,7 +8,7 @@
SPECS += hw platform_odroid_xu
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# add repository relative paths
REP_INC_DIR += include/exynos5_uart

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@ -8,7 +8,7 @@
SPECS += hw platform_panda
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# set address where to link the text segment at
LD_TEXT_ADDR ?= 0x81000000

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@ -8,7 +8,7 @@
SPECS += hw platform_pbxa9
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# set address where to link text segment at
LD_TEXT_ADDR ?= 0x70000000

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@ -8,7 +8,7 @@
SPECS += hw platform_rpi
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# set address where to link the text segment at
LD_TEXT_ADDR ?= 0x800000

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@ -8,7 +8,7 @@
SPECS += hw platform_vea9x4
# configure multiprocessor mode
PROCESSORS = 1
NR_OF_CPUS = 1
# set address where to link text segment at
LD_TEXT_ADDR ?= 0x01000000

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@ -26,10 +26,9 @@ namespace Genode
static void outer_cache_invalidate() { }
static void outer_cache_flush() { }
static void prepare_kernel() { }
static void secondary_processors_ip(void * const ip) { }
static void secondary_cpus_ip(void * const ip) { }
static bool is_smp() { return false; }
};
};
}
#endif /* _BOARD_H_ */

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@ -85,7 +85,7 @@ namespace Kernel
*
* Kernel and/or hardware may cache parts of a domain configuration. This
* function ensures that the in-memory state of the targeted domain gets
* processor locally effective.
* CPU-locally effective.
*/
inline void update_pd(unsigned const pd_id)
{
@ -137,7 +137,7 @@ namespace Kernel
* Start execution of a thread
*
* \param thread_id kernel name of the targeted thread
* \param cpu_id kernel name of the targeted processor
* \param cpu_id kernel name of the targeted CPU
* \param pd_id kernel name of the targeted domain
* \param utcb core local pointer to userland thread-context
*/
@ -287,7 +287,7 @@ namespace Kernel
* Create a virtual machine that is stopped initially
*
* \param dst memory donation for the VM object
* \param state location of the processor state of the VM
* \param state location of the CPU state of the VM
* \param signal_context_id kernel name of the signal context for VM events
*
* \retval >0 kernel name of the new VM

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@ -1,5 +1,5 @@
/*
* \brief A multiplexable common instruction processor
* \brief Class for kernel data that is needed to manage a specific CPU
* \author Martin Stein
* \author Stefan Kalkowski
* \date 2014-01-14
@ -12,8 +12,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _KERNEL__PROCESSOR_H_
#define _KERNEL__PROCESSOR_H_
#ifndef _KERNEL__CPU_H_
#define _KERNEL__CPU_H_
/* core includes */
#include <timer.h>
@ -31,9 +31,9 @@ namespace Kernel
class Cpu_job;
/**
* Ability to do a domain update on all processors
* Ability to do a domain update on all CPUs
*/
class Processor_domain_update;
class Cpu_domain_update;
/**
* Execution context that is scheduled on CPU idle
@ -41,37 +41,37 @@ namespace Kernel
class Cpu_idle;
/**
* A multiplexable common instruction processor
* Class for kernel data that is needed to manage a specific CPU
*/
class Processor;
class Cpu;
/**
* Provides a processor object for every available processor
* Provides a CPU object for every available CPU
*/
class Processor_pool;
class Cpu_pool;
/**
* Return Processor_pool singleton
* Return singleton of CPU pool
*/
Processor_pool * processor_pool();
Cpu_pool * cpu_pool();
}
class Kernel::Processor_domain_update : public Double_list_item
class Kernel::Cpu_domain_update : public Double_list_item
{
friend class Processor_domain_update_list;
friend class Cpu_domain_update_list;
private:
bool _pending[PROCESSORS];
bool _pending[NR_OF_CPUS];
unsigned _domain_id;
/**
* Domain-update back-end
*/
void _domain_update() { Cpu::flush_tlb_by_pid(_domain_id); }
void _domain_update() { Genode::Cpu::flush_tlb_by_pid(_domain_id); }
/**
* Perform the domain update on the executing processors
* Perform the domain update on the executing CPU
*/
void _do();
@ -80,73 +80,63 @@ class Kernel::Processor_domain_update : public Double_list_item
/**
* Constructor
*/
Processor_domain_update()
Cpu_domain_update()
{
for (unsigned i = 0; i < PROCESSORS; i++) { _pending[i] = false; }
for (unsigned i = 0; i < NR_OF_CPUS; i++) { _pending[i] = false; }
}
/**
* Perform the domain update on all processors
*
* \param domain_id kernel name of targeted domain
*
* \return wether the update blocks and reports back on completion
* Do an update of domain 'id' on all CPUs and return if this blocks
*/
bool _do_global(unsigned const domain_id);
bool _do_global(unsigned const id);
/**
* Notice that the update isn't pending on any processor anymore
* Notice that the update isn't pending on any CPU anymore
*/
virtual void _processor_domain_update_unblocks() = 0;
virtual void _cpu_domain_update_unblocks() = 0;
};
class Kernel::Cpu_job : public Cpu_share
{
protected:
Processor * _cpu;
Cpu * _cpu;
Cpu_lazy_state _lazy_state;
/**
* Handle an interrupt exception that occured during execution
*
* \param processor_id kernel name of targeted processor
* Handle interrupt exception that occured during execution on CPU 'id'
*/
void _interrupt(unsigned const processor_id);
void _interrupt(unsigned const id);
/**
* Insert context into the processor scheduling
* Insert context into the scheduling of this CPU
*/
void _schedule();
/**
* Remove context from the processor scheduling
* Remove context from the scheduling of this CPU
*/
void _unschedule();
/**
* Yield currently scheduled processor share of the context
* Yield the currently scheduled CPU share of this context
*/
void _yield();
public:
/**
* Handle an exception that occured during execution
*
* \param processor_id kernel name of targeted processor
* Handle exception that occured during execution on CPU 'id'
*/
virtual void exception(unsigned const processor_id) = 0;
virtual void exception(unsigned const id) = 0;
/**
* Continue execution
*
* \param processor_id kernel name of targeted processor
* Continue execution on CPU 'id'
*/
virtual void proceed(unsigned const processor_id) = 0;
virtual void proceed(unsigned const id) = 0;
/**
* Construct a job with scheduling priority 'prio'
* Construct a job with scheduling priority 'p'
*/
Cpu_job(Cpu_priority const p) : Cpu_share(p, 0), _cpu(0) { }
@ -158,17 +148,17 @@ class Kernel::Cpu_job : public Cpu_share
/**
* Link job to CPU 'cpu'
*/
void affinity(Processor * const cpu);
void affinity(Cpu * const cpu);
/***************
** Accessors **
***************/
void cpu(Processor * const cpu) { _cpu = cpu; }
void cpu(Cpu * const cpu) { _cpu = cpu; }
Cpu_lazy_state * lazy_state() { return &_lazy_state; }
};
class Kernel::Cpu_idle : public Cpu::User_context, public Cpu_job
class Kernel::Cpu_idle : public Genode::Cpu::User_context, public Cpu_job
{
private:
@ -179,14 +169,14 @@ class Kernel::Cpu_idle : public Cpu::User_context, public Cpu_job
/**
* Main function of all idle threads
*/
static void _main() { while (1) { Cpu::wait_for_interrupt(); } }
static void _main() { while (1) { Genode::Cpu::wait_for_interrupt(); } }
public:
/**
* Construct idle context for CPU 'cpu'
*/
Cpu_idle(Processor * const cpu);
Cpu_idle(Cpu * const cpu);
/**
* Handle exception that occured during execution on CPU 'cpu'
@ -206,7 +196,7 @@ class Kernel::Cpu_idle : public Cpu::User_context, public Cpu_job
void proceed(unsigned const cpu_id);
};
class Kernel::Processor : public Cpu
class Kernel::Cpu : public Genode::Cpu
{
private:
@ -227,7 +217,7 @@ class Kernel::Processor : public Cpu
/**
* Construct object for CPU 'id' with scheduling timer 'timer'
*/
Processor(unsigned const id, Timer * const timer)
Cpu(unsigned const id, Timer * const timer)
:
_id(id), _idle(this), _timer(timer),
_scheduler(&_idle, _quota(), _fill()),
@ -239,12 +229,12 @@ class Kernel::Processor : public Cpu
bool timer_irq(unsigned const i) { return _timer->interrupt_id(_id) == i; }
/**
* Notice that the inter-processor interrupt isn't pending anymore
* Notice that the IPI of the CPU isn't pending anymore
*/
void ip_interrupt_handled() { _ip_interrupt_pending = false; }
/**
* Raise the inter-processor interrupt of the processor
* Raise the IPI of the CPU
*/
void trigger_ip_interrupt();
@ -254,7 +244,7 @@ class Kernel::Processor : public Cpu
void schedule(Job * const job);
/**
* Handle exception of the processor and proceed its user execution
* Handle recent exception of the CPU and proceed its user execution
*/
void exception()
{
@ -291,39 +281,38 @@ class Kernel::Processor : public Cpu
Cpu_scheduler * scheduler() { return &_scheduler; }
};
class Kernel::Processor_pool
class Kernel::Cpu_pool
{
private:
Timer _timer;
char _processors[PROCESSORS][sizeof(Processor)];
char _cpus[NR_OF_CPUS][sizeof(Cpu)];
public:
/**
* Constructor
* Construct pool and thereby objects for all available CPUs
*/
Processor_pool()
Cpu_pool()
{
for (unsigned id = 0; id < PROCESSORS; id++) {
new (_processors[id]) Processor(id, &_timer); }
for (unsigned id = 0; id < NR_OF_CPUS; id++) {
new (_cpus[id]) Cpu(id, &_timer); }
}
/**
* Return the kernel object of processor 'id'
* Return object of CPU 'id'
*/
Processor * processor(unsigned const id) const
Cpu * cpu(unsigned const id) const
{
assert(id < PROCESSORS);
char * const p = const_cast<char *>(_processors[id]);
return reinterpret_cast<Processor *>(p);
assert(id < NR_OF_CPUS);
char * const p = const_cast<char *>(_cpus[id]);
return reinterpret_cast<Cpu *>(p);
}
/**
* Return the object of the primary processor
* Return object of primary CPU
*/
Processor * primary_processor() const {
return processor(Processor::primary_id()); }
Cpu * primary_cpu() const { return cpu(Cpu::primary_id()); }
};
#endif /* _KERNEL__PROCESSOR_H_ */
#endif /* _KERNEL__CPU_H_ */

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@ -23,7 +23,7 @@
#include <kernel/early_translations.h>
#include <kernel/configuration.h>
#include <kernel/object.h>
#include <kernel/processor.h>
#include <kernel/cpu.h>
#include <translation_table.h>
#include <assert.h>
@ -77,7 +77,7 @@ class Kernel::Lock
namespace Kernel
{
/**
* Processor context of the kernel
* CPU context of the kernel
*/
class Cpu_context;
@ -179,16 +179,16 @@ class Kernel::Mode_transition_control
/**
* Continue execution of client context
*
* \param context targeted client processor-context
* \param processor_id kernel name of targeted processor
* \param entry_raw raw pointer to assembly entry-code
* \param context targeted CPU context
* \param cpu kernel name of targeted CPU
* \param entry_raw raw pointer to assembly entry-code
*/
void _continue_client(void * const context, unsigned const processor_id,
void _continue_client(void * const context, unsigned const cpu,
addr_t const entry_raw)
{
/* override client-context pointer of the executing processor */
/* override client-context pointer of the executing CPU */
addr_t const context_ptr_base = (addr_t)&_mt_client_context_ptr;
size_t const context_ptr_offset = processor_id * sizeof(context);
size_t const context_ptr_offset = cpu * sizeof(context);
addr_t const context_ptr = context_ptr_base + context_ptr_offset;
*(void * *)context_ptr = context;
@ -206,7 +206,7 @@ class Kernel::Mode_transition_control
enum {
SIZE_LOG2 = Genode::Translation_table::MIN_PAGE_SIZE_LOG2,
SIZE = 1 << SIZE_LOG2,
VIRT_BASE = Processor::exception_entry,
VIRT_BASE = Cpu::exception_entry,
ALIGN_LOG2 = Genode::Translation_table::ALIGNM_LOG2,
ALIGN = 1 << ALIGN_LOG2,
};
@ -236,28 +236,16 @@ class Kernel::Mode_transition_control
}
/**
* Continue execution of userland context
*
* \param context targeted userland context
* \param processor_id kernel name of targeted processor
* Continue execution of 'user' at 'cpu'
*/
void continue_user(Processor::Context * const context,
unsigned const processor_id)
{
_continue_client(context, processor_id, _virt_user_entry());
}
void continue_user(Cpu::Context * const user, unsigned const cpu) {
_continue_client(user, cpu, _virt_user_entry()); }
/**
* Continue execution of virtual machine
*
* \param context targeted virtual-machine context
* \param processor_id kernel name of targeted processor
* Continue execution of 'vm' at 'cpu'
*/
void continue_vm(Cpu_state_modes * const context,
unsigned const processor_id)
{
_continue_client(context, processor_id, (addr_t)&_mt_vm_entry_pic);
}
void continue_vm(Cpu_state_modes * const vm, unsigned const cpu) {
_continue_client(vm, cpu, (addr_t)&_mt_vm_entry_pic); }
} __attribute__((aligned(Mode_transition_control::ALIGN)));
@ -290,7 +278,7 @@ class Kernel::Pd : public Object<Pd, MAX_PDS, Pd_ids, pd_ids, pd_pool>
/**
* Let the CPU context 'c' join the PD
*/
void admit(Processor::Context * const c)
void admit(Cpu::Context * const c)
{
c->protection_domain(id());
c->translation_table((addr_t)translation_table());

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@ -18,7 +18,7 @@
#include <kernel/configuration.h>
#include <kernel/signal_receiver.h>
#include <kernel/ipc_node.h>
#include <kernel/processor.h>
#include <kernel/cpu.h>
#include <kernel/thread_base.h>
namespace Kernel
@ -44,12 +44,8 @@ class Kernel::Thread
:
public Cpu::User_context,
public Object<Thread, MAX_THREADS, Thread_ids, thread_ids, thread_pool>,
public Cpu_job,
public Processor_domain_update,
public Ipc_node,
public Signal_context_killer,
public Signal_handler,
public Thread_base
public Cpu_job, public Cpu_domain_update, public Ipc_node,
public Signal_context_killer, public Signal_handler, public Thread_base
{
friend class Thread_event;
@ -262,11 +258,11 @@ class Kernel::Thread
void _await_request_failed();
/*****************************
** Processor_domain_update **
*****************************/
/***********************
** Cpu_domain_update **
***********************/
void _processor_domain_update_unblocks() { _resume(); }
void _cpu_domain_update_unblocks() { _resume(); }
public:
@ -281,21 +277,21 @@ class Kernel::Thread
/**
* Prepare thread to get scheduled the first time
*
* \param processor targeted processor
* \param pd targeted domain
* \param utcb core local pointer to userland thread-context
* \param start wether to start executing the thread
* \param cpu targeted CPU
* \param pd targeted domain
* \param utcb core local pointer to userland thread-context
* \param start wether to start executing the thread
*/
void init(Processor * const processor, Pd * const pd,
Native_utcb * const utcb, bool const start);
void init(Cpu * const cpu, Pd * const pd, Native_utcb * const utcb,
bool const start);
/*************
** Cpu_job **
*************/
void exception(unsigned const processor_id);
void proceed(unsigned const processor_id);
void exception(unsigned const cpu);
void proceed(unsigned const cpu);
/***************

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@ -61,7 +61,7 @@ class Kernel::Vm : public Object<Vm, MAX_VMS, Vm_ids, vm_ids, vm_pool>,
:
Cpu_job(Cpu_priority::min), _state((Vm_state * const)state),
_context(context)
{ Cpu_job::affinity(processor_pool()->primary_processor()); }
{ affinity(cpu_pool()->primary_cpu()); }
/****************
@ -69,7 +69,6 @@ class Kernel::Vm : public Object<Vm, MAX_VMS, Vm_ids, vm_ids, vm_pool>,
****************/
void run() { Cpu_job::_schedule(); }
void pause() { Cpu_job::_unschedule(); }
@ -77,25 +76,22 @@ class Kernel::Vm : public Object<Vm, MAX_VMS, Vm_ids, vm_ids, vm_pool>,
** Cpu_job **
*************/
void exception(unsigned const processor_id)
void exception(unsigned const cpu)
{
switch(_state->cpu_exception) {
case Genode::Cpu_state::INTERRUPT_REQUEST:
case Genode::Cpu_state::FAST_INTERRUPT_REQUEST:
_interrupt(processor_id);
_interrupt(cpu);
return;
case Genode::Cpu_state::DATA_ABORT:
_state->dfar = Processor::Dfar::read();
_state->dfar = Cpu::Dfar::read();
default:
Cpu_job::_unschedule();
_context->submit(1);
}
}
void proceed(unsigned const processor_id)
{
mtc()->continue_vm(_state, processor_id);
}
void proceed(unsigned const cpu) { mtc()->continue_vm(_state, cpu); }
};
#endif /* _KERNEL__VM_H_ */

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@ -36,58 +36,60 @@ namespace Genode {
*/
class Platform : public Platform_generic
{
typedef Core_mem_allocator::Phys_allocator Phys_allocator;
private:
Core_mem_allocator _core_mem_alloc; /* core-accessible memory */
Phys_allocator _io_mem_alloc; /* MMIO allocator */
Phys_allocator _irq_alloc; /* IRQ allocator */
Rom_fs _rom_fs; /* ROM file system */
typedef Core_mem_allocator::Phys_allocator Phys_allocator;
/*
* Virtual-memory range for non-core address spaces.
* The virtual memory layout of core is maintained in
* '_core_mem_alloc.virt_alloc()'.
*/
addr_t _vm_start;
size_t _vm_size;
Core_mem_allocator _core_mem_alloc; /* core-accessible memory */
Phys_allocator _io_mem_alloc; /* MMIO allocator */
Phys_allocator _irq_alloc; /* IRQ allocator */
Rom_fs _rom_fs; /* ROM file system */
/*
* Virtual-memory range for non-core address spaces.
* The virtual memory layout of core is maintained in
* '_core_mem_alloc.virt_alloc()'.
*/
addr_t _vm_start;
size_t _vm_size;
public:
/**
* Get one of the consecutively numbered available resource regions
*
* \return >0 region pointer if region with index 'i' exists
* 0 if region with index 'i' doesn't exist
*
* These functions should provide all ressources that are available
* on the current platform.
*/
static Native_region * _ram_regions(unsigned i);
static Native_region * _mmio_regions(unsigned i);
/**
* Get one of the consecutively numbered available resource regions
*
* \return >0 region pointer if region with index 'i' exists
* 0 if region with index 'i' doesn't exist
*
* These functions should provide all ressources that are available
* on the current platform.
*/
static Native_region * _ram_regions(unsigned i);
static Native_region * _mmio_regions(unsigned i);
/**
* Get one of the consecutively numbered core regions
*
* \return >0 Region pointer if region with index 'i' exists
* 0 If region with index 'i' doesn't exist
*
* Core regions are address regions that must be permitted to
* core only, such as the core image ROM. These regions are normally
* a subset of the ressource regions provided above.
*/
static Native_region * _core_only_ram_regions(unsigned i);
static Native_region * _core_only_mmio_regions(unsigned i);
/**
* Get one of the consecutively numbered core regions
*
* \return >0 Region pointer if region with index 'i' exists
* 0 If region with index 'i' doesn't exist
*
* Core regions are address regions that must be permitted to
* core only, such as the core image ROM. These regions are
* normally a subset of the ressource regions provided above.
*/
static Native_region * _core_only_ram_regions(unsigned i);
static Native_region * _core_only_mmio_regions(unsigned i);
/**
* Get one of the consecutively numbered user interrupts
*
* \param i index of interrupt
*
* \return >0 pointer to the name of the requested interrupt
* 0 no interrupt for that index
*/
static unsigned * _irq(unsigned const i);
/**
* Get one of the consecutively numbered user interrupts
*
* \param i index of interrupt
*
* \return >0 pointer to the name of the requested interrupt
* 0 no interrupt for that index
*/
static unsigned * _irq(unsigned const i);
/**
* Constructor
@ -120,17 +122,13 @@ namespace Genode {
inline Rom_fs *rom_fs() { return &_rom_fs; }
inline void wait_for_exit()
{
while (1) { Kernel::pause_current_thread(); }
};
inline void wait_for_exit() {
while (1) { Kernel::pause_current_thread(); } };
bool supports_direct_unmap() const { return 1; }
Affinity::Space affinity_space() const
{
return Affinity::Space(PROCESSORS);
}
Affinity::Space affinity_space() const {
return Affinity::Space(NR_OF_CPUS); }
};
}

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@ -19,10 +19,10 @@
*/
.macro _init_kernel_sp base_reg, size_reg
/* get kernel name of processor */
_get_processor_id sp
/* get kernel name of CPU */
_get_cpu_id sp
/* calculate top of the kernel-stack of this processor and apply as SP */
/* calculate top of the kernel-stack of this CPU and apply as SP */
add sp, #1
mul \size_reg, \size_reg, sp
add sp, \base_reg, \size_reg

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@ -32,7 +32,7 @@
.set IRQ_PC_ADJUST, 4
.set FIQ_PC_ADJUST, 4
/* offsets of the member variables in a processor context */
/* offsets of the member variables in a CPU context */
.set R12_OFFSET, 12 * 4
.set SP_OFFSET, 13 * 4
.set LR_OFFSET, 14 * 4
@ -61,19 +61,19 @@
.global _mt_master_context_end
_mt_master_context_end:
/* space for a client context-pointer per processor */
/* space for a client context-pointer per CPU */
.p2align 2
.global _mt_client_context_ptr
_mt_client_context_ptr:
.rept PROCESSORS
.rept NR_OF_CPUS
.space CONTEXT_PTR_SIZE
.endr
/* a globally mapped buffer per processor */
/* a globally mapped buffer per CPU */
.p2align 2
.global _mt_buffer
_mt_buffer:
.rept PROCESSORS
.rept NR_OF_CPUS
.space BUFFER_SIZE
.endr

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@ -432,7 +432,7 @@ class Genode::Translation_table
pt_phys = pt_phys ? pt_phys : pt; /* hack for core */
_entries[i] = Page_table_descriptor::create(pt_phys);
/* some processors need to act on changed translations */
/* some CPUs need to act on changed translations */
size_t const dsize = sizeof(Descriptor::access_t);
Cpu::translation_added((addr_t)&_entries[i], dsize);
}

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@ -78,7 +78,7 @@ class Genode::Arm_gic_distributor : public Mmio
struct Priority : Bitfield<0, 8> { }; };
/**
* Interrupt processor target registers
* Interrupt CPU-target registers
*/
struct Itargetsr : Register_array<0x800, 32, nr_of_irq, 8> {
struct Cpu_targets : Bitfield<0, 8> { }; };
@ -214,7 +214,7 @@ class Genode::Arm_gic
/**
* Initialize CPU local interface of the controller
*/
void init_processor_local()
void init_cpu_local()
{
/* disable the priority filter */
_cpui.write<Cpui::Pmr::Priority>(_distr.min_priority());

View File

@ -33,11 +33,7 @@ namespace Genode
class Cpu;
}
namespace Kernel
{
using Genode::Cpu_lazy_state;
using Genode::Cpu;
}
namespace Kernel { using Genode::Cpu_lazy_state; }
class Genode::Cpu : public Arm
{
@ -141,7 +137,7 @@ class Genode::Cpu : public Arm
*/
static void tlb_insertions() { flush_tlb(); }
static void start_secondary_processors(void *) { assert(!Board::is_smp()); }
static void start_secondary_cpus(void *) { assert(!Board::is_smp()); }
/**
* Return wether to retry an undefined user instruction after this call
@ -157,7 +153,7 @@ class Genode::Cpu : public Arm
static void translation_added(addr_t const addr, size_t const size)
{
/*
* The Cortex A8 processor can't use the L1 cache on page-table
* The Cortex-A8 CPU can't use the L1 cache on page-table
* walks. Therefore, as the page-tables lie in write-back cacheable
* memory we've to clean the corresponding cache-lines even when a
* page table entry is added. We only do this as core as the kernel
@ -167,12 +163,12 @@ class Genode::Cpu : public Arm
}
/**
* Return kernel name of the executing processor
* Return kernel name of the executing CPU
*/
static unsigned executing_id();
/**
* Return kernel name of the primary processor
* Return kernel name of the primary CPU
*/
static unsigned primary_id();

View File

@ -15,12 +15,10 @@
.include "spec/arm/macros_support.s"
/**
* Determine the kernel name of the executing processor
*
* \param target_reg register that shall receive the processor name
* Load kernel name of the executing CPU into register 'r'
*/
.macro _get_processor_id target_reg
.macro _get_cpu_id r
/* no multiprocessing supported for ARMv6 */
mov \target_reg, #0
mov \r, #0
.endm

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@ -292,12 +292,12 @@ class Genode::Arm_v7 : public Arm
static void data_synchronization_barrier() { asm volatile ("dsb"); }
/**
* Enable secondary processors with instr. pointer 'ip'
* Enable secondary CPUs with instr. pointer 'ip'
*/
static void start_secondary_processors(void * const ip)
static void start_secondary_cpus(void * const ip)
{
if (!(PROCESSORS > 1)) { return; }
Board::secondary_processors_ip(ip);
if (!(NR_OF_CPUS > 1)) { return; }
Board::secondary_cpus_ip(ip);
data_synchronization_barrier();
asm volatile ("sev\n");
}

View File

@ -15,15 +15,13 @@
.include "spec/arm/macros_support.s"
/**
* Determine the kernel name of the executing processor
*
* \param target_reg register that shall receive the processor name
* Load kernel name of the executing CPU into register 'r'
*/
.macro _get_processor_id target_reg
.macro _get_cpu_id r
/* read the multiprocessor affinity register */
mrc p15, 0, \target_reg, c0, c0, 5
mrc p15, 0, \r, c0, c0, 5
/* get the affinity-0 bitfield from the read register value */
and \target_reg, \target_reg, #0xff
and \r, \r, #0xff
.endm

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@ -28,14 +28,10 @@ namespace Genode
static void prepare_kernel() { }
/**
* Tell secondary processors where to start execution from
*
* \param ip initial instruction pointer of secondary processors
* Tell secondary CPUs to start execution from instr. pointer 'ip'
*/
static void secondary_processors_ip(void * const ip)
{
*(void * volatile *)IRAM_BASE = ip;
}
static void secondary_cpus_ip(void * const ip) {
*(void * volatile *)IRAM_BASE = ip; }
static bool is_smp() { return true; }
};

View File

@ -30,11 +30,7 @@ namespace Genode
class Cpu;
}
namespace Kernel
{
using Genode::Cpu_lazy_state;
using Genode::Cpu;
}
namespace Kernel { using Genode::Cpu_lazy_state; }
class Genode::Cpu : public Arm_v7
{
@ -46,12 +42,12 @@ class Genode::Cpu : public Arm_v7
bool retry_undefined_instr(Cpu_lazy_state *) { return false; }
/**
* Return kernel name of the executing processor
* Return kernel name of the executing CPU
*/
static unsigned executing_id();
/**
* Return kernel name of the primary processor
* Return kernel name of the primary CPU
*/
static unsigned primary_id();

View File

@ -30,11 +30,7 @@ namespace Genode
class Cpu;
}
namespace Kernel
{
using Genode::Cpu_lazy_state;
using Genode::Cpu;
}
namespace Kernel { using Genode::Cpu_lazy_state; }
class Genode::Cpu : public Arm_v7
{
@ -59,7 +55,7 @@ class Genode::Cpu : public Arm_v7
static void translation_added(addr_t const addr, size_t const size)
{
/*
* The Cortex A8 processor can't use the L1 cache on page-table
* The Cortex-A8 CPU can't use the L1 cache on page-table
* walks. Therefore, as the page-tables lie in write-back cacheable
* memory we've to clean the corresponding cache-lines even when a
* page table entry is added. We only do this as core as the kernel
@ -69,12 +65,12 @@ class Genode::Cpu : public Arm_v7
}
/**
* Return kernel name of the executing processor
* Return kernel name of the executing CPU
*/
static unsigned executing_id();
/**
* Return kernel name of the primary processor
* Return kernel name of the primary CPU
*/
static unsigned primary_id();

View File

@ -31,11 +31,7 @@ namespace Genode
class Cpu;
}
namespace Kernel
{
using Genode::Cpu_lazy_state;
using Genode::Cpu;
}
namespace Kernel { using Genode::Cpu_lazy_state; }
class Genode::Cpu_lazy_state
{
@ -167,9 +163,7 @@ class Genode::Cpu : public Arm_v7
}
/**
* Save state of the advanced FP/SIMD extension to memory
*
* \param state processor state to save FP/SIMD state into
* Save state of the advanced FP/SIMD extension into 'state'
*/
static void _save_advanced_fp_simd_state(Cpu_lazy_state * const state)
{
@ -189,9 +183,7 @@ class Genode::Cpu : public Arm_v7
}
/**
* Load state of the advanced FP/SIMD extension from memory
*
* \param state processor state to load FP/SIMD state out of
* Load state of the advanced FP/SIMD extension from 'state'
*/
static void _load_advanced_fp_simd_state(Cpu_lazy_state * const state)
{
@ -259,8 +251,8 @@ class Genode::Cpu : public Arm_v7
/**
* Prepare for the proceeding of a user
*
* \param old_state processor state of the last user
* \param new_state processor state of the next user
* \param old_state CPU state of the last user
* \param new_state CPU state of the next user
*/
static void prepare_proceeding(Cpu_lazy_state * const old_state,
Cpu_lazy_state * const new_state)
@ -272,7 +264,7 @@ class Genode::Cpu : public Arm_v7
/**
* Return wether to retry an undefined user instruction after this call
*
* \param state processor state of the user
* \param state CPU state of the user
*/
bool retry_undefined_instr(Cpu_lazy_state * const state)
{
@ -289,12 +281,12 @@ class Genode::Cpu : public Arm_v7
}
/**
* Return kernel name of the executing processor
* Return kernel name of the executing CPU
*/
static unsigned executing_id();
/**
* Return kernel name of the primary processor
* Return kernel name of the primary CPU
*/
static unsigned primary_id();

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@ -188,13 +188,11 @@ class Genode::Timer : public Mmio
/**
* Return kernel name of timer interrupt of a specific processor
*
* \param processor_id kernel name of targeted processor
* Return kernel name of the interrupt of the timer of CPU 'cpu'
*/
static unsigned interrupt_id(unsigned const processor_id)
static unsigned interrupt_id(unsigned const cpu)
{
switch (processor_id) {
switch (cpu) {
case 0: return Board::MCT_IRQ_L0;
case 1: return Board::MCT_IRQ_L1;
default: return 0;
@ -218,15 +216,11 @@ class Genode::Timer : public Mmio
}
/**
* Start single timeout run
*
* \param tics delay of timer interrupt
* \param processor_id kernel name of processor of targeted timer
* Raise interrupt of CPU 'cpu' once after timeout 'tics'
*/
inline void start_one_shot(unsigned const tics,
unsigned const processor_id)
inline void start_one_shot(unsigned const tics, unsigned const cpu)
{
switch (processor_id) {
switch (cpu) {
case 0:
write<L0_int_cstat::Frcnt>(1);
_run_0(0);
@ -248,9 +242,9 @@ class Genode::Timer : public Mmio
*/
unsigned ms_to_tics(unsigned const ms) { return ms * _tics_per_ms; }
unsigned value(unsigned const processor_id)
unsigned value(unsigned const cpu)
{
switch (processor_id) {