hw & arm_v7: provide run/hw_info
The run test 'hw_info' prints the content of the basic ARMv7 identification and feature registers in a pretty readable format. It is a kernel-internal test because many of these registers are restricted to privilege level 1 or higher. fix #1278
This commit is contained in:
Martin Stein
Christian Helmuth
parent
1b1fd1e1f9
commit
b3655902ed
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#
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# \brief Build config for a core that prints hardware information
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# \author Martin Stein
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# \date 2011-12-16
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#
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# add C++ sources
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SRC_CC += spec/arm_v7/info.cc
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# decrlare source directories
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vpath % $(REP_DIR)/src/test/hw_info
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@ -0,0 +1,20 @@
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#
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# \brief Print some useful information on the underlying hardware
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# \author Martin Stein
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# \date 2014-10-21
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#
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# build program images
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build "test/hw_info"
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# create directory where the boot files are written to
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create_boot_directory
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# create single boot image from the compiled program images
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build_boot_image "test-hw_info" test
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# configure qemu to use 64 MB RAM and avoid GUI mode
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append qemu_args " -m 64 -nographic"
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# execute the test in qemu if the targeted platform is supported
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run_genode_until "------ End ------.*\n" 60
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/*
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* \brief Provide detailed hardware Information
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* \author Martin Stein
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* \date 2014-10-20
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*/
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/*
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* Copyright (C) 2014 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* base includes */
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#include <base/printf.h>
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using namespace Genode;
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namespace Kernel { void test(); }
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void info();
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/**
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* Main routine
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*/
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void Kernel::test()
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{
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printf("\n");
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info();
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printf("------ End ------\n");
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while (1) ;
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}
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@ -0,0 +1,427 @@
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/*
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* \brief Provide detailed hardware Information
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* \author Martin Stein
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* \date 2014-10-20
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*/
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/*
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* Copyright (C) 2014 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* base includes */
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#include <util/register.h>
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#include <base/printf.h>
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using namespace Genode;
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struct Reg_32_8: Register<32>
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{
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struct B0 : Bitfield<0,4> { };
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struct B1 : Bitfield<4,4> { };
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struct B2 : Bitfield<8,4> { };
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struct B3 : Bitfield<12,4> { };
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struct B4 : Bitfield<16,4> { };
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struct B5 : Bitfield<20,4> { };
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struct B6 : Bitfield<24,4> { };
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struct B7 : Bitfield<28,4> { };
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};
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struct Id_pfr1 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c1, 1" : "=r" (v) :: );
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return v;
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}
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};
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struct Id_mmfr0 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c1, 4" : "=r" (v) :: );
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return v;
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}
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};
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struct Id_mmfr1 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c1, 5" : "=r" (v) :: );
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return v;
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}
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};
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struct Id_mmfr2 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c1, 6" : "=r" (v) :: );
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return v;
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}
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};
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struct Id_mmfr3 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c1, 7" : "=r" (v) :: );
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return v;
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}
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};
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struct Id_pfr0 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c1, 0" : "=r" (v) :: );
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return v;
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}
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};
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struct Ctr : Register<32>
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{
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struct Iminline : Bitfield<0,4> { };
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struct L1ip : Bitfield<14,2> { };
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struct Dminline : Bitfield<16,4> { };
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struct Erg : Bitfield<20,4> { };
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struct Cgw : Bitfield<24,4> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (v) :: );
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return v;
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}
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};
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struct Ccsidr : Register<32>
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{
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struct Line_size : Bitfield<0,3> { };
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struct Associativity : Bitfield<3,10> { };
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struct Num_sets : Bitfield<13,15> { };
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struct Wa : Bitfield<28,1> { };
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struct Ra : Bitfield<29,1> { };
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struct Wb : Bitfield<30,1> { };
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struct Wt : Bitfield<31,1> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (v) :: );
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return v;
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}
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};
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struct Clidr : Register<32>
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{
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struct Ctype1 : Bitfield<0,3> { };
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struct Ctype2 : Bitfield<3,3> { };
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struct Ctype3 : Bitfield<6,3> { };
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struct Ctype4 : Bitfield<9,3> { };
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struct Ctype5 : Bitfield<12,3> { };
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struct Ctype6 : Bitfield<15,3> { };
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struct Ctype7 : Bitfield<18,3> { };
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struct Louis : Bitfield<21,3> { };
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struct Loc : Bitfield<24,3> { };
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struct Louu : Bitfield<27,3> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (v) :: );
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return v;
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}
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};
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struct Fpsid : Register<32>
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{
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struct Revision : Bitfield<0,4> { };
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struct Variant : Bitfield<4,4> { };
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struct Part_number : Bitfield<8,8> { };
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struct Subarchitecture : Bitfield<16,7> { };
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struct Sw : Bitfield<23,1> { };
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struct Implementer : Bitfield<24,8> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p10, 7, %0, cr0, cr0" : "=r" (v) :: );
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return v;
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}
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};
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struct Mvfr0 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p10, 7, %0, cr7, cr0" : "=r" (v) :: );
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return v;
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}
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};
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struct Mvfr1 : Reg_32_8
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{
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p10, 7, %0, cr6, cr0" : "=r" (v));
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return v;
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}
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};
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struct Mpidr : Register<32>
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{
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struct Mp : Bitfield<31,1> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (v) :: );
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return v;
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}
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};
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struct Tlbtr : Register<32>
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{
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struct Nu : Bitfield<0,1> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c0, 3" : "=r" (v) :: );
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return v;
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}
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};
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struct Midr : Register<32>
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{
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struct Revision : Bitfield<0,4> { };
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struct Primary_part_number : Bitfield<4,12> { };
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struct Architecture : Bitfield<16,4> { };
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struct Variant : Bitfield<20,4> { };
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struct Implementer : Bitfield<24,8> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (v) :: );
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return v;
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}
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};
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struct Csselr : Register<32>
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{
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struct Ind : Bitfield<0,1> { };
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struct Level : Bitfield<1,3> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (v) :: );
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return v;
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}
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static void write(access_t const v) {
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" :: "r" (v) : ); }
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};
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void info_ccsidr()
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{
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printf(" Cache Size Identification Register for L%u %s:\n", Csselr::Level::get(Csselr::read()) + 1, Csselr::Ind::get(Csselr::read()) ? "Instruction Cache" : "Data Cache");
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printf(" Line size: 0x%x\n", Ccsidr::Line_size::get(Ccsidr::read()));
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printf(" Associativity: 0x%x\n", Ccsidr::Associativity::get(Ccsidr::read()));
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printf(" Number of Sets: 0x%x\n", Ccsidr::Num_sets::get(Ccsidr::read()));
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printf(" Write-Allocation: 0x%x\n", Ccsidr::Wa::get(Ccsidr::read()));
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printf(" Read-Allocation: 0x%x\n", Ccsidr::Ra::get(Ccsidr::read()));
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printf(" Write-Back: 0x%x\n", Ccsidr::Wb::get(Ccsidr::read()));
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printf(" Write-Through: 0x%x\n", Ccsidr::Wt::get(Ccsidr::read()));
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printf(" \n");
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}
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void info_ccsidr_level(unsigned const l, Clidr::access_t const t)
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{
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Csselr::access_t s = 0;
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Csselr::Level::set(s, l - 1);
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if (t & 1) { Csselr::Ind::set(s, 1); Csselr::write(s); info_ccsidr(); }
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if (t & 2) { Csselr::Ind::set(s, 0); Csselr::write(s); info_ccsidr(); }
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}
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void info()
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{
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/*
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* Processor
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*/
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printf("------ ARMv7 processor ------\n");
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printf("\n");
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printf(" Main Identification Register:\n");
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printf(" Revision: %u\n", Midr::Revision::get(Midr::read()));
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printf(" Primary Part number: %u\n", Midr::Primary_part_number::get(Midr::read()));
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printf(" Architecture: %u\n", Midr::Architecture::get(Midr::read()));
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printf(" Variant: %u\n", Midr::Variant::get(Midr::read()));
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printf(" Implementer: %c\n", Midr::Implementer::get(Midr::read()));
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printf(" \n");
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printf(" Multiprocessor Identification Register 0:\n");
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printf(" Multiprocessor: %u\n", Mpidr::Mp::get(Mpidr::read()));
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printf(" \n");
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printf(" Processor feature register 0:\n");
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printf(" ARM instruction set support: 0x%x\n", Id_pfr0::B0::get(Id_pfr0::read()));
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printf(" Thumb instruction set support: 0x%x\n", Id_pfr0::B1::get(Id_pfr0::read()));
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printf(" Jazelle extension support: 0x%x\n", Id_pfr0::B2::get(Id_pfr0::read()));
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printf(" ThumbEE instruction set support: 0x%x\n", Id_pfr0::B3::get(Id_pfr0::read()));
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printf(" \n");
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printf(" Processor feature register 1:\n");
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printf(" Programmers’ model: 0x%x\n", Id_pfr1::B0::get(Id_pfr1::read()));
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printf(" Security Extensions: 0x%x\n", Id_pfr1::B1::get(Id_pfr1::read()));
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printf(" M profile programmers model: 0x%x\n", Id_pfr1::B2::get(Id_pfr1::read()));
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printf(" Virtualization Extensions: 0x%x\n", Id_pfr1::B3::get(Id_pfr1::read()));
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printf(" Generic Timer Extension: 0x%x\n", Id_pfr1::B4::get(Id_pfr1::read()));
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printf(" \n");
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/*
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* Memory Model
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*/
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printf("------ ARMv7 memory model ------\n");
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printf("\n");
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printf(" Memory model feature register 0:\n");
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printf(" VMSA support: 0x%x\n", Id_mmfr0::B0::get(Id_mmfr0::read()));
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printf(" PMSA support: 0x%x\n", Id_mmfr0::B1::get(Id_mmfr0::read()));
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printf(" Outermost shareability: 0x%x\n", Id_mmfr0::B2::get(Id_mmfr0::read()));
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printf(" Shareability levels: 0x%x\n", Id_mmfr0::B3::get(Id_mmfr0::read()));
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printf(" TCM support: 0x%x\n", Id_mmfr0::B4::get(Id_mmfr0::read()));
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printf(" Auxiliary registers: 0x%x\n", Id_mmfr0::B5::get(Id_mmfr0::read()));
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printf(" FCSE support: 0x%x\n", Id_mmfr0::B6::get(Id_mmfr0::read()));
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printf(" Innermost shareability: 0x%x\n", Id_mmfr0::B7::get(Id_mmfr0::read()));
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printf(" \n");
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printf(" Memory model feature register 1:\n");
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printf(" L1 Harvard cache VA: 0x%x\n", Id_mmfr1::B0::get(Id_mmfr1::read()));
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printf(" L1 unified cache VA: 0x%x\n", Id_mmfr1::B1::get(Id_mmfr1::read()));
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printf(" L1 Harvard cache set/way: 0x%x\n", Id_mmfr1::B2::get(Id_mmfr1::read()));
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printf(" L1 unified cache set/way: 0x%x\n", Id_mmfr1::B3::get(Id_mmfr1::read()));
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printf(" L1 Harvard cache: 0x%x\n", Id_mmfr1::B4::get(Id_mmfr1::read()));
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printf(" L1 unified cache: 0x%x\n", Id_mmfr1::B5::get(Id_mmfr1::read()));
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printf(" L1 cache test and clean: 0x%x\n", Id_mmfr1::B6::get(Id_mmfr1::read()));
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printf(" Branch predictor: 0x%x\n", Id_mmfr1::B7::get(Id_mmfr1::read()));
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printf(" \n");
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printf(" Memory model feature register 2:\n");
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printf(" L1 Harvard fg fetch: 0x%x\n", Id_mmfr2::B0::get(Id_mmfr2::read()));
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printf(" L1 Harvard bg fetch: 0x%x\n", Id_mmfr2::B1::get(Id_mmfr2::read()));
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printf(" L1 Harvard range: 0x%x\n", Id_mmfr2::B2::get(Id_mmfr2::read()));
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printf(" Harvard TLB: 0x%x\n", Id_mmfr2::B3::get(Id_mmfr2::read()));
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printf(" Unified TLB: 0x%x\n", Id_mmfr2::B4::get(Id_mmfr2::read()));
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printf(" Mem barrier: 0x%x\n", Id_mmfr2::B5::get(Id_mmfr2::read()));
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printf(" WFI stall: 0x%x\n", Id_mmfr2::B6::get(Id_mmfr2::read()));
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printf(" HW Access flag: 0x%x\n", Id_mmfr2::B7::get(Id_mmfr2::read()));
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printf(" \n");
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printf(" Memory model feature register 3:\n");
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printf(" Cache maintain MVA: 0x%x\n", Id_mmfr3::B0::get(Id_mmfr3::read()));
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printf(" Cache maintain set/way: 0x%x\n", Id_mmfr3::B1::get(Id_mmfr3::read()));
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printf(" BP maintain: 0x%x\n", Id_mmfr3::B2::get(Id_mmfr3::read()));
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printf(" Maintenance broadcast: 0x%x\n", Id_mmfr3::B3::get(Id_mmfr3::read()));
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printf(" Coherent walk: 0x%x\n", Id_mmfr3::B5::get(Id_mmfr3::read()));
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printf(" Cached memory size: 0x%x\n", Id_mmfr3::B6::get(Id_mmfr3::read()));
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printf(" Supersection support: 0x%x\n", Id_mmfr3::B7::get(Id_mmfr3::read()));
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printf(" \n");
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printf(" TLB Type Register:\n");
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printf(" Unified TLB: %u\n", !Tlbtr::Nu::get(Tlbtr::read()));
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printf(" \n");
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/*
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* Caches
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*/
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printf("------ ARMv7 caches ------\n");
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printf("\n");
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printf(" Cache Type Register:\n");
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printf(" Instruction Cache Min Line: 0x%x\n", Ctr::Iminline::get(Ctr::read()));
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printf(" Level 1 Instruction Cache Policy: 0x%x\n", Ctr::L1ip::get(Ctr::read()));
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printf(" Data Cache Min Line: 0x%x\n", Ctr::Dminline::get(Ctr::read()));
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printf(" Exclusives Reservation Granule: 0x%x\n", Ctr::Erg::get(Ctr::read()));
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printf(" Cache Write-back Granule: 0x%x\n", Ctr::Cgw::get(Ctr::read()));
|
||||
printf(" \n");
|
||||
|
||||
printf(" Cache Level Identification Register:\n");
|
||||
printf(" Cache type 1: 0x%x\n", Clidr::Ctype1::get(Clidr::read()));
|
||||
printf(" Cache type 2: 0x%x\n", Clidr::Ctype2::get(Clidr::read()));
|
||||
printf(" Cache type 3: 0x%x\n", Clidr::Ctype3::get(Clidr::read()));
|
||||
printf(" Cache type 4: 0x%x\n", Clidr::Ctype4::get(Clidr::read()));
|
||||
printf(" Cache type 5: 0x%x\n", Clidr::Ctype5::get(Clidr::read()));
|
||||
printf(" Cache type 6: 0x%x\n", Clidr::Ctype6::get(Clidr::read()));
|
||||
printf(" Cache type 7: 0x%x\n", Clidr::Ctype7::get(Clidr::read()));
|
||||
printf(" Level of Unification Inner Shareable: 0x%x\n", Clidr::Louis::get(Clidr::read()));
|
||||
printf(" Level of Coherency: 0x%x\n", Clidr::Loc::get(Clidr::read()));
|
||||
printf(" Level of Unification Uniprocessor: 0x%x\n", Clidr::Louu::get(Clidr::read()));
|
||||
printf(" \n");
|
||||
|
||||
info_ccsidr_level(1, Clidr::Ctype1::get(Clidr::read()));
|
||||
info_ccsidr_level(2, Clidr::Ctype2::get(Clidr::read()));
|
||||
info_ccsidr_level(3, Clidr::Ctype3::get(Clidr::read()));
|
||||
info_ccsidr_level(4, Clidr::Ctype4::get(Clidr::read()));
|
||||
info_ccsidr_level(5, Clidr::Ctype5::get(Clidr::read()));
|
||||
info_ccsidr_level(6, Clidr::Ctype6::get(Clidr::read()));
|
||||
info_ccsidr_level(7, Clidr::Ctype7::get(Clidr::read()));
|
||||
|
||||
/*
|
||||
* Advanced SIMD and Floating-point Extensions
|
||||
*/
|
||||
|
||||
printf("------ ARMv7 advanced SIMD and floating-point extensions ------\n");
|
||||
printf("\n");
|
||||
|
||||
printf(" Floating-point System Identification Register:\n");
|
||||
printf(" Revision: %u\n", Fpsid::Revision::get(Fpsid::read()));
|
||||
printf(" Variant: %u\n", Fpsid::Variant::get(Fpsid::read()));
|
||||
printf(" Part number: %u\n", Fpsid::Part_number::get(Fpsid::read()));
|
||||
printf(" Subarchitecture: %u\n", Fpsid::Subarchitecture::get(Fpsid::read()));
|
||||
printf(" Software emulation: %u\n", Fpsid::Sw::get(Fpsid::read()));
|
||||
printf(" Implementer: %c\n", Fpsid::Implementer::get(Fpsid::read()));
|
||||
printf(" \n");
|
||||
|
||||
printf(" Media and VFP Feature Register 0:\n");
|
||||
printf(" Advanced SIMD registers: 0x%x\n", Mvfr0::B0::get(Mvfr0::read()));
|
||||
printf(" Single-precision: 0x%x\n", Mvfr0::B1::get(Mvfr0::read()));
|
||||
printf(" Double-precision: 0x%x\n", Mvfr0::B2::get(Mvfr0::read()));
|
||||
printf(" VFP exception trapping: 0x%x\n", Mvfr0::B3::get(Mvfr0::read()));
|
||||
printf(" Divide: 0x%x\n", Mvfr0::B4::get(Mvfr0::read()));
|
||||
printf(" Square root: 0x%x\n", Mvfr0::B5::get(Mvfr0::read()));
|
||||
printf(" Short vectors: 0x%x\n", Mvfr0::B6::get(Mvfr0::read()));
|
||||
printf(" VFP rounding modes: 0x%x\n", Mvfr0::B7::get(Mvfr0::read()));
|
||||
printf(" \n");
|
||||
|
||||
printf(" Media and VFP Feature Register 1:\n");
|
||||
printf(" Flush-to-Zero mode: 0x%x\n", Mvfr1::B0::get(Mvfr1::read()));
|
||||
printf(" Default NaN mode: 0x%x\n", Mvfr1::B1::get(Mvfr1::read()));
|
||||
printf(" Advanced SIMD load/store: 0x%x\n", Mvfr1::B2::get(Mvfr1::read()));
|
||||
printf(" Advanced SIMD integer instructions: 0x%x\n", Mvfr1::B3::get(Mvfr1::read()));
|
||||
printf(" Advanced SIMD single-precision FP: 0x%x\n", Mvfr1::B4::get(Mvfr1::read()));
|
||||
printf(" Advanced SIMD half-precision FP: 0x%x\n", Mvfr1::B5::get(Mvfr1::read()));
|
||||
printf(" VFP half-precision FP conversion: 0x%x\n", Mvfr1::B6::get(Mvfr1::read()));
|
||||
printf(" Fused multiply accumulate: 0x%x\n", Mvfr1::B7::get(Mvfr1::read()));
|
||||
printf(" \n");
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# \brief Build config for a core that prints hardware information
|
||||
# \author Martin Stein
|
||||
# \date 2011-12-16
|
||||
#
|
||||
|
||||
# set target name that this configuration applies to
|
||||
TARGET = test-hw_info
|
||||
|
||||
# add library dependencies
|
||||
LIBS += core test-hw_info
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += kernel/test.cc
|
||||
Loading…
Reference in New Issue