Stefan Kalkowski
Christian Helmuth
parent
4caf12cd16
commit
a3abf74d1e
|
|
@ -10,6 +10,8 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a15
|
|||
INC_DIR += $(REP_DIR)/src/core/include/spec/corelink_gic400
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += spec/exynos5/platform_support.cc
|
||||
SRC_CC += spec/exynos5/cpu.cc
|
||||
SRC_CC += platform_services.cc
|
||||
SRC_CC += spec/arm_gic/pic.cc
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Stefan Kalkowski
|
||||
# \author Martin Stein
|
||||
# \date 2012-10-04
|
||||
#
|
||||
|
||||
# add include paths
|
||||
INC_DIR += $(REP_DIR)/src/core/include/spec/arndale
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += spec/arndale/platform_support.cc
|
||||
SRC_CC += spec/arndale/cpu.cc
|
||||
|
||||
# include less specific configuration
|
||||
include $(REP_DIR)/lib/mk/exynos5/core.inc
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
#
|
||||
# \brief Build config for Genodes core process
|
||||
# \author Stefan Kalkowski
|
||||
# \date 2013-11-25
|
||||
#
|
||||
|
||||
# add include paths
|
||||
INC_DIR += $(REP_DIR)/src/core/include/spec/odroid_xu
|
||||
|
||||
# add C++ sources
|
||||
SRC_CC += spec/odroid_xu/platform_support.cc
|
||||
SRC_CC += cpu.cc
|
||||
|
||||
# include less specific library parts
|
||||
include $(REP_DIR)/lib/mk/exynos5/core.inc
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* \brief Parts of platform that are specific to Odroid XU
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2013-11-25
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU General Public License version 2.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
#include <pic.h>
|
||||
#include <cpu.h>
|
||||
#include <timer.h>
|
||||
|
||||
using namespace Genode;
|
||||
|
||||
Native_region * Platform::_ram_regions(unsigned const i)
|
||||
{
|
||||
static Native_region _regions[] =
|
||||
{
|
||||
{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
|
||||
};
|
||||
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
|
||||
}
|
||||
|
||||
|
||||
Native_region * Platform::_mmio_regions(unsigned const i)
|
||||
{
|
||||
static Native_region _regions[] =
|
||||
{
|
||||
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
|
||||
};
|
||||
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
|
||||
}
|
||||
|
||||
|
||||
Native_region * Platform::_core_only_mmio_regions(unsigned const i)
|
||||
{
|
||||
static Native_region _regions[] =
|
||||
{
|
||||
{ Board::GIC_CPU_MMIO_BASE, Board::GIC_CPU_MMIO_SIZE },
|
||||
{ Board::MCT_MMIO_BASE, Board::MCT_MMIO_SIZE },
|
||||
};
|
||||
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
|
||||
}
|
||||
|
||||
|
||||
Cpu::User_context::User_context() { cpsr = Psr::init_user(); }
|
||||
|
|
@ -34,15 +34,6 @@ namespace Genode
|
|||
PMU_MMIO_BASE = 0x10040000,
|
||||
PMU_MMIO_SIZE = 0x5000,
|
||||
|
||||
/* interrupt controller */
|
||||
GIC_CPU_MMIO_BASE = 0x10480000,
|
||||
GIC_CPU_MMIO_SIZE = 0x00010000,
|
||||
|
||||
/* UART */
|
||||
UART_2_MMIO_BASE = 0x12C20000,
|
||||
UART_2_CLOCK = 100000000,
|
||||
UART_2_IRQ = 85,
|
||||
|
||||
/* USB */
|
||||
USB_HOST20_IRQ = 103,
|
||||
USB_DRD30_IRQ = 104,
|
||||
|
|
@ -56,14 +47,11 @@ namespace Genode
|
|||
/* SD card */
|
||||
SDMMC0_IRQ = 107,
|
||||
|
||||
/* UART */
|
||||
UART_2_CLOCK = 100000000,
|
||||
|
||||
/* wether board provides security extension */
|
||||
SECURITY_EXTENSION = 1,
|
||||
|
||||
/* IRAM */
|
||||
IRAM_BASE = 0x02020000,
|
||||
|
||||
/* hardware name of the primary processor */
|
||||
PRIMARY_MPIDR_AFF_0 = 0,
|
||||
};
|
||||
};
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,17 +26,8 @@ namespace Genode
|
|||
{
|
||||
enum
|
||||
{
|
||||
/* interrupt controller */
|
||||
GIC_CPU_MMIO_BASE = 0x10481000,
|
||||
GIC_CPU_MMIO_SIZE = 0x00010000,
|
||||
|
||||
/* UART */
|
||||
UART_2_MMIO_BASE = 0x12C20000,
|
||||
UART_2_CLOCK = 62668800,
|
||||
UART_2_IRQ = 85,
|
||||
|
||||
/* CPU cache */
|
||||
CACHE_LINE_SIZE_LOG2 = 6,
|
||||
UART_2_CLOCK = 62668800,
|
||||
|
||||
/* wether board provides security extension */
|
||||
SECURITY_EXTENSION = 0,
|
||||
|
|
|
|||
|
|
@ -35,6 +35,14 @@ class Genode::Exynos5
|
|||
MMIO_0_BASE = 0x10000000,
|
||||
MMIO_0_SIZE = 0x10000000,
|
||||
|
||||
/* interrupt controller */
|
||||
GIC_CPU_MMIO_BASE = 0x10480000,
|
||||
GIC_CPU_MMIO_SIZE = 0x00010000,
|
||||
|
||||
/* UART */
|
||||
UART_2_MMIO_BASE = 0x12C20000,
|
||||
UART_2_IRQ = 85,
|
||||
|
||||
/* pulse-width-modulation timer */
|
||||
PWM_MMIO_BASE = 0x12dd0000,
|
||||
PWM_MMIO_SIZE = 0x1000,
|
||||
|
|
@ -50,6 +58,12 @@ class Genode::Exynos5
|
|||
|
||||
/* CPU cache */
|
||||
CACHE_LINE_SIZE_LOG2 = 6,
|
||||
|
||||
/* IRAM */
|
||||
IRAM_BASE = 0x02020000,
|
||||
|
||||
/* hardware name of the primary processor */
|
||||
PRIMARY_MPIDR_AFF_0 = 0,
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue