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hw: re-organize file structure 

fix #1197
This commit is contained in:
Martin Stein 2014-07-09 12:03:17 +02:00 committed by Norman Feske
parent bfdc4138ba
commit a5cf09fa6e
151 changed files with 1935 additions and 2599 deletions
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4
repos/base-hw/include/base/pager.h
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@ -19,9 +19,7 @@
#include <base/object_pool.h>
#include <base/signal.h>
#include <pager/capability.h>
/* base-hw includes */
#include <placement_new.h>
#include <unmanaged_singleton.h>
namespace Genode
{

38
repos/base-hw/include/platform/imx31/drivers/serial_log.h
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@ -1,38 +0,0 @@
/*
* \brief Serial output driver specific for the i.MX31
* \author Norman Feske
* \date 2012-08-30
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__IMX31__DRIVERS__SERIAL_LOG_H_
#define _INCLUDE__PLATFORM__IMX31__DRIVERS__SERIAL_LOG_H_
/* Genode includes */
#include <board.h>
#include <drivers/uart/imx31_uart_base.h>
namespace Genode
{
struct Serial_log : Imx31_uart_base
{
/**
* Constructor
*
* \param baud_rate targeted transfer baud-rate
*
* XXX: The 'baud_rate' argument is ignored for now.
*/
Serial_log(unsigned const baud_rate)
: Imx31_uart_base(Board::UART_1_MMIO_BASE) { }
};
}
#endif /* _INCLUDE__PLATFORM__IMX31__DRIVERS__SERIAL_LOG_H_ */

38
repos/base-hw/include/platform/imx53/drivers/serial_log.h
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@ -1,38 +0,0 @@
/*
* \brief Serial output driver specific for the i.MX53
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__IMX53__DRIVERS__SERIAL_LOG_H_
#define _INCLUDE__PLATFORM__IMX53__DRIVERS__SERIAL_LOG_H_
/* Genode includes */
#include <drivers/board_base.h>
#include <drivers/uart/imx31_uart_base.h>
namespace Genode
{
struct Serial_log : Imx31_uart_base
{
/**
* Constructor
*
* \param baud_rate targeted transfer baud-rate
*
* XXX: The 'baud_rate' argument is ignored for now.
*/
Serial_log(unsigned const baud_rate)
: Imx31_uart_base(Board_base::UART_1_MMIO_BASE) { }
};
}
#endif /* _INCLUDE__PLATFORM__IMX53__DRIVERS__SERIAL_LOG_H_ */

2
repos/base-hw/lib/mk/arm/base-common.mk
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@ -1,3 +1,3 @@
include $(REP_DIR)/lib/mk/base-common.inc
vpath kernel/interface.cc $(REP_DIR)/src/arm
vpath kernel/interface.cc $(REP_DIR)/src/base/arm

14
repos/base-hw/lib/mk/arm/core.inc
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@ -5,14 +5,16 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/arm
INC_DIR += $(REP_DIR)/src/core/include/spec/arm
# declare source paths
vpath cpu_support.cc $(REP_DIR)/src/core/arm
vpath crt0.s $(REP_DIR)/src/core/arm
# add C++ sources
SRC_CC += spec/arm/cpu_support.cc
# add assembly sources
SRC_S += spec/arm/crt0.s
# use dummy boot-modules per default
BOOT_MODULES_VPATH = $(REP_DIR)/src/core/arm
BOOT_MODULES_VPATH = $(REP_DIR)/src/core/spec/arm
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/core.inc

14
repos/base-hw/lib/mk/arm_v6/core-perf_counter_on.mk Normal file
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@ -0,0 +1,14 @@
#
# \brief Core build-config that depends on performance-counter status
# \author Josef Soentgen
# \date 2013-09-26
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include
# add C++ sources
SRC_CC += spec/arm_v6/perf_counter.cc
# declare source locations
vpath % $(REP_DIR)/src/core

8
repos/base-hw/lib/mk/arm_v6/core.inc
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@ -5,10 +5,10 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/arm_v6
INC_DIR += $(REP_DIR)/src/core/include/spec/arm_v6
# declare source paths
vpath mode_transition.s $(REP_DIR)/src/core/arm_v6
# add assembly sources
SRC_S += spec/arm_v6/mode_transition.s
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm/core.inc

3
repos/base-hw/lib/mk/arm_v6/enable_perf_counter.mk
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@ -1,3 +0,0 @@
SRC_CC = perf_counter.cc
vpath %.cc $(REP_DIR)/src/core/arm_v6

14
repos/base-hw/lib/mk/arm_v7/core-perf_counter_on.mk Normal file
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@ -0,0 +1,14 @@
#
# \brief Core build-config that depends on performance-counter status
# \author Josef Soentgen
# \date 2013-09-26
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include
# add C++ sources
SRC_CC += spec/arm_v7/perf_counter.cc
# declare source locations
vpath % $(REP_DIR)/src/core

8
repos/base-hw/lib/mk/arm_v7/core.inc
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@ -5,10 +5,10 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/arm_v7
INC_DIR += $(REP_DIR)/src/core/include/spec/arm_v7
# declare source paths
vpath mode_transition.s $(REP_DIR)/src/core/arm_v7
# add assembly sources
SRC_S += spec/arm_v7/mode_transition.s
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm/core.inc

3
repos/base-hw/lib/mk/arm_v7/enable_perf_counter.mk
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@ -1,3 +0,0 @@
SRC_CC = perf_counter.cc
vpath %.cc $(REP_DIR)/src/core/arm_v7

25
repos/base-hw/lib/mk/base-common.inc
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@ -5,27 +5,36 @@
# \date 2013-02-14
#
# add library dependencies
LIBS += cxx
SRC_CC += ipc.cc ipc/ipc_marshal_cap.cc
# add C++ sources
SRC_CC += ipc/ipc.cc
SRC_CC += ipc/ipc_marshal_cap.cc
SRC_CC += avl_tree/avl_tree.cc
SRC_CC += allocator/slab.cc
SRC_CC += allocator/allocator_avl.cc
SRC_CC += heap/heap.cc heap/sliced_heap.cc
SRC_CC += heap/heap.cc
SRC_CC += heap/sliced_heap.cc
SRC_CC += child/child.cc
SRC_CC += process/process.cc
SRC_CC += elf/elf_binary.cc
SRC_CC += console/console.cc
SRC_CC += lock/lock.cc
SRC_CC += signal/signal.cc signal/common.cc
SRC_CC += server/server.cc server/common.cc
SRC_CC += thread/thread_bootstrap.cc thread/trace.cc
SRC_CC += signal/signal.cc
SRC_CC += signal/common.cc
SRC_CC += server/server.cc
SRC_CC += server/common.cc
SRC_CC += thread/bootstrap.cc
SRC_CC += thread/trace.cc
SRC_CC += thread/context_allocator.cc
SRC_CC += kernel/interface.cc
INC_DIR += $(REP_DIR)/src/base/lock
# add include paths
INC_DIR += $(REP_DIR)/src/base/lock
INC_DIR += $(BASE_DIR)/src/base/lock
INC_DIR += $(BASE_DIR)/src/base/thread
vpath %.cc $(REP_DIR)/src/base
vpath %.cc $(BASE_DIR)/src/base
# declare source locations
vpath % $(REP_DIR)/src/base
vpath % $(BASE_DIR)/src/base

15
repos/base-hw/lib/mk/base.mk
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@ -4,14 +4,21 @@
# \date 2013-02-14
#
# add library dependencies
LIBS += base-common startup
# add C++ sources
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread.cc thread_support.cc
SRC_CC += env/env.cc
SRC_CC += env/context_area.cc
SRC_CC += env/reinitialize.cc
SRC_CC += thread/thread.cc
SRC_CC += thread/start.cc
# add include paths
INC_DIR += $(BASE_DIR)/src/base/env
vpath %.cc $(REP_DIR)/src/base
vpath %.cc $(BASE_DIR)/src/base
# declare source locations
vpath % $(REP_DIR)/src/base
vpath % $(BASE_DIR)/src/base

14
repos/base-hw/lib/mk/core-perf_counter.mk Normal file
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@ -0,0 +1,14 @@
#
# \brief Core build-config that depends on performance-counter status
# \author Josef Soentgen
# \date 2013-09-26
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include
# add C++ sources
SRC_CC += perf_counter.cc
# declare source locations
vpath % $(REP_DIR)/src/core

7
repos/base-hw/lib/mk/core-trustzone.inc
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@ -6,10 +6,9 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core
INC_DIR += $(REP_DIR)/src/core/include
INC_DIR += $(BASE_DIR)/src/core/include
# add C++ sources
SRC_CC += platform_support.cc
SRC_CC += platform_services.cc
# declare source paths
vpath % $(REP_DIR)/src/core
vpath % $(BASE_DIR)/src/core

44
repos/base-hw/lib/mk/core.inc
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@ -4,23 +4,21 @@
# \date 2011-12-16
#
# add library dependencies
LIBS += core-perf_counter
# set entry point of core's first thread
CC_OPT += -DCORE_MAIN=_main
# add library dependencies
LIBS += base-common perf_counter
LIBS += base-common
# add include paths
INC_DIR += $(REP_DIR)/src/core
INC_DIR += $(REP_DIR)/src/core/include
INC_DIR += $(REP_DIR)/include
INC_DIR += $(REP_DIR)/src/platform
INC_DIR += $(REP_DIR)/src/base
INC_DIR += $(BASE_DIR)/src/core/include
INC_DIR += $(BASE_DIR)/include
INC_DIR += $(BASE_DIR)/src/platform
INC_DIR += $(BASE_DIR)/src/base/thread
INC_DIR += $(BASE_DIR)/src/base/include
INC_DIR += $(BASE_DIR)/src/base/thread
INC_DIR += $(BASE_DIR)/src/platform
# add C++ sources
SRC_CC += console.cc
@ -45,12 +43,11 @@ SRC_CC += rm_session_component.cc
SRC_CC += rom_session_component.cc
SRC_CC += signal_session_component.cc
SRC_CC += trace_session_component.cc
SRC_CC += thread.cc
SRC_CC += thread_support.cc
SRC_CC += thread/thread.cc
SRC_CC += thread_start.cc
SRC_CC += rm_session_support.cc
SRC_CC += pager.cc
SRC_CC += _main.cc
SRC_CC += cpu_support.cc
SRC_CC += kernel/kernel.cc
SRC_CC += kernel/thread.cc
SRC_CC += kernel/vm.cc
@ -60,9 +57,7 @@ SRC_CC += kernel/processor.cc
SRC_CC += kernel/processor_pool.cc
# add assembly sources
SRC_S += mode_transition.s
SRC_S += boot_modules.s
SRC_S += crt0.s
# provide Genode version information
include $(BASE_DIR)/src/core/version.inc
@ -75,22 +70,7 @@ endif
vpath boot_modules.s $(BOOT_MODULES_VPATH)
# declare source locations
vpath _main.cc $(BASE_DIR)/src/platform
vpath cpu_session_component.cc $(BASE_DIR)/src/core
vpath dataspace_component.cc $(BASE_DIR)/src/core
vpath io_mem_session_component.cc $(BASE_DIR)/src/core
vpath io_mem_session_support.cc $(BASE_DIR)/src/core
vpath main.cc $(BASE_DIR)/src/core
vpath pd_session_component.cc $(BASE_DIR)/src/core
vpath ram_session_component.cc $(BASE_DIR)/src/core
vpath rm_session_component.cc $(BASE_DIR)/src/core
vpath rom_session_component.cc $(BASE_DIR)/src/core
vpath trace_session_component.cc $(BASE_DIR)/src/core
vpath dump_alloc.cc $(BASE_DIR)/src/core
vpath context_area.cc $(BASE_DIR)/src/core
vpath core_mem_alloc.cc $(BASE_DIR)/src/core
vpath console.cc $(REP_DIR)/src/base
vpath pager.cc $(REP_DIR)/src/base
vpath _main.cc $(BASE_DIR)/src/platform
vpath thread.cc $(BASE_DIR)/src/base/thread
vpath % $(REP_DIR)/src/core
vpath % $(REP_DIR)/src/core
vpath % $(BASE_DIR)/src/core
vpath % $(BASE_DIR)/src/platform
vpath % $(BASE_DIR)/src/base

10
repos/base-hw/lib/mk/exynos5/core.inc
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@ -5,14 +5,12 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/exynos5
INC_DIR += $(REP_DIR)/src/core/include/spec/exynos5
INC_DIR += $(REP_DIR)/src/core/include/spec/corelink_gic400
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += platform_support.cc
SRC_CC += spec/arm_gic/pic.cc
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v7/core.inc

3
repos/base-hw/lib/mk/perf_counter.mk
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@ -1,3 +0,0 @@
SRC_CC = perf_counter.cc
vpath %.cc $(REP_DIR)/src/core/

8
repos/base-hw/lib/mk/perf_counter/core-perf_counter.mk Normal file
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@ -0,0 +1,8 @@
#
# \brief Core build-config that depends on performance-counter status
# \author Josef Soentgen
# \date 2013-09-26
#
# add library dependencies
LIBS += core-perf_counter_on

1
repos/base-hw/lib/mk/perf_counter/perf_counter.mk
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@ -1 +0,0 @@
LIBS += enable_perf_counter

8
repos/base-hw/lib/mk/platform_arndale/core.mk
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@ -6,10 +6,10 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/arndale
INC_DIR += $(REP_DIR)/src/core/include/spec/arndale
# declare source paths
vpath platform_support.cc $(REP_DIR)/src/core/arndale
# add C++ sources
SRC_CC += spec/arndale/platform_support.cc
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/exynos5/core.inc

11
repos/base-hw/lib/mk/platform_imx31/core.mk
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@ -5,15 +5,12 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx31
INC_DIR += $(REP_DIR)/src/core/include/spec/imx31
INC_DIR += $(REP_DIR)/src/core/include/spec/imx
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += platform_support.cc
SRC_CC += spec/imx31/platform_support.cc
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
vpath platform_support.cc $(REP_DIR)/src/core/imx31
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v6/core.inc

15
repos/base-hw/lib/mk/platform_imx53/core-trustzone.inc
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@ -1,15 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx53
# add C++ sources
SRC_CC += pic.cc
# include less specific library parts
include $(REP_DIR)/lib/mk/core-trustzone.inc

16
repos/base-hw/lib/mk/platform_imx53/core-trustzone_off.mk
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@ -5,10 +5,14 @@
# \date 2012-10-24
#
# declare source paths
vpath platform_support.cc $(REP_DIR)/src/core/imx53
vpath pic.cc $(REP_DIR)/src/core/imx53
vpath platform_services.cc $(BASE_DIR)/src/core
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/imx53
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a8
# include less specific library parts
include $(REP_DIR)/lib/mk/platform_imx53/core-trustzone.inc
# add C++ sources
SRC_CC += spec/imx53/platform_support.cc
SRC_CC += spec/imx53/pic.cc
SRC_CC += platform_services.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/core-trustzone.inc

17
repos/base-hw/lib/mk/platform_imx53/core-trustzone_on.mk
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@ -6,16 +6,15 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx53/trustzone
INC_DIR += $(REP_DIR)/src/core/include/spec/imx53/trustzone
INC_DIR += $(REP_DIR)/src/core/include/spec/imx53
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a8
# add C++ sources
SRC_CC += spec/imx53/trustzone/platform_support.cc
SRC_CC += spec/imx53/trustzone/platform_services.cc
SRC_CC += spec/imx53/trustzone/pic.cc
SRC_CC += vm_session_component.cc
# declare source paths
vpath platform_support.cc $(REP_DIR)/src/core/imx53/trustzone
vpath platform_services.cc $(REP_DIR)/src/core/imx53/trustzone
vpath pic.cc $(REP_DIR)/src/core/imx53/trustzone
vpath vm_session_component.cc $(REP_DIR)/src/core
# include less specific library parts
include $(REP_DIR)/lib/mk/platform_imx53/core-trustzone.inc
# include less specific configuration
include $(REP_DIR)/lib/mk/core-trustzone.inc

6
repos/base-hw/lib/mk/platform_imx53/core.mk
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@ -9,7 +9,9 @@
LIBS += core-trustzone
# add include paths
INC_DIR += $(REP_DIR)/src/core/imx53
INC_DIR += $(REP_DIR)/src/core/include/spec/imx53
INC_DIR += $(REP_DIR)/src/core/include/spec/imx
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a8
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v7/core.inc

6
repos/base-hw/lib/mk/platform_odroid_xu/core.mk
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@ -5,10 +5,10 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/odroid_xu
INC_DIR += $(REP_DIR)/src/core/include/spec/odroid_xu
# declare source paths
vpath platform_support.cc $(REP_DIR)/src/core/odroid_xu
# add C++ sources
SRC_CC += spec/odroid_xu/platform_support.cc
# include less specific library parts
include $(REP_DIR)/lib/mk/exynos5/core.inc

14
repos/base-hw/lib/mk/platform_panda/core.mk
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@ -6,15 +6,15 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/panda
INC_DIR += $(REP_DIR)/src/core/include/spec/panda
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
INC_DIR += $(REP_DIR)/src/core/include/spec/tl16c750
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += platform_support.cc
SRC_CC += spec/panda/platform_support.cc
SRC_CC += spec/cortex_a9/pic.cc
SRC_CC += spec/arm_gic/pic.cc
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
vpath platform_support.cc $(REP_DIR)/src/core/panda
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v7/core.inc

14
repos/base-hw/lib/mk/platform_pbxa9/core.mk
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@ -6,15 +6,15 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/pbxa9
INC_DIR += $(REP_DIR)/src/core/include/spec/pbxa9
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += platform_support.cc
SRC_CC += spec/pbxa9/platform_support.cc
SRC_CC += spec/cortex_a9/pic.cc
SRC_CC += spec/arm_gic/pic.cc
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
vpath platform_support.cc $(REP_DIR)/src/core/pbxa9
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v7/core.inc

11
repos/base-hw/lib/mk/platform_rpi/core.mk
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@ -5,15 +5,12 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/rpi
INC_DIR += $(REP_DIR)/src/core/include/spec/rpi
INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += platform_support.cc
SRC_CC += spec/rpi/platform_support.cc
# declare source paths
vpath platform_services.cc $(BASE_DIR)/src/core
vpath platform_support.cc $(REP_DIR)/src/core/rpi
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v6/core.inc

12
repos/base-hw/lib/mk/platform_vea9x4/core-trustzone.inc
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@ -1,12 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/vea9x4
# include less specific library parts
include $(REP_DIR)/lib/mk/core-trustzone.inc

16
repos/base-hw/lib/mk/platform_vea9x4/core-trustzone_off.mk
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@ -5,9 +5,15 @@
# \date 2012-10-24
#
# declare source paths
vpath platform_support.cc $(REP_DIR)/src/core/vea9x4
vpath platform_services.cc $(BASE_DIR)/src/core
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
# include less specific library parts
include $(REP_DIR)/lib/mk/platform_vea9x4/core-trustzone.inc
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += spec/vea9x4/platform_support.cc
SRC_CC += spec/cortex_a9/pic.cc
SRC_CC += spec/arm_gic/pic.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/core-trustzone.inc

14
repos/base-hw/lib/mk/platform_vea9x4/core-trustzone_on.mk
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@ -7,14 +7,14 @@
# add include paths
INC_DIR += $(REP_DIR)/src/core/vea9x4/trustzone
INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
# add C++ sources
SRC_CC += vm_session_component.cc
SRC_CC += spec/vea9x4/trustzone/platform_support.cc
SRC_CC += spec/vea9x4/trustzone/pic.cc
SRC_CC += spec/vea9x4/trustzone/platform_services.cc
# declare source paths
vpath platform_support.cc $(REP_DIR)/src/core/vea9x4/trustzone
vpath platform_services.cc $(REP_DIR)/src/core/vea9x4/trustzone
vpath vm_session_component.cc $(REP_DIR)/src/core
# include less specific library parts
include $(REP_DIR)/lib/mk/platform_vea9x4/core-trustzone.inc
# include less specific configuration
include $(REP_DIR)/lib/mk/core-trustzone.inc

6
repos/base-hw/lib/mk/platform_vea9x4/core.mk
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@ -9,7 +9,9 @@
LIBS += core-trustzone
# add include paths
INC_DIR += $(REP_DIR)/src/core/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
# include less specific library parts
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v7/core.inc

0
repos/base-hw/src/arm/kernel/interface.cc → repos/base-hw/src/base/arm/kernel/interface.cc
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0
repos/base-hw/src/base/ipc.cc → repos/base-hw/src/base/ipc/ipc.cc
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22
repos/base-hw/src/base/placement_new.h
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@ -1,22 +0,0 @@
/*
* \brief Placement new operator
* \author Martin Stein
* \date 2013-11-07
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PLACEMENT_NEW_H_
#define _PLACEMENT_NEW_H_
/* base includes */
#include <unmanaged_singleton.h>
/* FIXME: remove this header as soon as the Placeable template is public */
#endif /* _PLACEMENT_NEW_H_ */

2
repos/base-hw/src/base/thread/thread_bootstrap.cc → repos/base-hw/src/base/thread/bootstrap.cc
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@ -1,5 +1,5 @@
/*
* \brief Thread initialization
* \brief Implementations for the initialization of a thread
* \author Martin stein
* \author Stefan Kalkowski
* \date 2013-02-15

2
repos/base-hw/src/base/thread_support.cc → repos/base-hw/src/base/thread/start.cc
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@ -1,5 +1,5 @@
/**
* \brief Platform specific parts of the thread API
* \brief Implementations for the start of a thread
* \author Martin Stein
* \author Stefan Kalkowski
* \date 2012-02-12

56
repos/base-hw/src/core/arndale/timer.h
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@ -1,56 +0,0 @@
/*
* \brief Timer for kernel
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _ARNDALE__TIMER_H_
#define _ARNDALE__TIMER_H_
/* core includes */
#include <board.h>
#include <timer/exynos_mct.h>
namespace Kernel
{
/**
* Kernel timer
*/
class Timer : public Exynos_mct::Timer
{
public:
/**
* Return kernel name of timer interrupt of a specific processor
*
* \param processor_id kernel name of targeted processor
*/
static unsigned interrupt_id(unsigned const processor_id)
{
switch (processor_id) {
case 0:
return Genode::Board::MCT_IRQ_L0;
case 1:
return Genode::Board::MCT_IRQ_L1;
default:
PERR("unknown processor");
return 0;
}
}
/**
* Constructor
*/
Timer() : Exynos_mct::Timer(Genode::Board::MCT_MMIO_BASE,
Genode::Board::MCT_CLOCK) { }
};
}
#endif /* _ARNDALE__TIMER_H_ */

17
repos/base-hw/src/base/console.cc → repos/base-hw/src/core/console.cc
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@ -14,7 +14,9 @@
/* Genode includes */
#include <base/console.h>
#include <base/printf.h>
#include <drivers/serial_log.h>
/* core includes */
#include <serial.h>
/* base includes */
#include <unmanaged_singleton.h>
@ -24,8 +26,7 @@ namespace Genode
/**
* Platform specific Genode console
*/
class Platform_console : public Console,
public Serial_log
class Platform_console : public Console, public Serial
{
enum { BAUD_RATE = 115200 };
@ -43,10 +44,10 @@ namespace Genode
/* auto complete new line commands */
if (c == ASCII_LINE_FEED)
Serial_log::put_char(ASCII_CARRIAGE_RETURN);
Serial::put_char(ASCII_CARRIAGE_RETURN);
/* print char */
Serial_log::put_char(c);
Serial::put_char(c);
}
public:
@ -54,7 +55,7 @@ namespace Genode
/**
* Constructor
*/
Platform_console() : Serial_log(BAUD_RATE) { }
Platform_console() : Serial(BAUD_RATE) { }
};
}
@ -84,5 +85,7 @@ void Genode::printf(const char *format, ...)
void Genode::vprintf(const char *format, va_list list)
{ platform_console()->vprintf(format, list); }
{
platform_console()->vprintf(format, list);
}

42
repos/base-hw/src/core/exynos5/pic.h
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@ -1,42 +0,0 @@
/*
* \brief Interrupt controller for kernel
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _EXYNOS5__PIC_H_
#define _EXYNOS5__PIC_H_
/* core includes */
#include <pic/corelink_gic400.h>
#include <board.h>
namespace Kernel
{
/**
* Interrupt controller for kernel
*/
class Pic : public Corelink_gic400::Pic
{
public:
/**
* Constructor
*/
Pic() : Corelink_gic400::Pic(Genode::Board::GIC_CPU_MMIO_BASE) { }
};
}
bool Arm_gic::Pic::_use_security_ext() { return 0; }
#endif /* _EXYNOS5__PIC_H_ */

29
repos/base-hw/src/core/imx31/pic.h
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@ -1,29 +0,0 @@
/*
* \brief Interrupt controller for kernel
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX31__PIC_H_
#define _IMX31__PIC_H_
/* core includes */
#include <pic/imx31.h>
namespace Kernel
{
/**
* Interrupt controller for kernel
*/
class Pic : public Imx31::Pic { };
}
#endif /* _IMX31__PIC_H_ */

27
repos/base-hw/src/core/imx31/processor_driver.h
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@ -1,27 +0,0 @@
/*
* \brief Processor driver for core
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX31__PROCESSOR_DRIVER_H_
#define _IMX31__PROCESSOR_DRIVER_H_
/* core includes */
#include <processor_driver/arm_v6.h>
namespace Genode
{
using Arm_v6::Processor_lazy_state;
using Arm_v6::Processor_driver;
}
#endif /* _IMX31__PROCESSOR_DRIVER_H_ */

43
repos/base-hw/src/core/imx31/timer.h
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@ -1,43 +0,0 @@
/*
* \brief Timer for kernel
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX31__TIMER_H_
#define _IMX31__TIMER_H_
/* core includes */
#include <drivers/timer/epit_base.h>
#include <board.h>
namespace Kernel
{
class Timer : public Genode::Epit_base
{
public:
/**
* Return kernel name of timer interrupt
*/
static unsigned interrupt_id(unsigned)
{
return Genode::Board::EPIT_1_IRQ;
}
/**
* Constructor
*/
Timer() : Genode::Epit_base(Genode::Board::EPIT_1_MMIO_BASE) { }
};
}
#endif /* _IMX31__TIMER_H_ */

232
repos/base-hw/src/core/imx53/pic.h
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@ -1,232 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
/* Genode includes */
#include <util/mmio.h>
/* core includes */
#include <board.h>
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic : public Mmio
{
public:
enum { NR_OF_IRQ = 109 };
protected:
/**
* Interrupt control register
*/
struct Intctrl : Register<0, 32>
{
struct Enable : Bitfield<0,1> { };
struct Nsen : Bitfield<16,1> { };
struct Nsen_mask : Bitfield<31,1> { };
};
struct Priomask : Register<0xc, 32>
{
struct Mask : Bitfield<0,8> { };
};
struct Syncctrl : Register<0x10, 32>
{
struct Syncmode : Bitfield<0,2> { };
};
struct Dsmint : Register<0x14, 32>
{
struct Dsm : Bitfield<0,1> { };
};
/**
* Interrupt security registers
*/
struct Intsec : Register_array<0x80, 32, NR_OF_IRQ, 1>
{
struct Nonsecure : Bitfield<0, 1> { };
};
/**
* Interrupt set enable registers
*/
struct Enset : Register_array<0x100, 32, NR_OF_IRQ, 1, true>
{
struct Set_enable : Bitfield<0, 1> { };
};
/**
* Interrupt clear enable registers
*/
struct Enclear : Register_array<0x180, 32, NR_OF_IRQ, 1, true>
{
struct Clear_enable : Bitfield<0, 1> { };
};
/**
* Interrupt priority level registers
*/
struct Priority : Register_array<0x400, 32, NR_OF_IRQ, 8>
{
enum { MIN_PRIO = 0xff };
};
/**
* Pending registers
*/
struct Pndr : Register_array<0xd00, 32, NR_OF_IRQ, 1>
{
struct Pending : Bitfield<0, 1> { };
};
/**
* Highest interrupt pending registers
*/
struct Hipndr : Register_array<0xd80, 32, NR_OF_IRQ, 1, true>
{
struct Pending : Bitfield<0, 1> { };
};
/**
* Maximum supported interrupt priority
*/
unsigned _max_priority() { return 255; }
/**
* Initialization that is common to constructor implementations
*/
void _common_init()
{
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
write<Intsec::Nonsecure>(1, i);
write<Enclear::Clear_enable>(1, i);
}
write<Priomask::Mask>(0x1f);
write<Intctrl>(Intctrl::Enable::bits(1) |
Intctrl::Nsen::bits(1) |
Intctrl::Nsen_mask::bits(1));
}
public:
/**
* Constructor, all interrupts get masked
*/
Pic();
void unsecure(unsigned const i);
void secure(unsigned const i);
/**
* Initialize processor local interface of the controller
*/
void init_processor_local() { }
/**
* Receive a pending request number 'i'
*/
bool take_request(unsigned & i)
{
for (unsigned j = 0; j < NR_OF_IRQ; j++) {
if (read<Hipndr::Pending>(j)) {
i = j;
return true;
}
}
return false;
}
/**
* Finish the last taken request
*/
void finish_request() { }
/**
* Validate request number 'i'
*/
bool valid(unsigned const i) const {
return i < NR_OF_IRQ; }
/**
* Unmask all interrupts
*/
void unmask()
{
for (unsigned i=0; i < NR_OF_IRQ; i++)
write<Enset::Set_enable>(1, i);
}
/**
* Mask all interrupts
*/
void mask()
{
for (unsigned i=0; i < NR_OF_IRQ; i++)
write<Enclear::Clear_enable>(1, i);
}
/**
* Unmask interrupt
*
* \param interrupt_id kernel name of targeted interrupt
*/
void unmask(unsigned const interrupt_id, unsigned)
{
if (interrupt_id < NR_OF_IRQ) {
write<Enset::Set_enable>(1, interrupt_id);
}
}
/**
* Mask interrupt 'i'
*/
void mask(unsigned const i)
{
if (i < NR_OF_IRQ)
write<Enclear::Clear_enable>(1, i);
}
/**
* Wether an interrupt is inter-processor interrupt of a processor
*
* \param interrupt_id kernel name of the interrupt
* \param processor_id kernel name of the processor
*/
bool is_ip_interrupt(unsigned const interrupt_id,
unsigned const processor_id)
{
return false;
}
/**
* Trigger the inter-processor interrupt of a processor
*
* \param processor_id kernel name of the processor
*/
void trigger_ip_interrupt(unsigned const processor_id) { }
};
}
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

44
repos/base-hw/src/core/imx53/processor_driver.h
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@ -1,44 +0,0 @@
/*
* \brief Processor driver for core
* \author Martin Stein
* \date 2012-12-14
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__PROCESSOR_DRIVER_H_
#define _IMX53__PROCESSOR_DRIVER_H_
/* core includes */
#include <processor_driver/cortex_a8.h>
namespace Genode
{
using Cortex_a8::Processor_lazy_state;
/**
* Processor driver for core
*/
class Processor_driver : public Cortex_a8::Processor_driver
{
public:
/**
* Return kernel name of the primary processor
*/
static unsigned primary_id() { return 0; }
/**
* Return kernel name of the executing processor
*/
static unsigned executing_id() { return primary_id(); }
};
}
#endif /* _IMX53__PROCESSOR_DRIVER_H_ */

48
repos/base-hw/src/core/imx53/timer.h
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@ -1,48 +0,0 @@
/*
* \brief Timer for kernel
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__TIMER_H_
#define _IMX53__TIMER_H_
/* core includes */
#include <board.h>
#include <drivers/timer/epit_base.h>
namespace Imx53
{
/**
* Kernel timer
*/
class Timer : public Genode::Epit_base
{
public:
/**
* Return kernel name of timer interrupt
*/
static unsigned interrupt_id(unsigned)
{
return Board::EPIT_1_IRQ;
}
/**
* Constructor
*/
Timer() : Epit_base(Board::EPIT_1_MMIO_BASE) { }
};
}
namespace Kernel { class Timer : public Imx53::Timer { }; }
#endif /* _IMX53__TIMER_H_ */

0
repos/base-hw/src/core/board.h → repos/base-hw/src/core/include/board.h
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0
repos/base-hw/src/core/kernel/configuration.h → repos/base-hw/src/core/include/kernel/configuration.h
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0
repos/base-hw/src/core/kernel/core_interface.h → repos/base-hw/src/core/include/kernel/core_interface.h
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0
repos/base-hw/src/core/kernel/double_list.h → repos/base-hw/src/core/include/kernel/double_list.h
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0
repos/base-hw/src/core/kernel/ipc_node.h → repos/base-hw/src/core/include/kernel/ipc_node.h
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4
repos/base-hw/src/core/kernel/irq.h → repos/base-hw/src/core/include/kernel/irq.h
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@ -17,9 +17,7 @@
/* Genode includes */
#include <base/native_types.h>
#include <irq_session/irq_session.h>
/* base-hw includes */
#include <placement_new.h>
#include <unmanaged_singleton.h>
/* core includes */
#include <kernel/signal_receiver.h>

0
repos/base-hw/src/core/kernel/kernel.h → repos/base-hw/src/core/include/kernel/kernel.h
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0
repos/base-hw/src/core/kernel/object.h → repos/base-hw/src/core/include/kernel/object.h
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2
repos/base-hw/src/core/kernel/pd.h → repos/base-hw/src/core/include/kernel/pd.h
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@ -38,7 +38,7 @@ extern Genode::addr_t _mt_master_context_end;
namespace Kernel
{
/**
* Lock that enables synchronization inside the kernel
* Lock that enables synchronization inside the kernel
*/
class Lock;
}

19
repos/base-hw/include/kernel/perf_counter.h → repos/base-hw/src/core/include/kernel/perf_counter.h
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@ -11,21 +11,26 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PERF_COUNTER_H_
#define _PERF_COUNTER_H_
namespace Kernel {
#ifndef _KERNEL__PERF_COUNTER_H_
#define _KERNEL__PERF_COUNTER_H_
namespace Kernel
{
/**
* Performance counter
*/
class Perf_counter
{
public:
/**
* Enable counting
*/
void enable();
};
extern Perf_counter *perf_counter();
extern Perf_counter * perf_counter();
}
#endif /* _PERF_COUNTER_H_ */
#endif /* _KERNEL__PERF_COUNTER_H_ */

0
repos/base-hw/src/core/kernel/processor.h → repos/base-hw/src/core/include/kernel/processor.h
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0
repos/base-hw/src/core/kernel/processor_pool.h → repos/base-hw/src/core/include/kernel/processor_pool.h
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0
repos/base-hw/src/core/kernel/scheduler.h → repos/base-hw/src/core/include/kernel/scheduler.h
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0
repos/base-hw/src/core/kernel/signal_receiver.h → repos/base-hw/src/core/include/kernel/signal_receiver.h
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0
repos/base-hw/src/core/kernel/thread.h → repos/base-hw/src/core/include/kernel/thread.h
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0
repos/base-hw/src/core/kernel/thread_event.h → repos/base-hw/src/core/include/kernel/thread_event.h
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0
repos/base-hw/src/core/kernel/vm.h → repos/base-hw/src/core/include/kernel/vm.h
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5
repos/base-hw/src/core/arm/cpu_support.h → repos/base-hw/src/core/include/spec/arm/cpu_support.h
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@ -11,6 +11,9 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _CPU_SUPPORT_H_
#define _CPU_SUPPORT_H_
/* core includes */
#include <kernel/thread_event.h>
@ -39,3 +42,5 @@ class Kernel::Thread_cpu_support
*/
Thread_cpu_support(Thread * const t);
};
#endif /* _CPU_SUPPORT_H_ */

3
repos/base-hw/src/core/arm/macros.s → repos/base-hw/src/core/include/spec/arm/macros_support.s
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@ -11,8 +11,6 @@
* under the terms of the GNU General Public License version 2.
*/
.include "macros_arm.s"
/**
* Calculate and apply kernel SP for a given kernel-stacks area
*
@ -55,4 +53,3 @@
/* alignment constraints */
.set MIN_PAGE_SIZE_LOG2, 12
.set DATA_ACCESS_ALIGNM_LOG2, 2

0
repos/base-hw/src/core/arm/mode_transition.s → repos/base-hw/src/core/include/spec/arm/mode_transition.s
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23
repos/base-hw/src/core/processor_driver/arm.h → repos/base-hw/src/core/include/spec/arm/processor_driver_support.h
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@ -12,8 +12,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PROCESSOR_DRIVER__ARM_H_
#define _PROCESSOR_DRIVER__ARM_H_
#ifndef _SPEC__ARM__PROCESSOR_DRIVER_SUPPORT_H_
#define _SPEC__ARM__PROCESSOR_DRIVER_SUPPORT_H_
/* Genode includes */
#include <util/register.h>
@ -23,15 +23,18 @@
#include <board.h>
#include <util.h>
namespace Arm
namespace Genode
{
using namespace Genode;
/**
* CPU driver for core
*/
struct Processor_driver
{
class Arm;
}
class Genode::Arm
{
public:
enum {
TTBCR_N = 0,
EXCEPTION_ENTRY = 0xffff0000,
@ -710,8 +713,6 @@ namespace Arm
* Return true if the processor support multiple cores
*/
static bool is_smp() { return PROCESSORS > 1; }
};
}
#endif /* _PROCESSOR_DRIVER__ARM_H_ */
};
#endif /* _SPEC__ARM__PROCESSOR_DRIVER_SUPPORT_H_ */

97
repos/base-hw/src/core/arm/short_translation_table.h → repos/base-hw/src/core/include/spec/arm/short_translation_table.h
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@ -12,8 +12,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _ARM__SHORT_TRANSLATION_TABLE_H_
#define _ARM__SHORT_TRANSLATION_TABLE_H_
#ifndef _SPEC__ARM__SHORT_TRANSLATION_TABLE_H_
#define _SPEC__ARM__SHORT_TRANSLATION_TABLE_H_
/* Genode includes */
#include <util/register.h>
@ -24,56 +24,22 @@
#include <page_slab.h>
#include <processor_driver.h>
namespace Arm
namespace Genode
{
using namespace Genode;
/**
* Check if 'p' is aligned to 1 << 'alignm_log2'
*/
inline bool aligned(addr_t const a, size_t const alignm_log2) {
return a == ((a >> alignm_log2) << alignm_log2); }
/**
* Return permission configuration according to given mapping flags
*
* \param T targeted translation-table-descriptor type
* \param flags mapping flags
*
* \return descriptor value with AP and XN set and the rest left zero
*/
template <typename T>
static typename T::access_t
access_permission_bits(Page_flags const & flags)
{
typedef typename T::Xn Xn;
typedef typename T::Ap Ap;
typedef typename T::access_t access_t;
bool const w = flags.writeable;
bool const p = flags.privileged;
access_t ap;
if (w) { if (p) { ap = Ap::bits(0b001); }
else { ap = Ap::bits(0b011); }
} else { if (p) { ap = Ap::bits(0b101); }
else { ap = Ap::bits(0b010); }
}
return Xn::bits(!flags.executable) | ap;
}
/**
* Memory region attributes for the translation descriptor 'T'
*/
template <typename T>
static typename T::access_t
memory_region_attr(Page_flags const & flags);
arm_memory_region_attr(Page_flags const & flags);
class Section_table;
/**
* First level translation table
*/
class Translation_table;
}
/**
* First level translation table
*/
class Arm::Section_table
class Genode::Translation_table
{
public:
@ -87,6 +53,38 @@ class Arm::Section_table
private:
/**
* Check if 'p' is aligned to 1 << 'alignm_log2'
*/
static inline bool aligned(addr_t const a, size_t const alignm_log2) {
return a == ((a >> alignm_log2) << alignm_log2); }
/**
* Return permission configuration according to given mapping flags
*
* \param T targeted translation-table-descriptor type
* \param flags mapping flags
*
* \return descriptor value with AP and XN set and the rest left zero
*/
template <typename T>
static typename T::access_t
access_permission_bits(Page_flags const & flags)
{
typedef typename T::Xn Xn;
typedef typename T::Ap Ap;
typedef typename T::access_t access_t;
bool const w = flags.writeable;
bool const p = flags.privileged;
access_t ap;
if (w) { if (p) { ap = Ap::bits(0b001); }
else { ap = Ap::bits(0b011); }
} else { if (p) { ap = Ap::bits(0b101); }
else { ap = Ap::bits(0b010); }
}
return Xn::bits(!flags.executable) | ap;
}
/**
* Second level translation table
*/
@ -183,7 +181,7 @@ class Arm::Section_table
addr_t const pa)
{
access_t v = access_permission_bits<Small_page>(flags);
v |= memory_region_attr<Small_page>(flags);
v |= arm_memory_region_attr<Small_page>(flags);
v |= Ng::bits(!flags.global);
v |= S::bits(Processor_driver::is_smp());
v |= Pa::masked(pa);
@ -451,7 +449,7 @@ class Arm::Section_table
addr_t const pa)
{
access_t v = access_permission_bits<Section>(flags);
v |= memory_region_attr<Section>(flags);
v |= arm_memory_region_attr<Section>(flags);
v |= Domain::bits(DOMAIN);
v |= S::bits(Processor_driver::is_smp());
v |= Ng::bits(!flags.global);
@ -553,7 +551,7 @@ class Arm::Section_table
/**
* Constructor
*/
Section_table()
Translation_table()
{
if (!aligned((addr_t)this, ALIGNM_LOG2))
throw Misaligned();
@ -682,9 +680,6 @@ class Arm::Section_table
vo += sz;
}
}
} __attribute__((aligned(1<<Section_table::ALIGNM_LOG2)));
namespace Genode { using Translation_table = Arm::Section_table; }
#endif /* _ARM__SHORT_TRANSLATION_TABLE_H_ */
} __attribute__((aligned(1<<Translation_table::ALIGNM_LOG2)));
#endif /* _SPEC__ARM__SHORT_TRANSLATION_TABLE_H_ */

44
repos/base-hw/src/core/pic/arm_gic.h → repos/base-hw/src/core/include/spec/arm_gic/pic_support.h
View File

@ -11,25 +11,21 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC__ARM_GIC_H_
#define _PIC__ARM_GIC_H_
#ifndef _SPEC__ARM_GIC__PIC_SUPPORT_H_
#define _SPEC__ARM_GIC__PIC_SUPPORT_H_
/* Genode includes */
#include <util/mmio.h>
namespace Arm_gic
namespace Genode
{
using namespace Genode;
/**
* Programmable interrupt controller for core
*
* ARM generic interrupt controller, Architecture version 2.0
*/
class Pic;
class Arm_gic;
}
class Arm_gic::Pic
class Genode::Arm_gic
{
public:
@ -225,11 +221,6 @@ class Arm_gic::Pic
unsigned const _max_interrupt;
unsigned _last_request;
/**
* Wether the security extension is used or not
*/
inline static bool _use_security_ext();
/**
* Return inter-processor interrupt of a specific processor
*
@ -240,31 +231,23 @@ class Arm_gic::Pic
return processor_id + 1;
}
/**
* Platform specific initialization
*/
void _init();
public:
/**
* Constructor
*/
Pic(addr_t const distr_base, addr_t const cpu_base)
Arm_gic(addr_t const distr_base, addr_t const cpu_base)
:
_distr(distr_base), _cpu(cpu_base),
_max_interrupt(_distr.max_interrupt()),
_last_request(SPURIOUS_ID)
{
/* with security extension any board has its own init */
if (_use_security_ext()) return;
/* disable device */
_distr.write<Distr::Ctlr::Enable>(0);
/* configure every shared peripheral interrupt */
for (unsigned i=MIN_SPI; i <= _max_interrupt; i++)
{
_distr.write<Distr::Icfgr::Edge_triggered>(0, i);
_distr.write<Distr::Ipriorityr::Priority>(_distr.max_priority(), i);
}
/* enable device */
_distr.write<Distr::Ctlr::Enable>(1);
_init();
}
/**
@ -383,5 +366,4 @@ class Arm_gic::Pic
}
};
#endif /* _PIC__ARM_GIC_H_ */
#endif /* _SPEC__ARM_GIC__PIC_SUPPORT_H_ */

2
repos/base-hw/src/core/arm_v6/macros_arm.s → repos/base-hw/src/core/include/spec/arm_v6/macros.s
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@ -11,6 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
/* core includes */
.include "spec/arm/macros_support.s"
/**
* Determine the kernel name of the executing processor

72
repos/base-hw/src/core/processor_driver/arm_v6.h → repos/base-hw/src/core/include/spec/arm_v6/processor_driver.h
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@ -12,20 +12,16 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PROCESSOR_DRIVER__ARM_V6_H_
#define _PROCESSOR_DRIVER__ARM_V6_H_
/* Genode includes */
#include <base/printf.h>
#ifndef _PROCESSOR_DRIVER_H_
#define _PROCESSOR_DRIVER_H_
/* core includes */
#include <processor_driver/arm.h>
#include <spec/arm/processor_driver_support.h>
#include <assert.h>
#include <board.h>
namespace Arm_v6
namespace Genode
{
using namespace Genode;
/**
* Part of processor state that is not switched on every mode transition
*/
@ -34,12 +30,17 @@ namespace Arm_v6
/**
* Processor driver for core
*/
struct Processor_driver : Arm::Processor_driver
{
class Processor_driver;
}
class Genode::Processor_driver : public Arm
{
public:
/**
* Cache type register
*/
struct Ctr : Arm::Processor_driver::Ctr
struct Ctr : Arm::Ctr
{
struct P : Bitfield<23, 1> { }; /* page mapping restriction on */
};
@ -47,7 +48,7 @@ namespace Arm_v6
/**
* System control register
*/
struct Sctlr : Arm::Processor_driver::Sctlr
struct Sctlr : Arm::Sctlr
{
struct W : Bitfield<3,1> { }; /* enable write buffer */
@ -80,7 +81,7 @@ namespace Arm_v6
static access_t init_virt_kernel()
{
return base_value() |
Arm::Processor_driver::Sctlr::init_virt_kernel() |
Arm::Sctlr::init_virt_kernel() |
W::bits(0) |
B::bits(B::LITTLE) |
S::bits(0) |
@ -98,7 +99,7 @@ namespace Arm_v6
static access_t init_phys_kernel()
{
return base_value() |
Arm::Processor_driver::Sctlr::init_phys_kernel() |
Arm::Sctlr::init_phys_kernel() |
W::bits(0) |
B::bits(B::LITTLE) |
S::bits(0) |
@ -114,7 +115,7 @@ namespace Arm_v6
/**
* Translation table base control register 0
*/
struct Ttbr0 : Arm::Processor_driver::Ttbr0
struct Ttbr0 : Arm::Ttbr0
{
struct C : Bitfield<0,1> /* inner cachable mode */
{
@ -130,7 +131,7 @@ namespace Arm_v6
*/
static access_t init_virt_kernel(addr_t const sect_table)
{
return Arm::Processor_driver::Ttbr0::init_virt_kernel(sect_table) |
return Arm::Ttbr0::init_virt_kernel(sect_table) |
P::bits(0) |
C::bits(C::NON_CACHEABLE);
}
@ -152,10 +153,7 @@ namespace Arm_v6
flush_tlb();
/* check for mapping restrictions */
if (restricted_page_mappings()) {
PDBG("Insufficient driver for page tables");
while (1) ;
}
assert(!restricted_page_mappings());
}
/**
@ -182,7 +180,7 @@ namespace Arm_v6
static void start_secondary_processors(void * const ip)
{
if (is_smp()) { PERR("multiprocessing not implemented"); }
assert(!is_smp());
}
/**
@ -232,37 +230,35 @@ namespace Arm_v6
bool retry_undefined_instr(Processor_lazy_state *) { return false; }
/**
* The ARM1176JZF-S processor cannot page table walk from level one cache.
* Therefore, as the page-tables lie in write-back cacheable memory we've
* to clean the corresponding cache-lines even when a page table entry is added
* Post processing after a translation was added to a translation table
*
* \param addr virtual address of the translation
* \param size size of the translation
*/
static void translation_added(Genode::addr_t addr, Genode::size_t size)
static void translation_added(addr_t const addr, size_t const size)
{
/*
* only clean lines as core, the kernel adds entries
* before MMU and caches are enabled
* The Cortex A8 processor can't use the L1 cache on page-table
* walks. Therefore, as the page-tables lie in write-back cacheable
* memory we've to clean the corresponding cache-lines even when a
* page table entry is added. We only do this as core as the kernel
* adds translations solely before MMU and caches are enabled.
*/
if (is_user()) Kernel::update_data_region(addr, size);
}
};
}
};
/***************************
** Arm::Processor_driver **
***************************/
void Arm::Processor_driver::flush_data_caches()
void Genode::Arm::flush_data_caches()
{
asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : );
}
void Arm::Processor_driver::invalidate_data_caches()
void Genode::Arm::invalidate_data_caches()
{
asm volatile ("mcr p15, 0, %[rd], c7, c6, 0" :: [rd]"r"(0) : );
}
#endif /* _PROCESSOR_DRIVER__ARM_V6_H_ */
#endif /* _PROCESSOR_DRIVER_H_ */

10
repos/base-hw/src/core/arm_v6/translation_table.h → repos/base-hw/src/core/include/spec/arm_v6/translation_table.h
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@ -12,15 +12,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _ARM_V6__TRANSLATION_TABLE_H_
#define _ARM_V6__TRANSLATION_TABLE_H_
#ifndef _TRANSLATION_TABLE_H_
#define _TRANSLATION_TABLE_H_
/* core includes */
#include <arm/short_translation_table.h>
#include <spec/arm/short_translation_table.h>
template <typename T>
static typename T::access_t
Arm::memory_region_attr(Page_flags const & flags)
Genode::arm_memory_region_attr(Page_flags const & flags)
{
typedef typename T::Tex Tex;
typedef typename T::C C;
@ -35,4 +35,4 @@ Arm::memory_region_attr(Page_flags const & flags)
return 0;
}
#endif /* _ARM_V6__TRANSLATION_TABLE_H_ */
#endif /* _TRANSLATION_TABLE_H_ */

2
repos/base-hw/src/core/arm_v7/macros_arm.s → repos/base-hw/src/core/include/spec/arm_v7/macros.s
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@ -11,6 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
/* core includes */
.include "spec/arm/macros_support.s"
/**
* Determine the kernel name of the executing processor

93
repos/base-hw/src/core/processor_driver/arm_v7.h → repos/base-hw/src/core/include/spec/arm_v7/processor_driver_support.h
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@ -11,11 +11,11 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PROCESSOR_DRIVER__ARM_V7_H_
#define _PROCESSOR_DRIVER__ARM_V7_H_
#ifndef _SPEC__ARM_V7__PROCESSOR_DRIVER_SUPPORT_H_
#define _SPEC__ARM_V7__PROCESSOR_DRIVER_SUPPORT_H_
/* core includes */
#include <processor_driver/arm.h>
#include <spec/arm/processor_driver_support.h>
#include <board.h>
/**
@ -102,44 +102,47 @@
*/
#define FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1 \
\
/* decrement the index */ \
"subs r7, r7, #1\n" \
/* decrement the index */ \
"subs r7, r7, #1\n" \
\
/* end loop over indices */ \
"bge 3b\n" \
/* end loop over indices */ \
"bge 3b\n" \
\
/* decrement the way number */ \
"subs r8, r8, #1\n" \
/* decrement the way number */ \
"subs r8, r8, #1\n" \
\
/* end loop over way numbers */ \
"bge 2b\n" \
/* end loop over way numbers */ \
"bge 2b\n" \
\
/* label to skip a cache number */ \
"4:\n" \
/* label to skip a cache number */ \
"4:\n" \
\
/* increment the cache number */ \
"add r9, r9, #2\n" \
"cmp r3, r9\n" \
/* increment the cache number */ \
"add r9, r9, #2\n" \
"cmp r3, r9\n" \
\
/* end loop over cache numbers */ \
"bgt 1b\n" \
/* end loop over cache numbers */ \
"bgt 1b\n" \
\
/* synchronize data */ \
"dsb\n" \
/* synchronize data */ \
"dsb\n" \
\
/* label to skip all */ \
"5:\n" \
::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
/* label to skip all */ \
"5:\n" \
::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
namespace Arm_v7
namespace Genode
{
using namespace Genode;
/**
* CPU driver for core
*/
struct Processor_driver : Arm::Processor_driver
{
class Arm_v7;
}
class Genode::Arm_v7 : public Arm
{
protected:
/**
* Secure configuration register
*/
@ -174,7 +177,7 @@ namespace Arm_v7
/**
* System control register
*/
struct Sctlr : Arm::Processor_driver::Sctlr
struct Sctlr : Arm::Sctlr
{
struct Unused_0 : Bitfield<3,4> { }; /* shall be ~0 */
struct Sw : Bitfield<10,1> { }; /* support SWP and SWPB */
@ -209,7 +212,7 @@ namespace Arm_v7
static access_t init_phys_kernel()
{
return base_value() |
Arm::Processor_driver::Sctlr::init_phys_kernel() |
Arm::Sctlr::init_phys_kernel() |
Sw::bits(0) |
Ha::bits(0) |
Nmfi::bits(0) |
@ -222,7 +225,7 @@ namespace Arm_v7
static access_t init_virt_kernel()
{
return base_value() |
Arm::Processor_driver::Sctlr::init_virt_kernel() |
Arm::Sctlr::init_virt_kernel() |
Sw::bits(0) |
Ha::bits(0) |
Nmfi::bits(0) |
@ -233,7 +236,7 @@ namespace Arm_v7
/**
* Translation table base register 0
*/
struct Ttbr0 : Arm::Processor_driver::Ttbr0
struct Ttbr0 : Arm::Ttbr0
{
struct Nos : Bitfield<5,1> { }; /* not outer shareable */
@ -247,7 +250,7 @@ namespace Arm_v7
*/
static access_t init_virt_kernel(addr_t const sect_table)
{
return Arm::Processor_driver::Ttbr0::init_virt_kernel(sect_table) |
return Arm::Ttbr0::init_virt_kernel(sect_table) |
Nos::bits(0) |
Irgn_1::bits(0) |
Irgn_0::bits(1);
@ -257,7 +260,7 @@ namespace Arm_v7
/**
* Translation table base control register
*/
struct Ttbcr : Arm::Processor_driver::Ttbcr
struct Ttbcr : Arm::Ttbcr
{
struct Pd0 : Bitfield<4,1> { }; /* disable walk for TTBR0 */
struct Pd1 : Bitfield<5,1> { }; /* disable walk for TTBR1 */
@ -267,12 +270,14 @@ namespace Arm_v7
*/
static access_t init_virt_kernel()
{
return Arm::Processor_driver::Ttbcr::init_virt_kernel() |
return Arm::Ttbcr::init_virt_kernel() |
Pd0::bits(0) |
Pd1::bits(0);
}
};
public:
/**
* Switch to the virtual mode in kernel
*
@ -360,7 +365,7 @@ namespace Arm_v7
static void start_secondary_processors(void * const ip)
{
if (is_smp()) {
Genode::Board::secondary_processors_ip(ip);
Board::secondary_processors_ip(ip);
data_synchronization_barrier();
asm volatile ("sev\n");
}
@ -370,15 +375,10 @@ namespace Arm_v7
* Wait for the next interrupt as cheap as possible
*/
static void wait_for_interrupt() { asm volatile ("wfi"); }
};
}
};
/***************************
** Arm::Processor_driver **
***************************/
void Arm::Processor_driver::flush_data_caches()
void Genode::Arm::flush_data_caches()
{
asm volatile (
FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0
@ -388,7 +388,7 @@ void Arm::Processor_driver::flush_data_caches()
}
void Arm::Processor_driver::invalidate_data_caches()
void Genode::Arm::invalidate_data_caches()
{
asm volatile (
FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0
@ -398,7 +398,8 @@ void Arm::Processor_driver::invalidate_data_caches()
}
Arm::Processor_driver::Psr::access_t Arm::Processor_driver::Psr::init_user_with_trustzone()
Genode::Arm::Psr::access_t
Genode::Arm::Psr::init_user_with_trustzone()
{
return M::bits(M::USER) |
T::bits(T::ARM) |
@ -410,5 +411,5 @@ Arm::Processor_driver::Psr::access_t Arm::Processor_driver::Psr::init_user_with_
}
#endif /* _PROCESSOR_DRIVER__ARM_V7_H_ */
#endif /* _SPEC__ARM_V7__PROCESSOR_DRIVER_SUPPORT_H_ */

10
repos/base-hw/src/core/arm_v7/translation_table.h → repos/base-hw/src/core/include/spec/arm_v7/translation_table.h
View File

@ -12,15 +12,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _ARM_V7__TRANSLATION_TABLE_H_
#define _ARM_V7__TRANSLATION_TABLE_H_
#ifndef _TRANSLATION_TABLE_H_
#define _TRANSLATION_TABLE_H_
/* core includes */
#include <arm/short_translation_table.h>
#include <spec/arm/short_translation_table.h>
template <typename T>
static typename T::access_t
Arm::memory_region_attr(Page_flags const & flags)
Genode::arm_memory_region_attr(Page_flags const & flags)
{
typedef typename T::Tex Tex;
typedef typename T::C C;
@ -35,4 +35,4 @@ Arm::memory_region_attr(Page_flags const & flags)
return 0;
}
#endif /* _ARM_V7__TRANSLATION_TABLE_H_ */
#endif /* _TRANSLATION_TABLE_H_ */

0
repos/base-hw/src/core/arndale/board.h → repos/base-hw/src/core/include/spec/arndale/board.h
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13
repos/base-hw/src/core/arndale/processor_driver.h → repos/base-hw/src/core/include/spec/arndale/processor_driver.h
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@ -11,20 +11,18 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _ARNDALE__PROCESSOR_DRIVER_H_
#define _ARNDALE__PROCESSOR_DRIVER_H_
#ifndef _PROCESSOR_DRIVER_H_
#define _PROCESSOR_DRIVER_H_
/* core includes */
#include <processor_driver/cortex_a15.h>
#include <spec/cortex_a15/processor_driver_support.h>
namespace Genode
{
using Cortex_a15::Processor_lazy_state;
/**
* Processor driver for core
*/
class Processor_driver : public Cortex_a15::Processor_driver
class Processor_driver : public Cortex_a15
{
public:
@ -43,5 +41,4 @@ namespace Genode
};
}
#endif /* _ARNDALE__PROCESSOR_DRIVER_H_ */
#endif /* _PROCESSOR_DRIVER_H_ */

49
repos/base-hw/src/core/include/spec/corelink_gic400/pic.h Normal file
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@ -0,0 +1,49 @@
/*
* \brief Programmable interrupt controller for core
* \author Martin stein
* \date 2013-01-22
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
/* core includes */
#include <spec/arm_gic/pic_support.h>
#include <board.h>
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : public Arm_gic
{
private:
enum {
BASE = Board::GIC_CPU_MMIO_BASE,
DISTR_BASE = BASE + 0x1000,
CPUI_BASE = BASE + 0x2000,
};
public:
/**
* Constructor
*/
Pic() : Arm_gic(DISTR_BASE, CPUI_BASE) { }
};
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

56
repos/base-hw/src/core/include/spec/cortex_a15/processor_driver_support.h Normal file
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@ -0,0 +1,56 @@
/*
* \brief Processor driver for core
* \author Martin stein
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _SPEC__CORTEX_A15__PROCESSOR_DRIVER_SUPPORT_H_
#define _SPEC__CORTEX_A15__PROCESSOR_DRIVER_SUPPORT_H_
/* core includes */
#include <spec/arm_v7/processor_driver_support.h>
namespace Genode
{
/**
* Part of processor state that is not switched on every mode transition
*/
class Processor_lazy_state { };
/**
* Processor driver for core
*/
class Cortex_a15;
}
class Genode::Cortex_a15 : public Arm_v7
{
public:
/**
* Return wether to retry an undefined user instruction after this call
*/
bool retry_undefined_instr(Processor_lazy_state *) { return false; }
/*************
** Dummies **
*************/
static void tlb_insertions() { }
static void translation_added(addr_t, size_t) { }
static void prepare_proceeding(Processor_lazy_state *,
Processor_lazy_state *) { }
};
void Genode::Arm_v7::finish_init_phys_kernel() { }
#endif /* _SPEC__CORTEX_A15__PROCESSOR_DRIVER_SUPPORT_H_ */

86
repos/base-hw/src/core/include/spec/cortex_a8/processor_driver.h Normal file
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@ -0,0 +1,86 @@
/*
* \brief Processor driver for core
* \author Martin stein
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PROCESSOR_DRIVER_H_
#define _PROCESSOR_DRIVER_H_
/* core includes */
#include <spec/arm_v7/processor_driver_support.h>
namespace Genode
{
/**
* Part of processor state that is not switched on every mode transition
*/
class Processor_lazy_state { };
/**
* Processor driver for core
*/
class Processor_driver;
}
class Genode::Processor_driver : public Arm_v7
{
public:
/**
* Ensure that TLB insertions get applied
*/
static void tlb_insertions() { flush_tlb(); }
/**
* Prepare for the proceeding of a user
*/
static void prepare_proceeding(Processor_lazy_state *,
Processor_lazy_state *) { }
/**
* Return wether to retry an undefined user instruction after this call
*/
bool retry_undefined_instr(Processor_lazy_state *) { return false; }
/**
* Post processing after a translation was added to a translation table
*
* \param addr virtual address of the translation
* \param size size of the translation
*/
static void translation_added(addr_t const addr, size_t const size)
{
/*
* The Cortex A8 processor can't use the L1 cache on page-table
* walks. Therefore, as the page-tables lie in write-back cacheable
* memory we've to clean the corresponding cache-lines even when a
* page table entry is added. We only do this as core as the kernel
* adds translations solely before MMU and caches are enabled.
*/
if (is_user()) Kernel::update_data_region(addr, size);
}
/**
* Return kernel name of the primary processor
*/
static unsigned primary_id() { return 0; }
/**
* Return kernel name of the executing processor
*/
static unsigned executing_id() { return primary_id(); }
};
void Genode::Arm_v7::finish_init_phys_kernel() { }
#endif /* _PROCESSOR_DRIVER_H_ */

49
repos/base-hw/src/core/include/spec/cortex_a9/pic.h Normal file
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@ -0,0 +1,49 @@
/*
* \brief Programmable interrupt controller for core
* \author Martin stein
* \date 2011-10-26
*/
/*
* Copyright (C) 2011-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
/* core includes */
#include <spec/arm_gic/pic_support.h>
#include <processor_driver.h>
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : public Arm_gic
{
private:
public:
/**
* Constructor
*/
Pic() : Arm_gic(Processor_driver::PL390_DISTRIBUTOR_MMIO_BASE,
Processor_driver::PL390_CPU_MMIO_BASE) { }
/**
* Mark interrupt 'i' unsecure
*/
void unsecure(unsigned const i);
};
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

44
repos/base-hw/src/core/processor_driver/cortex_a9.h → repos/base-hw/src/core/include/spec/cortex_a9/processor_driver.h
View File

@ -11,17 +11,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PROCESSOR_DRIVER__CORTEX_A9_H_
#define _PROCESSOR_DRIVER__CORTEX_A9_H_
#ifndef _PROCESSOR_DRIVER_H_
#define _PROCESSOR_DRIVER_H_
/* core includes */
#include <processor_driver/arm_v7.h>
#include <spec/arm_v7/processor_driver_support.h>
#include <board.h>
namespace Cortex_a9
namespace Genode
{
using namespace Genode;
/**
* Part of processor state that is not switched on every mode transition
*/
@ -33,7 +31,7 @@ namespace Cortex_a9
class Processor_driver;
}
class Cortex_a9::Processor_lazy_state
class Genode::Processor_lazy_state
{
friend class Processor_driver;
@ -55,7 +53,7 @@ class Cortex_a9::Processor_lazy_state
inline Processor_lazy_state();
};
class Cortex_a9::Processor_driver : public Arm_v7::Processor_driver
class Genode::Processor_driver : public Arm_v7
{
friend class Processor_lazy_state;
@ -296,33 +294,31 @@ class Cortex_a9::Processor_driver : public Arm_v7::Processor_driver
*/
static void translation_added(Genode::addr_t addr,
Genode::size_t size) { }
/**
* Return kernel name of the primary processor
*/
static unsigned primary_id() { return 0; }
/**
* Return kernel name of the executing processor
*/
static unsigned executing_id() { return primary_id(); }
};
/******************************
** Arm_v7::Processor_driver **
******************************/
void Arm_v7::Processor_driver::finish_init_phys_kernel()
void Genode::Arm_v7::finish_init_phys_kernel()
{
Cortex_a9::Processor_driver::init_advanced_fp_simd();
Processor_driver::init_advanced_fp_simd();
}
/*************************************
** Cortex_a9::Processor_lazy_state **
*************************************/
Cortex_a9::Processor_lazy_state::Processor_lazy_state()
Genode::Processor_lazy_state::Processor_lazy_state()
{
fpexc = Processor_driver::Fpexc::En::bits(1);
}
/*****************
** Annotations **
*****************/
/*
* Annotation 1
*
@ -343,4 +339,4 @@ Cortex_a9::Processor_lazy_state::Processor_lazy_state()
* head branch as from 2014.04.17.
*/
#endif /* _PROCESSOR_DRIVER__CORTEX_A9_H_ */
#endif /* _PROCESSOR_DRIVER_H_ */

13
repos/base-hw/src/core/timer/cortex_a9.h → repos/base-hw/src/core/include/spec/cortex_a9/timer.h
View File

@ -1,5 +1,5 @@
/*
* \brief Timer for core
* \brief Timer driver for core
* \author Martin stein
* \date 2011-12-13
*/
@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _TIMER__CORTEX_A9_H_
#define _TIMER__CORTEX_A9_H_
#ifndef _TIMER_H_
#define _TIMER_H_
/* Genode includes */
#include <util/mmio.h>
@ -20,10 +20,10 @@
/* core includes */
#include <processor_driver.h>
namespace Cortex_a9
namespace Genode
{
/**
* Timer for core
* Timer driver for core
*/
class Timer : public Mmio
{
@ -105,5 +105,6 @@ namespace Cortex_a9
};
}
#endif /* _TIMER__CORTEX_A9_H_ */
namespace Kernel { class Timer : public Genode::Timer { }; }
#endif /* _TIMER_H_ */

20
repos/base-hw/include/exynos5_uart/drivers/serial_log.h → repos/base-hw/src/core/include/spec/exynos5/serial.h
View File

@ -1,5 +1,5 @@
/*
* \brief Serial output driver for console lib
* \brief Serial output driver for core
* \author Martin Stein
* \author Stefan Kalkowski
* \date 2013-01-09
@ -12,19 +12,21 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__EXYNOS_UART__DRIVERS__SERIAL_LOG_H_
#define _INCLUDE__EXYNOS_UART__DRIVERS__SERIAL_LOG_H_
#ifndef _SERIAL_H_
#define _SERIAL_H_
/* core includes */
#include <board.h>
/* Genode includes */
#include <board.h>
#include <drivers/uart/exynos_uart_base.h>
namespace Genode
{
/**
* Serial output driver for console lib
* Serial output driver for core
*/
class Serial_log : public Exynos_uart_base
class Serial : public Exynos_uart_base
{
public:
@ -33,12 +35,12 @@ namespace Genode
*
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Serial(unsigned const baud_rate)
:
Exynos_uart_base(Board::UART_2_MMIO_BASE,
Board::UART_2_CLOCK, baud_rate)
{ }
};
}
#endif /* _INCLUDE__EXYNOS_UART__DRIVERS__SERIAL_LOG_H_ */
#endif /* _SERIAL_H_ */

286
repos/base-hw/src/core/include/spec/exynos5/timer.h Normal file
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@ -0,0 +1,286 @@
/*
* \brief Timer driver for core
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _TIMER_H_
#define _TIMER_H_
/* core include */
#include <board.h>
/* Genode includes */
#include <util/mmio.h>
namespace Genode
{
/**
* Timer driver for core
*/
class Timer;
}
class Genode::Timer : public Mmio
{
private:
enum {
PRESCALER = 1,
DIV_MUX = 0,
};
/**
* MCT configuration
*/
struct Mct_cfg : Register<0x0, 32>
{
struct Prescaler : Bitfield<0, 8> { };
struct Div_mux : Bitfield<8, 3> { };
};
/*******************
** Local timer 0 **
*******************/
/**
* Free running counter buffer
*/
struct L0_frcntb : Register<0x310, 32> { };
/**
* Configuration
*/
struct L0_tcon : Register<0x320, 32>
{
struct Frc_start : Bitfield<3, 1> { };
};
/**
* Expired status
*/
struct L0_int_cstat : Register<0x330, 32, true>
{
struct Frcnt : Bitfield<1, 1> { };
};
/**
* Interrupt enable
*/
struct L0_int_enb : Register<0x334, 32>
{
struct Frceie : Bitfield<1, 1> { };
};
/**
* Write status
*/
struct L0_wstat : Register<0x340, 32, true>
{
struct Frcntb : Bitfield<2, 1> { };
struct Tcon : Bitfield<3, 1> { };
};
struct L0_frcnto : Register<0x314, 32> { };
/**
* Start and stop counting
*/
void _run_0(bool const run)
{
_acked_write<L0_tcon, L0_wstat::Tcon>
(L0_tcon::Frc_start::bits(run));
}
/*******************
** Local timer 1 **
*******************/
/**
* Free running counter buffer
*/
struct L1_frcntb : Register<0x410, 32> { };
/**
* Configuration
*/
struct L1_tcon : Register<0x420, 32>
{
struct Frc_start : Bitfield<3, 1> { };
};
/**
* Expired status
*/
struct L1_int_cstat : Register<0x430, 32, true>
{
struct Frcnt : Bitfield<1, 1> { };
};
/**
* Interrupt enable
*/
struct L1_int_enb : Register<0x434, 32>
{
struct Frceie : Bitfield<1, 1> { };
};
/**
* Write status
*/
struct L1_wstat : Register<0x440, 32, true>
{
struct Frcntb : Bitfield<2, 1> { };
struct Tcon : Bitfield<3, 1> { };
};
struct L1_frcnto : Register<0x414, 32> { };
/**
* Start and stop counting
*/
void _run_1(bool const run)
{
_acked_write<L1_tcon, L1_wstat::Tcon>
(L1_tcon::Frc_start::bits(run));
}
/********************
** Helper methods **
********************/
/**
* Write to reg that replies via ack bit and clear ack bit
*/
template <typename DEST, typename ACK>
void _acked_write(typename DEST::Register_base::access_t const v)
{
typedef typename DEST::Register_base Dest;
typedef typename ACK::Bitfield_base Ack;
write<Dest>(v);
while (!read<Ack>());
write<Ack>(1);
}
/**
* Calculate amount of tics per ms for specific input clock
*
* \param clock input clock
*/
unsigned static _calc_tics_per_ms(unsigned const clock)
{
return clock / (PRESCALER + 1) / (1 << DIV_MUX) / 1000;
}
unsigned const _tics_per_ms;
public:
/**
* Return kernel name of timer interrupt of a specific processor
*
* \param processor_id kernel name of targeted processor
*/
static unsigned interrupt_id(unsigned const processor_id)
{
switch (processor_id) {
case 0: return Board::MCT_IRQ_L0;
case 1: return Board::MCT_IRQ_L1;
default: return 0;
}
}
/**
* Constructor
*/
Timer()
:
Mmio(Board::MCT_MMIO_BASE),
_tics_per_ms(_calc_tics_per_ms(Board::MCT_CLOCK))
{
Mct_cfg::access_t mct_cfg = 0;
Mct_cfg::Prescaler::set(mct_cfg, PRESCALER);
Mct_cfg::Div_mux::set(mct_cfg, DIV_MUX);
write<Mct_cfg>(mct_cfg);
write<L0_int_enb>(L0_int_enb::Frceie::bits(1));
write<L1_int_enb>(L1_int_enb::Frceie::bits(1));
}
/**
* Start single timeout run
*
* \param tics delay of timer interrupt
* \param processor_id kernel name of processor of targeted timer
*/
inline void start_one_shot(unsigned const tics,
unsigned const processor_id)
{
switch (processor_id) {
case 0:
_run_0(0);
_acked_write<L0_frcntb, L0_wstat::Frcntb>(tics);
_run_0(1);
return;
case 1:
_run_1(0);
_acked_write<L1_frcntb, L1_wstat::Frcntb>(tics);
_run_1(1);
return;
default: return;
}
}
/**
* Translate 'ms' milliseconds to a native timer value
*/
unsigned ms_to_tics(unsigned const ms) { return ms * _tics_per_ms; }
/**
* Clear interrupt output line
*/
void clear_interrupt(unsigned const processor_id)
{
switch (processor_id) {
case 0:
write<L0_int_cstat::Frcnt>(1);
return;
case 1:
write<L1_int_cstat::Frcnt>(1);
return;
default: return;
}
}
unsigned value(unsigned const processor_id)
{
switch (processor_id) {
case 0: return read<L0_frcnto>();
case 1: return read<L1_frcnto>();
default: return 0;
}
}
unsigned irq_state(unsigned const processor_id)
{
switch (processor_id) {
case 0: return read<L0_int_cstat::Frcnt>();
case 1: return read<L1_int_cstat::Frcnt>();
default: return 0;
}
}
};
namespace Kernel { class Timer : public Genode::Timer { }; }
#endif /* _TIMER_H_ */

41
repos/base-hw/src/core/include/spec/imx/serial.h Normal file
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@ -0,0 +1,41 @@
/*
* \brief Serial output driver for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _SERIAL_H_
#define _SERIAL_H_
/* core includes */
#include <board.h>
/* Genode includes */
#include <drivers/uart/imx31_uart_base.h>
namespace Genode
{
/**
* Serial output driver for core
*/
class Serial : public Imx31_uart_base
{
public:
/**
* Constructor
*
* XXX: The 'baud_rate' argument is ignored for now.
*/
Serial(unsigned) : Imx31_uart_base(Board::UART_1_MMIO_BASE) { }
};
}
#endif /* _SERIAL_H_ */

48
repos/base-hw/src/core/include/spec/imx/timer.h Normal file
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@ -0,0 +1,48 @@
/*
* \brief Timer driver for core
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _TIMER_H_
#define _TIMER_H_
/* Genode includes */
#include <drivers/timer/epit_base.h>
/* core includes */
#include <board.h>
namespace Genode
{
/**
* Timer driver for core
*/
class Timer;
}
class Genode::Timer : public Epit_base
{
public:
/**
* Return kernel name of timer interrupt
*/
static unsigned interrupt_id(unsigned) { return Board::EPIT_1_IRQ; }
/**
* Constructor
*/
Timer() : Epit_base(Board::EPIT_1_MMIO_BASE) { }
};
namespace Kernel { class Timer : public Genode::Timer { }; }
#endif /* _TIMER_H_ */

6
repos/base-hw/src/core/imx31/board.h → repos/base-hw/src/core/include/spec/imx31/board.h
View File

@ -4,8 +4,8 @@
* \date 2012-11-01
*/
#ifndef _BOARD__IMX31_H_
#define _BOARD__IMX31_H_
#ifndef _BOARD_H_
#define _BOARD_H_
/* Genode includes */
#include <drivers/board_base.h>
@ -98,4 +98,4 @@ namespace Genode
};
}
#endif /* _BOARD__IMX31_H_ */
#endif /* _BOARD_H_ */

214
repos/base-hw/src/core/include/spec/imx31/pic.h Normal file
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@ -0,0 +1,214 @@
/*
* \brief Programmable interrupt controller for core
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : public Mmio
{
/**
* Interrupt control register
*/
struct Intcntl : Register<0x0, 32>
{
struct Nm : Bitfield<18,1> /* IRQ mode */
{
enum { SW_CONTROL = 0 };
};
struct Fiad : Bitfield<19,1> { }; /* FIQ rises prio in arbiter */
struct Niad : Bitfield<20,1> { }; /* IRQ rises prio in arbiter */
struct Fidis : Bitfield<21,1> { }; /* FIQ disable */
struct Nidis : Bitfield<22,1> { }; /* IRQ disable */
struct Abfen : Bitfield<24,1> { }; /* if ABFLAG is sticky */
struct Abflag : Bitfield<25,1> { }; /* rise prio in bus arbiter */
static access_t init_value()
{
return Nm::bits(Nm::SW_CONTROL) |
Fiad::bits(0) |
Niad::bits(0) |
Fidis::bits(0) |
Nidis::bits(0) |
Abfen::bits(0) |
Abflag::bits(0);
}
};
/**
* Normal interrupt mask register
*/
struct Nimask : Register<0x4, 32>
{
enum { NONE_MASKED = ~0 };
};
/**
* Interrupt enable number register
*/
struct Intennum : Register<0x8, 32>
{
struct Enable : Bitfield<0,6> { };
};
/**
* Interrupt disable number register
*/
struct Intdisnum : Register<0xc, 32>
{
struct Disable : Bitfield<0,6> { };
};
/**
* Interrupt enable register
*/
struct Intenableh : Register<0x10, 32> { };
struct Intenablel : Register<0x14, 32> { };
/**
* Interrupt type register
*/
struct Inttype { enum { ALL_IRQS = 0 }; };
struct Inttypeh : Register<0x18, 32> { };
struct Inttypel : Register<0x1c, 32> { };
/**
* Normal interrupt priority registers
*/
struct Nipriority : Register_array<0x20, 32, 8, 32>
{
enum { ALL_LOWEST = 0 };
};
/**
* Interrupt source registers
*/
struct Intsrch : Register<0x48, 32> { };
struct Intsrcl : Register<0x4c, 32> { };
/**
* Normal interrupt pending registers
*/
struct Nipndh : Register<0x58, 32> { };
struct Nipndl : Register<0x5c, 32> { };
/**
* Normal interrupt vector and status register
*/
struct Nivecsr : Register<0x40, 32>
{
struct Nvector : Bitfield<16, 16> { };
};
public:
enum { NR_OF_IRQ = 64 };
/**
* Constructor, enables all interrupts
*/
Pic() : Mmio(Board::AVIC_MMIO_BASE)
{
mask();
write<Nimask>(Nimask::NONE_MASKED);
write<Intcntl>(Intcntl::init_value());
write<Inttypeh>(Inttype::ALL_IRQS);
write<Inttypel>(Inttype::ALL_IRQS);
for (unsigned i = 0; i < Nipriority::ITEMS; i++)
write<Nipriority>(Nipriority::ALL_LOWEST, i);
}
/**
* Initialize processor local interface of the controller
*/
void init_processor_local() { }
/**
* Receive a pending request number 'i'
*/
bool take_request(unsigned & i)
{
i = read<Nivecsr::Nvector>();
return valid(i) ? true : false;
}
/**
* Finish the last taken request
*/
void finish_request() {
/* requests disappear by source retraction or masking */ }
/**
* Validate request number 'i'
*/
bool valid(unsigned const i) const {
return i < NR_OF_IRQ; }
/**
* Mask all interrupts
*/
void mask()
{
write<Intenablel>(0);
write<Intenableh>(0);
}
/**
* Unmask interrupt
*
* \param interrupt_id kernel name of targeted interrupt
*/
void unmask(unsigned const interrupt_id, unsigned)
{
if (interrupt_id < NR_OF_IRQ) {
write<Intennum>(interrupt_id);
}
}
/**
* Mask interrupt 'i'
*/
void mask(unsigned const i) {
if (i < NR_OF_IRQ) write<Intdisnum>(i); }
/**
* Wether an interrupt is inter-processor interrupt of a processor
*
* \param interrupt_id kernel name of the interrupt
* \param processor_id kernel name of the processor
*/
bool is_ip_interrupt(unsigned const interrupt_id,
unsigned const processor_id)
{
return false;
}
/**
* Trigger the inter-processor interrupt of a processor
*
* \param processor_id kernel name of the processor
*/
void trigger_ip_interrupt(unsigned const processor_id) { }
};
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

11
repos/base-hw/src/core/imx53/board.h → repos/base-hw/src/core/include/spec/imx53/board.h
View File

@ -11,12 +11,10 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IMX53__BOARD_H_
#define _IMX53__BOARD_H_
#ifndef _BOARD_H_
#define _BOARD_H_
/**
* Genode includes
*/
/* Genode includes */
#include <platform/imx53/drivers/board_base.h>
#include <util/mmio.h>
@ -109,5 +107,4 @@ namespace Imx53
namespace Genode { class Board : public Imx53::Board { }; }
#endif /* _IMX53__BOARD_H_ */
#endif /* _BOARD_H_ */

236
repos/base-hw/src/core/include/spec/imx53/pic.h Normal file
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@ -0,0 +1,236 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
/* Genode includes */
#include <util/mmio.h>
/* core includes */
#include <board.h>
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : public Mmio
{
public:
enum { NR_OF_IRQ = 109 };
protected:
/**
* Interrupt control register
*/
struct Intctrl : Register<0, 32>
{
struct Enable : Bitfield<0,1> { };
struct Nsen : Bitfield<16,1> { };
struct Nsen_mask : Bitfield<31,1> { };
};
struct Priomask : Register<0xc, 32>
{
struct Mask : Bitfield<0,8> { };
};
struct Syncctrl : Register<0x10, 32>
{
struct Syncmode : Bitfield<0,2> { };
};
struct Dsmint : Register<0x14, 32>
{
struct Dsm : Bitfield<0,1> { };
};
/**
* Interrupt security registers
*/
struct Intsec : Register_array<0x80, 32, NR_OF_IRQ, 1>
{
struct Nonsecure : Bitfield<0, 1> { };
};
/**
* Interrupt set enable registers
*/
struct Enset : Register_array<0x100, 32, NR_OF_IRQ, 1, true>
{
struct Set_enable : Bitfield<0, 1> { };
};
/**
* Interrupt clear enable registers
*/
struct Enclear : Register_array<0x180, 32, NR_OF_IRQ, 1, true>
{
struct Clear_enable : Bitfield<0, 1> { };
};
/**
* Interrupt priority level registers
*/
struct Priority : Register_array<0x400, 32, NR_OF_IRQ, 8>
{
enum { MIN_PRIO = 0xff };
};
/**
* Pending registers
*/
struct Pndr : Register_array<0xd00, 32, NR_OF_IRQ, 1>
{
struct Pending : Bitfield<0, 1> { };
};
/**
* Highest interrupt pending registers
*/
struct Hipndr : Register_array<0xd80, 32, NR_OF_IRQ, 1, true>
{
struct Pending : Bitfield<0, 1> { };
};
/**
* Maximum supported interrupt priority
*/
unsigned _max_priority() { return 255; }
/**
* Initializes security extension if needed
*/
void _init_security_ext();
public:
/**
* Constructor
*/
Pic() : Mmio(Board::TZIC_MMIO_BASE)
{
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
write<Intsec::Nonsecure>(1, i);
write<Enclear::Clear_enable>(1, i);
}
write<Priomask::Mask>(0x1f);
write<Intctrl>(Intctrl::Enable::bits(1) |
Intctrl::Nsen::bits(1) |
Intctrl::Nsen_mask::bits(1));
_init_security_ext();
}
/**
* Mark interrupt unsecure
*
* \param i targeted interrupt
*/
void unsecure(unsigned const i);
/**
* Mark interrupt secure
*
* \param i targeted interrupt
*/
void secure(unsigned const i);
/**
* Initialize processor local interface of the controller
*/
void init_processor_local() { }
/**
* Receive a pending request number 'i'
*/
bool take_request(unsigned & i)
{
for (unsigned j = 0; j < NR_OF_IRQ; j++) {
if (read<Hipndr::Pending>(j)) {
i = j;
return true;
}
}
return false;
}
/**
* Finish the last taken request
*/
void finish_request() { }
/**
* Validate request number 'i'
*/
bool valid(unsigned const i) const {
return i < NR_OF_IRQ; }
/**
* Mask all interrupts
*/
void mask()
{
for (unsigned i=0; i < NR_OF_IRQ; i++)
write<Enclear::Clear_enable>(1, i);
}
/**
* Unmask interrupt
*
* \param interrupt_id kernel name of targeted interrupt
*/
void unmask(unsigned const interrupt_id, unsigned)
{
if (interrupt_id < NR_OF_IRQ) {
write<Enset::Set_enable>(1, interrupt_id);
}
}
/**
* Mask interrupt 'i'
*/
void mask(unsigned const i)
{
if (i < NR_OF_IRQ)
write<Enclear::Clear_enable>(1, i);
}
/**
* Wether an interrupt is inter-processor interrupt of a processor
*
* \param interrupt_id kernel name of the interrupt
* \param processor_id kernel name of the processor
*/
bool is_ip_interrupt(unsigned const interrupt_id,
unsigned const processor_id)
{
return false;
}
/**
* Trigger the inter-processor interrupt of a processor
*
* \param processor_id kernel name of the processor
*/
void trigger_ip_interrupt(unsigned const processor_id) { }
};
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

10
repos/base-hw/src/core/imx53/trustzone/csu.h → repos/base-hw/src/core/include/spec/imx53/trustzone/csu.h
View File

@ -11,15 +11,14 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _SRC__SERVER__VMM__INCLUDE__CSU_H_
#define _SRC__SERVER__VMM__INCLUDE__CSU_H_
#ifndef _CSU_H_
#define _CSU_H_
/* Genode includes */
#include <util/mmio.h>
#include <util/register.h>
namespace Genode
{
namespace Genode {
class Csu : Mmio
{
@ -219,7 +218,6 @@ namespace Genode
write<Master::Esdhc4>(Master::UNSECURE_UNLOCKED);
}
};
}
#endif /* _BASE_HW__SRC__SERVER__VMM__TSC_380_H_ */
#endif /* _CSU_H_ */

15
repos/base-hw/src/core/pbxa9/processor_driver.h → repos/base-hw/src/core/include/spec/odroid_xu/processor_driver.h
View File

@ -5,26 +5,24 @@
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PBXA9__PROCESSOR_DRIVER_H_
#define _PBXA9__PROCESSOR_DRIVER_H_
#ifndef _PROCESSOR_DRIVER_H_
#define _PROCESSOR_DRIVER_H_
/* core includes */
#include <processor_driver/cortex_a9.h>
#include <spec/cortex_a15/processor_driver_support.h>
namespace Genode
{
using Cortex_a9::Processor_lazy_state;
/**
* Processor driver for core
*/
class Processor_driver : public Cortex_a9::Processor_driver
class Processor_driver : public Cortex_a15
{
public:
@ -40,5 +38,4 @@ namespace Genode
};
}
#endif /* _PBXA9__PROCESSOR_DRIVER_H_ */
#endif /* _PROCESSOR_DRIVER_H_ */

7
repos/base-hw/src/core/panda/board.h → repos/base-hw/src/core/include/spec/panda/board.h
View File

@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PANDA__BOARD_H_
#define _PANDA__BOARD_H_
#ifndef _BOARD_H_
#define _BOARD_H_
/* core includes */
#include <util/mmio.h>
@ -116,5 +116,4 @@ namespace Genode
};
}
#endif /* _PANDA__BOARD_H_ */
#endif /* _BOARD_H_ */

20
repos/base-hw/include/pl011/drivers/serial_log.h → repos/base-hw/src/core/include/spec/pl011/serial.h
View File

@ -1,5 +1,5 @@
/*
* \brief Serial output driver specific for the ARM PL011
* \brief Serial output driver for core
* \author Martin Stein
* \date 2012-04-23
*/
@ -11,19 +11,21 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PL011__DRIVERS__SERIAL_LOG_H_
#define _INCLUDE__PL011__DRIVERS__SERIAL_LOG_H_
#ifndef _SERIAL_H_
#define _SERIAL_H_
/* core includes */
#include <board.h>
/* Genode includes */
#include <board.h>
#include <drivers/uart/pl011_base.h>
namespace Genode
{
/**
* Serial output driver specific for the ARM PL011
* Serial output driver for core
*/
class Serial_log : public Pl011_base
class Serial : public Pl011_base
{
public:
@ -32,12 +34,12 @@ namespace Genode
*
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Serial(unsigned const baud_rate)
:
Pl011_base(Board::PL011_0_MMIO_BASE,
Board::PL011_0_CLOCK, baud_rate)
{ }
};
}
#endif /* _INCLUDE__PL011__DRIVERS__SERIAL_LOG_H_ */
#endif /* _SERIAL_H_ */

149
repos/base-hw/src/core/include/spec/rpi/pic.h Normal file
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@ -0,0 +1,149 @@
/*
* \brief Programmable interrupt controller for core
* \author Norman Feske
* \date 2013-04-05
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
/* Genode includes */
#include <util/mmio.h>
/* core includes */
#include <board.h>
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : Mmio
{
public:
enum { NR_OF_IRQ = 64 };
private:
struct Irq_pending_basic : Register<0x0, 32>
{
struct Timer : Bitfield<0, 1> { };
struct Gpu : Bitfield<8, 2> { };
};
struct Irq_pending_gpu_1 : Register<0x04, 32> { };
struct Irq_pending_gpu_2 : Register<0x08, 32> { };
struct Irq_enable_gpu_1 : Register<0x10, 32> { };
struct Irq_enable_gpu_2 : Register<0x14, 32> { };
struct Irq_enable_basic : Register<0x18, 32> { };
struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
struct Irq_disable_gpu_2 : Register<0x20, 32> { };
struct Irq_disable_basic : Register<0x24, 32> { };
/**
* Return true if specified interrupt is pending
*/
static bool _is_pending(unsigned i, uint32_t p1, uint32_t p2)
{
return i < 32 ? (p1 & (1 << i)) : (p2 & (1 << (i - 32)));
}
public:
/**
* Constructor
*/
Pic() : Mmio(Board::IRQ_CONTROLLER_BASE) { mask(); }
void init_processor_local() { }
bool take_request(unsigned &irq)
{
/* read basic IRQ status mask */
uint32_t const p = read<Irq_pending_basic>();
/* read GPU IRQ status mask */
uint32_t const p1 = read<Irq_pending_gpu_1>(),
p2 = read<Irq_pending_gpu_2>();
if (Irq_pending_basic::Timer::get(p)) {
irq = Irq_pending_basic::Timer::SHIFT;
return true;
}
/* search for lowest set bit in pending masks */
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
if (!_is_pending(i, p1, p2))
continue;
irq = Board_base::GPU_IRQ_BASE + i;
return true;
}
return false;
}
void finish_request() { }
void mask()
{
write<Irq_disable_basic>(~0);
write<Irq_disable_gpu_1>(~0);
write<Irq_disable_gpu_2>(~0);
}
void unmask(unsigned const i, unsigned)
{
if (i < 8)
write<Irq_enable_basic>(1 << i);
else if (i < 32 + 8)
write<Irq_enable_gpu_1>(1 << (i - 8));
else
write<Irq_enable_gpu_2>(1 << (i - 8 - 32));
}
void mask(unsigned const i)
{
if (i < 8)
write<Irq_disable_basic>(1 << i);
else if (i < 32 + 8)
write<Irq_disable_gpu_1>(1 << (i - 8));
else
write<Irq_disable_gpu_2>(1 << (i - 8 - 32));
}
/**
* Wether an interrupt is inter-processor interrupt of a processor
*
* \param interrupt_id kernel name of the interrupt
* \param processor_id kernel name of the processor
*/
bool is_ip_interrupt(unsigned const interrupt_id,
unsigned const processor_id)
{
return false;
}
/**
* Trigger the inter-processor interrupt of a processor
*
* \param processor_id kernel name of the processor
*/
void trigger_ip_interrupt(unsigned const processor_id) { }
};
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

78
repos/base-hw/src/core/include/spec/rpi/timer.h Normal file
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@ -0,0 +1,78 @@
/*
* \brief Timer driver for core
* \author Norman Feske
* \date 2013-04-05
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _TIMER_H_
#define _TIMER_H_
/* Genode includes */
#include <util/mmio.h>
/* core includes */
#include <board.h>
namespace Genode
{
/**
* Timer driver for core
*/
class Timer;
}
class Genode::Timer : public Mmio
{
private:
/*
* The timer channel 0 apparently does not work on the Raspberry Pi.
* So we use channel 1.
*/
struct Cs : Register<0x0, 32>
{
struct Status : Bitfield<1, 1> { };
};
struct Clo : Register<0x4, 32> { };
struct Cmp : Register<0x10, 32> { };
public:
Timer() : Mmio(Board::SYSTEM_TIMER_MMIO_BASE) { }
static unsigned interrupt_id(unsigned)
{
return Board::SYSTEM_TIMER_IRQ;
}
inline void start_one_shot(uint32_t const tics, unsigned)
{
write<Clo>(0);
write<Cmp>(read<Clo>() + tics);
write<Cs::Status>(1);
}
static uint32_t ms_to_tics(unsigned const ms)
{
return (Board::SYSTEM_TIMER_CLOCK / 1000) * ms;
}
void clear_interrupt(unsigned)
{
write<Cs::Status>(1);
read<Cs>();
}
};
namespace Kernel { class Timer : public Genode::Timer { }; }
#endif /* _TIMER_H_ */

20
repos/base-hw/include/tl16c750/drivers/serial_log.h → repos/base-hw/src/core/include/spec/tl16c750/serial.h
View File

@ -1,5 +1,5 @@
/*
* \brief Serial output driver specific for the Texas Instruments TL16C750
* \brief Serial output driver for core
* \author Martin Stein
* \date 2012-04-23
*/
@ -11,19 +11,21 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__TL16C750__DRIVERS__SERIAL_LOG_H_
#define _INCLUDE__TL16C750__DRIVERS__SERIAL_LOG_H_
#ifndef _SERIAL_H_
#define _SERIAL_H_
/* core includes */
#include <board.h>
/* Genode includes */
#include <board.h>
#include <drivers/uart/tl16c750_base.h>
namespace Genode
{
/**
* Serial output driver specific for the Texas Instruments TL16C750
* Serial output driver for core
*/
class Serial_log : public Tl16c750_base
class Serial : public Tl16c750_base
{
public:
@ -32,12 +34,12 @@ namespace Genode
*
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Serial(unsigned const baud_rate)
:
Tl16c750_base(Board::TL16C750_3_MMIO_BASE,
Board::TL16C750_CLOCK, baud_rate)
{ }
};
}
#endif /* _INCLUDE__TL16C750__DRIVERS__SERIAL_LOG_H_ */
#endif /* _SERIAL_H_ */

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