150 lines
3.2 KiB
C++
150 lines
3.2 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Norman Feske
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* \date 2013-04-05
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _PIC_H_
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#define _PIC_H_
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/* Genode includes */
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#include <util/mmio.h>
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/* core includes */
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#include <board.h>
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namespace Genode
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{
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/**
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* Programmable interrupt controller for core
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*/
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class Pic;
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}
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class Genode::Pic : Mmio
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{
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public:
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enum { NR_OF_IRQ = 64 };
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private:
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struct Irq_pending_basic : Register<0x0, 32>
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{
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struct Timer : Bitfield<0, 1> { };
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struct Gpu : Bitfield<8, 2> { };
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};
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struct Irq_pending_gpu_1 : Register<0x04, 32> { };
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struct Irq_pending_gpu_2 : Register<0x08, 32> { };
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struct Irq_enable_gpu_1 : Register<0x10, 32> { };
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struct Irq_enable_gpu_2 : Register<0x14, 32> { };
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struct Irq_enable_basic : Register<0x18, 32> { };
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struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
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struct Irq_disable_gpu_2 : Register<0x20, 32> { };
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struct Irq_disable_basic : Register<0x24, 32> { };
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/**
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* Return true if specified interrupt is pending
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*/
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static bool _is_pending(unsigned i, uint32_t p1, uint32_t p2)
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{
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return i < 32 ? (p1 & (1 << i)) : (p2 & (1 << (i - 32)));
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}
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public:
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/**
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* Constructor
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*/
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Pic() : Mmio(Board::IRQ_CONTROLLER_BASE) { mask(); }
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void init_processor_local() { }
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bool take_request(unsigned &irq)
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{
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/* read basic IRQ status mask */
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uint32_t const p = read<Irq_pending_basic>();
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/* read GPU IRQ status mask */
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uint32_t const p1 = read<Irq_pending_gpu_1>(),
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p2 = read<Irq_pending_gpu_2>();
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if (Irq_pending_basic::Timer::get(p)) {
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irq = Irq_pending_basic::Timer::SHIFT;
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return true;
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}
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/* search for lowest set bit in pending masks */
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for (unsigned i = 0; i < NR_OF_IRQ; i++) {
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if (!_is_pending(i, p1, p2))
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continue;
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irq = Board_base::GPU_IRQ_BASE + i;
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return true;
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}
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return false;
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}
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void finish_request() { }
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void mask()
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{
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write<Irq_disable_basic>(~0);
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write<Irq_disable_gpu_1>(~0);
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write<Irq_disable_gpu_2>(~0);
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}
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void unmask(unsigned const i, unsigned)
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{
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if (i < 8)
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write<Irq_enable_basic>(1 << i);
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else if (i < 32 + 8)
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write<Irq_enable_gpu_1>(1 << (i - 8));
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else
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write<Irq_enable_gpu_2>(1 << (i - 8 - 32));
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}
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void mask(unsigned const i)
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{
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if (i < 8)
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write<Irq_disable_basic>(1 << i);
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else if (i < 32 + 8)
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write<Irq_disable_gpu_1>(1 << (i - 8));
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else
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write<Irq_disable_gpu_2>(1 << (i - 8 - 32));
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}
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/**
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* Wether an interrupt is inter-processor interrupt of a processor
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*
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* \param interrupt_id kernel name of the interrupt
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* \param processor_id kernel name of the processor
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*/
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bool is_ip_interrupt(unsigned const interrupt_id,
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unsigned const processor_id)
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{
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return false;
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}
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/**
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* Trigger the inter-processor interrupt of a processor
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*
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* \param processor_id kernel name of the processor
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*/
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void trigger_ip_interrupt(unsigned const processor_id) { }
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};
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namespace Kernel { class Pic : public Genode::Pic { }; }
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#endif /* _PIC_H_ */
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