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hw vea9x4: remove trustzone support 

When building Genode for VEA9X4 as micro-hypervisor protected by the ARM
TrustZone hardware we ran into limitations regarding our basic daily
testing routines. The most significant is that, when speaking about RAM
partitioning, the only available options are to configure the whole SRAM
to be secure and the whole DDR-RAM to be non-secure or vice versa. The
SRAM however provides only 32 MB which isn't enough for both a
representative non-secure guest OS or a secure Genode that is still
capable of passing our basic tests. This initiated our decision to
remove the VEA9X4 TrustZone-support.

Fixes #1351
This commit is contained in:
Martin Stein 2015-01-08 13:28:42 +01:00
parent 91daf433c5
commit 9a4a0448be
19 changed files with 9 additions and 1059 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
repos/base-hw/include/platform/vea9x4/drivers/trustzone.h
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@ -1,31 +0,0 @@
/*
* \brief TrustZone specific definitions for the Versatile Express board
* \author Stefan Kalkowski
* \date 2013-11-15
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__VEA9X4__DRIVERS__TRUSTZONE_H_
#define _INCLUDE__PLATFORM__VEA9X4__DRIVERS__TRUSTZONE_H_
/* Genode includes */
#include <drivers/board_base.h>
namespace Trustzone
{
enum {
SECURE_RAM_BASE = Genode::Board_base::RAM_2_BASE,
SECURE_RAM_SIZE = Genode::Board_base::RAM_2_SIZE,
NONSECURE_RAM_BASE = 0x80000000,
NONSECURE_RAM_SIZE = 0x20000000,
};
}
#endif /* _INCLUDE__PLATFORM__VEA9X4__DRIVERS__TRUSTZONE_H_ */

19
repos/base-hw/lib/mk/platform_vea9x4/core-trustzone_off.mk
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@ -1,19 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += spec/vea9x4/platform_support.cc
SRC_CC += spec/cortex_a9/pic.cc
SRC_CC += spec/arm_gic/pic.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/core-trustzone.inc

20
repos/base-hw/lib/mk/platform_vea9x4/core-trustzone_on.mk
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@ -1,20 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/vea9x4/trustzone
INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
# add C++ sources
SRC_CC += vm_session_component.cc
SRC_CC += spec/vea9x4/trustzone/platform_support.cc
SRC_CC += spec/vea9x4/trustzone/pic.cc
SRC_CC += spec/vea9x4/trustzone/platform_services.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/core-trustzone.inc

7
repos/base-hw/lib/mk/platform_vea9x4/core.mk
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@ -5,9 +5,6 @@
# \date 2012-10-04
#
# add library dependencies
LIBS += core-trustzone
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
@ -15,6 +12,10 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
# add C++ sources
SRC_CC += cpu.cc
SRC_CC += platform_services.cc
SRC_CC += spec/vea9x4/platform_support.cc
SRC_CC += spec/cortex_a9/pic.cc
SRC_CC += spec/arm_gic/pic.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v7/core.inc

14
repos/base-hw/mk/spec-hw_vea9x4_tz.mk
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@ -1,14 +0,0 @@
#
# \brief Offer build configurations that are specific to base-hw and VEA9X4
# \author Martin Stein
# \date 2011-12-20
#
# denote wich specs are also fullfilled by this spec
SPECS += hw_vea9x4 trustzone
# adjust link address of a trustzone text segment
LD_TEXT_ADDR = 0x48000000
# include implied specs
include $(call select_from_repositories,mk/spec-hw_vea9x4.mk)

77
repos/base-hw/src/core/include/spec/vea9x4/trustzone/pic.h
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@ -1,77 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Martin Stein
* \author Stefan Kalkowski
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
/* core includes */
#include <spec/arm_gic/pic_support.h>
#include <cpu.h>
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : public Arm_gic
{
public:
/**
* Constructor
*/
Pic() : Arm_gic(Cpu::PL390_DISTRIBUTOR_MMIO_BASE,
Cpu::PL390_CPU_MMIO_BASE)
{
/* configure every shared peripheral interrupt */
for (unsigned i = min_spi; i <= _max_interrupt; i++) {
_distr.write<Distr::Icfgr::Edge_triggered>(0, i);
_distr.write<Distr::Ipriorityr::Priority>(0, i);
_distr.write<Distr::Itargetsr::Cpu_targets>(0xff, i);
}
/* disable the priority filter */
_cpui.write<Cpui::Pmr::Priority>(0xff);
/* signal secure IRQ via FIQ interface */
Cpui::Ctlr::access_t ctlr = 0;
Cpui::Ctlr::Enable_grp0::set(ctlr, 1);
Cpui::Ctlr::Enable_grp1::set(ctlr, 1);
Cpui::Ctlr::Fiq_en::set(ctlr, 1);
_cpui.write<Cpui::Ctlr>(ctlr);
/* use whole band of prios */
_cpui.write<Cpui::Bpr::Binary_point>(~0);
/* enable device */
_distr.write<Distr::Ctlr>(Distr::Ctlr::Enable::bits(1));
}
/**
* Mark interrupt 'i' unsecure
*/
void unsecure(unsigned const i) {
_distr.write<Distr::Igroupr::Group_status>(1, i); }
};
bool Genode::Arm_gic::_use_security_ext() { return 1; }
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

48
repos/base-hw/src/core/spec/vea9x4/trustzone/pic.cc
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@ -1,48 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2011-10-26
*/
/*
* Copyright (C) 2011-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* core includes */
#include <pic.h>
using namespace Genode;
void Arm_gic::_init()
{
/* configure every shared peripheral interrupt */
for (unsigned i = min_spi; i <= _max_irq; i++) {
_distr.write<Distr::Icfgr::Edge_triggered>(0, i);
_distr.write<Distr::Ipriorityr::Priority>(0, i);
_distr.write<Distr::Itargetsr::Cpu_targets>(~0, i);
}
/* disable the priority filter */
_cpui.write<Cpui::Pmr::Priority>(~0);
/* signal secure IRQ via FIQ interface */
typedef Cpui::Ctlr Ctlr;
Ctlr::access_t v = 0;
Ctlr::Enable_grp0::set(v, 1);
Ctlr::Enable_grp1::set(v, 1);
Ctlr::Fiq_en::set(v, 1);
_cpui.write<Ctlr>(v);
/* use whole band of prios */
_cpui.write<Cpui::Bpr::Binary_point>(~0);
/* enable device */
_distr.write<Distr::Ctlr>(Distr::Ctlr::Enable::bits(1));
}
void Pic::unsecure(unsigned const i) {
_distr.write<Distr::Igroupr::Group_status>(1, i); }

36
repos/base-hw/src/core/spec/vea9x4/trustzone/platform_services.cc
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@ -1,36 +0,0 @@
/*
* \brief Platform specific services for base-hw and VEA9X4 (TrustZone)
* \author Stefan Kalkowski
* \date 2012-10-26
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* Genode includes */
#include <base/service.h>
#include <drivers/trustzone.h>
/* Core includes */
#include <platform.h>
#include <platform_services.h>
#include <vm_root.h>
/*
* Add TrustZone specific vm service
*/
void Genode::platform_add_local_services(Genode::Rpc_entrypoint *ep,
Genode::Sliced_heap *sh,
Genode::Service_registry *ls)
{
using namespace Genode;
static Vm_root vm_root(ep, sh);
static Local_service vm_ls(Vm_session::service_name(), &vm_root);
ls->insert(&vm_ls);
}

94
repos/base-hw/src/core/spec/vea9x4/trustzone/platform_support.cc
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@ -1,94 +0,0 @@
/*
* \brief Platform implementations specific for base-hw and VEA9X4
* \author Martin Stein
* \date 2012-04-27
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#include <drivers/trustzone.h>
/* core includes */
#include <board.h>
#include <cpu.h>
#include <platform.h>
#include <pic.h>
#include <trustzone.h>
#include <pic.h>
using namespace Genode;
/* monitor exception vector address */
extern int _mon_kernel_entry;
void Kernel::init_trustzone(Pic * pic)
{
/* check for compatibility */
if (NR_OF_CPUS > 1) {
PERR("trustzone not supported with multiprocessing");
return;
}
/* set exception vector entry */
Cpu::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry);
/* enable coprocessor access for TZ VMs */
Cpu::allow_coprocessor_nonsecure();
/* set unsecure IRQs */
pic->unsecure(35); //Timer 2/3
pic->unsecure(36); //RTC
pic->unsecure(37); //UART0
pic->unsecure(41); //MCI0
pic->unsecure(42); //MCI1
pic->unsecure(43); //AACI
pic->unsecure(44); //KMI0
pic->unsecure(45); //KMI1
pic->unsecure(47); //ETHERNET
pic->unsecure(48); //USB
}
Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Trustzone::SECURE_RAM_BASE, Trustzone::SECURE_RAM_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
{ Trustzone::NONSECURE_RAM_BASE, Trustzone::NONSECURE_RAM_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Native_region * Platform::_core_only_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
/* Core timer and PIC */
{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
/* Core UART */
{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Cpu::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); }

8
repos/base/include/platform/vea9x4/drivers/board_base.h
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@ -65,14 +65,6 @@ namespace Genode
PL180_0_IRQ = 9,
PL180_1_IRQ = 10,
/* TrustZone Address Space Controller */
TZASC_MMIO_BASE = 0x100ec000,
TZASC_MMIO_SIZE = 0x1000,
/* TrustZone Protection Controller */
TZPC_MMIO_BASE = 0x100e6000,
TZPC_MMIO_SIZE = 0x1000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,

18
repos/os/src/server/tz_vmm/README
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@ -1,17 +1,9 @@
This is a small example virtual machine monitor, that uses the base-hw kernel
as TrustZone micro-hypervisor on the ARM Versatile Express CT A9x4 platform.
The VMM configures TrustZone Protection Controller and Address Space Controller
in a way, that allows a guest to access nearly all devices, and the DDR-RAM.
Only few resources needed by the kernel (timer, SRAM) aren't accessable by the
virtual-machine.
as secure-world micro-hypervisor on ARM TrustZone platforms. The VMM
configures TrustZone hardware in a way, that allows a guest to access nearly
all devices, and the DDR-RAM. Only few resources needed by the kernel (timer,
SRAM) aren't accessable by the virtual-machine.
Moreover, the VMM prepares the guest memory with a Linux image, and ramdisk,
and boots it. For the Linux guest to work properly a small patch, and tweaked
configuration is needed. Please checkout the following branch to test it:
https://github.com/skalk/linux/tree/vexpress-tz
To build linux do:
! make ARCH=arm CROSS_COMPILE=<path_to_cross_compiler> vexpress_tz_defconfig
! make ARCH=arm CROSS_COMPILE=<path_to_cross_compiler>
configuration is needed.

126
repos/os/src/server/tz_vmm/vea9x4/bp_147.h
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@ -1,126 +0,0 @@
/*
* \brief Driver for the Trustzone Protection Controller BP147
* \author Stefan Kalkowski
* \date 2012-07-04
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _BASE_HW__SRC__SERVER__VMM__BP_147_H_
#define _BASE_HW__SRC__SERVER__VMM__BP_147_H_
/* Genode includes */
#include <util/mmio.h>
class Bp_147 : Genode::Mmio
{
private:
/**
* Secure RAM Region Size Register
*/
struct Tzpcr0size : public Register<0x00, 32>
{
struct R0size : Bitfield<0,10> { };
};
/**
* Decode Protection 0 Registers
*/
template <Genode::off_t OFF>
struct Tzpcdecprot0 : public Register<OFF, 32>
{
struct Pl341_apb : Register<OFF, 32>::template Bitfield<0,1> {};
struct Pl354_apb : Register<OFF, 32>::template Bitfield<1,1> {};
struct Scc : Register<OFF, 32>::template Bitfield<2,1> {};
struct Dual_timer : Register<OFF, 32>::template Bitfield<4,1> {};
struct Watchdog : Register<OFF, 32>::template Bitfield<5,1> {};
struct Tzpc : Register<OFF, 32>::template Bitfield<6,1> {};
struct Pl351_apb : Register<OFF, 32>::template Bitfield<7,1> {};
struct Fast_pl301_apb : Register<OFF, 32>::template Bitfield<9,1> {};
struct Slow_pl301_apb : Register<OFF, 32>::template Bitfield<10,1> {};
struct Dmc_tzasc : Register<OFF, 32>::template Bitfield<12,1> {};
struct Nmc_tzasc : Register<OFF, 32>::template Bitfield<12,1> {};
struct Smc_tzasc : Register<OFF, 32>::template Bitfield<13,1> {};
struct Debug_apb_phs : Register<OFF, 32>::template Bitfield<14,1> {};
};
/**
* Decode Protection 1 Registers
*/
template <Genode::off_t OFF>
struct Tzpcdecprot1 : public Register<OFF, 32>
{
struct External_axi_slave_port
: Register<OFF, 32>::template Bitfield<0,1> {};
/* SMC access */
struct Pl354_axi
: Register<OFF, 32>::template Bitfield<1,1> {};
struct Pl351_axi
: Register<OFF, 32>::template Bitfield<2,1> {};
struct Entire_apb
: Register<OFF, 32>::template Bitfield<3,1> {};
struct Pl111_configuration_port
: Register<OFF, 32>::template Bitfield<4,1> {};
struct Axi_ram
: Register<OFF, 32>::template Bitfield<5,1> {};
/* DDR RAM access */
struct Pl341_axi
: Register<OFF, 32>::template Bitfield<6,1> {};
/* ACP access */
struct Cortexa9_coherency_port
: Register<OFF, 32>::template Bitfield<8,1> {};
struct Entire_slow_axi_system
: Register<OFF, 32>::template Bitfield<9,1> {};
};
/**
* Decode Protection 2 Registers
*/
template <Genode::off_t OFF>
struct Tzpcdecprot2 : public Register<OFF, 32>
{
struct External_master_tz : Register<OFF, 32>::template Bitfield<0,1> {};
struct Dap_tz_override : Register<OFF, 32>::template Bitfield<1,1> {};
struct Pl111_master_tz : Register<OFF, 32>::template Bitfield<2,1> {};
struct Dmc_tzasc_lockdown : Register<OFF, 32>::template Bitfield<3,1> {};
struct Nmc_tzasc_lockdown : Register<OFF, 32>::template Bitfield<4,1> {};
struct Smc_tzasc_lockdown : Register<OFF, 32>::template Bitfield<5,1> {};
};
struct Tzpcdecprot0stat : Tzpcdecprot0<0x800> {};
struct Tzpcdecprot0set : Tzpcdecprot0<0x804> {};
struct Tzpcdecprot0clr : Tzpcdecprot0<0x808> {};
struct Tzpcdecprot1stat : Tzpcdecprot1<0x80c> {};
struct Tzpcdecprot1set : Tzpcdecprot1<0x810> {};
struct Tzpcdecprot1clr : Tzpcdecprot1<0x814> {};
struct Tzpcdecprot2stat : Tzpcdecprot2<0x818> {};
struct Tzpcdecprot2set : Tzpcdecprot2<0x81c> {};
struct Tzpcdecprot2clr : Tzpcdecprot2<0x820> {};
public:
Bp_147(Genode::addr_t const base) : Genode::Mmio(base)
{
/**
* Configure TZPC to allow non-secure AXI signals to
* Static Memory Controller (SMC),
* Dynamic Memory Controller (DMC),
* Accelerator Coherency Port (ACP), and
* PL111 configuration registers
*/
write<Tzpcdecprot1set>(
Tzpcdecprot1set::Pl341_axi::bits(1) |
Tzpcdecprot1set::Pl354_axi::bits(1) |
Tzpcdecprot1set::Cortexa9_coherency_port::bits(1) |
Tzpcdecprot1set::Pl111_configuration_port::bits(1));
}
};
#endif /* _BASE_HW__SRC__SERVER__VMM__BP_147_H_ */

211
repos/os/src/server/tz_vmm/vea9x4/main.cc
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@ -1,211 +0,0 @@
/*
* \brief Virtual Machine Monitor
* \author Stefan Kalkowski
* \date 2012-06-25
*/
/*
* Copyright (C) 2008-2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* Genode includes */
#include <base/elf.h>
#include <base/env.h>
#include <base/sleep.h>
#include <base/thread.h>
#include <cpu/cpu_state.h>
#include <io_mem_session/connection.h>
#include <rom_session/connection.h>
#include <vm_session/connection.h>
#include <dataspace/client.h>
#include <drivers/trustzone.h>
/* local includes */
#include <tsc_380.h>
#include <bp_147.h>
#include <sys_reg.h>
#include <sp810.h>
#include <vm.h>
using namespace Genode;
namespace Vmm {
class Vmm;
}
class Vmm::Vmm : public Thread<8192>
{
private:
enum Hypervisor_calls {
SP810_ENABLE = 1,
CPU_ID,
SYS_COUNTER,
MISC_FLAGS,
SYS_CTRL,
MCI_STATUS
};
Io_mem_connection _tsc_io_mem;
Io_mem_connection _tpc_io_mem;
Io_mem_connection _sys_io_mem;
Io_mem_connection _sp810_io_mem;
Tsc_380 _tsc;
Bp_147 _tpc;
Sys_reg _sys;
Sp810 _sp810;
Vm *_vm;
void _sys_ctrl()
{
enum {
OSC1 = 0xc0110001,
DVI_SRC = 0xc0710000,
DVI_MODE = 0xc0b00000
};
uint32_t ctrl = _vm->state()->r2;
uint32_t data = _vm->state()->r0;
switch(ctrl) {
case OSC1:
_sys.osc1(data);
break;
case DVI_SRC:
_sys.dvi_source(data);
break;
case DVI_MODE:
_sys.dvi_mode(data);
break;
default:
PWRN("Access violation to sys configuration ctrl=%ux", ctrl);
_vm->dump();
}
}
void _handle_hypervisor_call()
{
switch (_vm->state()->r1) {
case SP810_ENABLE:
_sp810.enable_timer0();
_sp810.enable_timer1();
break;
case CPU_ID:
_vm->state()->r0 = 0x0c000191; // Coretile A9 ID
break;
case SYS_COUNTER:
_vm->state()->r0 = _sys.counter();
break;
case MISC_FLAGS:
_vm->state()->r0 = _sys.misc_flags();
break;
case SYS_CTRL:
_sys_ctrl();
break;
case MCI_STATUS:
_vm->state()->r0 = _sys.mci_status();
break;
default:
PERR("Unknown hypervisor call!");
_vm->dump();
}
}
bool _handle_data_abort()
{
PWRN("Vm tried to access %p which isn't allowed",
_tsc.last_failed_access());
_vm->dump();
return false;
}
bool _handle_vm()
{
switch (_vm->state()->cpu_exception) {
case Cpu_state::DATA_ABORT:
if (!_handle_data_abort()) {
PERR("Could not handle data-abort will exit!");
return false;
}
break;
case Cpu_state::SUPERVISOR_CALL:
_handle_hypervisor_call();
break;
default:
PERR("Curious exception occured");
_vm->dump();
return false;
}
return true;
}
protected:
void entry()
{
Signal_receiver sig_rcv;
Signal_context sig_cxt;
Signal_context_capability sig_cap(sig_rcv.manage(&sig_cxt));
_vm->sig_handler(sig_cap);
_vm->start();
while (true) {
_vm->run();
Signal s = sig_rcv.wait_for_signal();
if (s.context() != &sig_cxt) {
PWRN("Invalid context");
continue;
}
if (!_handle_vm())
return;
}
};
public:
Vmm(addr_t tsc_base, addr_t tpc_base,
addr_t sys_base, addr_t sp810_base,
Vm *vm)
: Thread<8192>("vmm"),
_tsc_io_mem(tsc_base, 0x1000),
_tpc_io_mem(tpc_base, 0x1000),
_sys_io_mem(sys_base, 0x1000),
_sp810_io_mem(sp810_base, 0x1000),
_tsc((addr_t)env()->rm_session()->attach(_tsc_io_mem.dataspace())),
_tpc((addr_t)env()->rm_session()->attach(_tpc_io_mem.dataspace())),
_sys((addr_t)env()->rm_session()->attach(_sys_io_mem.dataspace())),
_sp810((addr_t)env()->rm_session()->attach(_sp810_io_mem.dataspace())),
_vm(vm) { }
};
int main()
{
enum {
SYS_VEA9X4_BASE = 0x10000000,
SP810_VEA9X4_BASE = 0x10001000,
TPC_VEA9X4_BASE = 0x100e6000,
TSC_VEA9X4_BASE = 0x100ec000,
MAIN_MEM_START = Trustzone::NONSECURE_RAM_BASE,
MAIN_MEM_SIZE = Trustzone::NONSECURE_RAM_SIZE,
KERNEL_OFFSET = 0x8000,
MACH_TYPE = 2272,
};
static const char* cmdline = "console=ttyAMA0,115200n8 root=/dev/ram0 lpj=1554432";
static Vm vm("linux", "initrd.gz", cmdline, MAIN_MEM_START, MAIN_MEM_SIZE,
KERNEL_OFFSET, MACH_TYPE);
static Vmm::Vmm vmm(TSC_VEA9X4_BASE, TPC_VEA9X4_BASE,
SYS_VEA9X4_BASE, SP810_VEA9X4_BASE, &vm);
PINF("Start virtual machine");
vmm.start();
sleep_forever();
return 0;
}

41
repos/os/src/server/tz_vmm/vea9x4/sp810.h
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@ -1,41 +0,0 @@
/*
* \brief Driver for the SP810 system controller
* \author Stefan Kalkowski
* \date 2012-09-21
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _BASE_HW__SRC__SERVER__VMM__810_H_
#define _BASE_HW__SRC__SERVER__VMM__810_H_
/* Genode includes */
#include <util/mmio.h>
class Sp810 : Genode::Mmio
{
private:
struct Ctrl : public Register<0, 32>
{
struct Timer0_enable : Bitfield<15,1> {};
struct Timer1_enable : Bitfield<17,1> {};
};
public:
Sp810(Genode::addr_t const base) : Genode::Mmio(base) {}
bool timer0() { return read<Ctrl::Timer0_enable>(); }
bool timer1() { return read<Ctrl::Timer0_enable>(); }
void enable_timer0() { write<Ctrl::Timer0_enable>(1); }
void enable_timer1() { write<Ctrl::Timer0_enable>(1); }
};
#endif /* _BASE_HW__SRC__SERVER__VMM__SP810_H_ */

100
repos/os/src/server/tz_vmm/vea9x4/sys_reg.h
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@ -1,100 +0,0 @@
/*
* \brief Driver for the Motherboard Express system registers
* \author Stefan Kalkowski
* \date 2012-09-21
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _BASE_HW__SRC__SERVER__VMM__SYS_REG_H_
#define _BASE_HW__SRC__SERVER__VMM__SYS_REG_H_
/* Genode includes */
#include <util/mmio.h>
class Sys_reg : Genode::Mmio
{
private:
struct Sys_mci : public Register<0x48, 32> {};
struct Sys_24mhz : public Register<0x5c, 32> {};
struct Sys_misc : public Register<0x60, 32> {};
struct Sys_cfg_data : public Register<0xa0, 32, true> {};
struct Sys_cfg_ctrl : public Register<0xa4, 32, true>
{
struct Device : Bitfield<0,12> { };
struct Position : Bitfield<12,4> { };
struct Site : Bitfield<16,2> { };
struct Function : Bitfield<20,6> { };
struct Write : Bitfield<30,1> { };
struct Start : Bitfield<31,1> { };
};
struct Sys_cfg_stat : public Register<0xa8, 32>
{
struct Complete : Bitfield<0,1> { };
struct Error : Bitfield<1,1> { };
};
public:
Sys_reg(Genode::addr_t const base) : Genode::Mmio(base) {}
Genode::uint32_t counter() { return read<Sys_24mhz>(); }
Genode::uint32_t misc_flags() { return read<Sys_misc>(); }
void osc1(Genode::uint32_t mhz)
{
write<Sys_cfg_stat::Complete>(0);
write<Sys_cfg_data>(mhz);
write<Sys_cfg_ctrl>(Sys_cfg_ctrl::Device::bits(1) |
Sys_cfg_ctrl::Site::bits(1) |
Sys_cfg_ctrl::Function::bits(1) |
Sys_cfg_ctrl::Write::bits(1) |
Sys_cfg_ctrl::Start::bits(1));
while (!read<Sys_cfg_stat::Complete>()) ;
}
void dvi_source(Genode::uint32_t site)
{
if (site > 2) {
PERR("Invalid site value %u ignored", site);
return;
}
write<Sys_cfg_stat::Complete>(0);
write<Sys_cfg_data>(site);
write<Sys_cfg_ctrl>(Sys_cfg_ctrl::Site::bits(1) |
Sys_cfg_ctrl::Function::bits(0x7) |
Sys_cfg_ctrl::Write::bits(1) |
Sys_cfg_ctrl::Start::bits(1));
while (!read<Sys_cfg_stat::Complete>()) ;
}
void dvi_mode(Genode::uint32_t mode)
{
if (mode > 4) {
PERR("Invalid dvi mode %u ignored", mode);
return;
}
write<Sys_cfg_stat::Complete>(0);
write<Sys_cfg_data>(mode);
write<Sys_cfg_ctrl>(Sys_cfg_ctrl::Function::bits(0xb) |
Sys_cfg_ctrl::Write::bits(1) |
Sys_cfg_ctrl::Start::bits(1));
while (!read<Sys_cfg_stat::Complete>()) ;
}
Genode::uint32_t mci_status() { return read<Sys_mci>(); }
};
#endif /* _BASE_HW__SRC__SERVER__VMM__SYS_REG_H_ */

5
repos/os/src/server/tz_vmm/vea9x4/target.mk
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@ -1,5 +0,0 @@
TARGET = tz_vmm
REQUIRES = trustzone platform_vea9x4
LIBS = base
SRC_CC = main.cc
INC_DIR += $(PRG_DIR) $(PRG_DIR)/../include

208
repos/os/src/server/tz_vmm/vea9x4/tsc_380.h
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@ -1,208 +0,0 @@
/*
* \brief Driver for the CoreLink Trustzone Address Space Controller TSC-380
* \author Stefan Kalkowski
* \date 2012-07-04
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _BASE_HW__SRC__SERVER__VMM__TSC_380_H_
#define _BASE_HW__SRC__SERVER__VMM__TSC_380_H_
/* Genode includes */
#include <util/mmio.h>
class Tsc_380 : Genode::Mmio
{
private:
enum {
REGION0_REG_OFF = 0x100,
REGION1_REG_OFF = 0x110,
REGION2_REG_OFF = 0x120,
REGION3_REG_OFF = 0x130,
REGION4_REG_OFF = 0x140,
REGION5_REG_OFF = 0x150,
REGION6_REG_OFF = 0x160,
REGION7_REG_OFF = 0x170,
REGION8_REG_OFF = 0x180,
REGION9_REG_OFF = 0x190,
REGION10_REG_OFF = 0x1a0,
REGION11_REG_OFF = 0x1b0,
REGION12_REG_OFF = 0x1c0,
REGION13_REG_OFF = 0x1d0,
REGION14_REG_OFF = 0x1e0,
REGION15_REG_OFF = 0x1f0,
REGION_LOW_OFF = 0x0,
REGION_HIGH_OFF = 0x4,
REGION_ATTR_OFF = 0x8,
};
/**
* Configuration register
*/
struct Config : public Register<0, 32>
{
struct Region_number : Bitfield<0,4> { };
struct Address_width : Bitfield<8,6> { };
};
struct Irq_status : public Register<0x10, 32>
{
struct Status : Bitfield<0,1> {};
struct Overrun : Bitfield<1,1> {};
};
struct Irq_clear : public Register<0x14, 32>
{
struct Status : Bitfield<0,1> {};
struct Overrun : Bitfield<1,1> {};
};
/**
* Fail address low register
*/
struct Fail_low : public Register<0x20, 32> { };
template <Genode::off_t OFF>
struct Region_low : public Register<OFF + REGION_LOW_OFF, 32>
{
enum { MASK = ~0UL << 15 };
};
template <Genode::off_t OFF>
struct Region_high : public Register<OFF + REGION_HIGH_OFF, 32> { };
template <Genode::off_t OFF>
struct Region_attr : public Register<OFF + REGION_ATTR_OFF, 32>
{
struct Enable :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<0, 1> { };
struct Size :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<1, 6>
{
enum {
SZ_32K = 14,
SZ_64K,
SZ_128K,
SZ_256K,
SZ_512K,
SZ_1M,
SZ_2M,
SZ_4M,
SZ_8M,
SZ_16M,
SZ_32M,
SZ_64M,
SZ_128M,
SZ_256M,
SZ_512M,
SZ_1G,
};
};
struct Subreg0 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<8, 1> { };
struct Subreg1 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<9, 1> { };
struct Subreg2 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<10, 1> { };
struct Subreg3 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<11, 1> { };
struct Subreg4 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<12, 1> { };
struct Subreg5 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<13, 1> { };
struct Subreg6 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<14, 1> { };
struct Subreg7 :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<15, 1> { };
struct Normal_write :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<28, 1> { };
struct Normal_read :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<29, 1> { };
struct Secure_write :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<30, 1> { };
struct Secure_read :
Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<31, 1> { };
};
typedef Region_low<0x100> Region0_low;
public:
Tsc_380(Genode::addr_t const base) : Genode::Mmio(base)
{
/* Access to AACI, MMCI, KMI0/1 */
write<Region_low<REGION15_REG_OFF> >(0x10000000);
write<Region_high<REGION15_REG_OFF> >(0x10008000);
write<Region_attr<REGION15_REG_OFF>::Enable>(1);
write<Region_attr<REGION15_REG_OFF>::Size>(Region_attr<REGION15_REG_OFF>::Size::SZ_32K);
write<Region_attr<REGION15_REG_OFF>::Normal_read>(1);
write<Region_attr<REGION15_REG_OFF>::Normal_write>(1);
write<Region_attr<REGION15_REG_OFF>::Secure_read>(1);
write<Region_attr<REGION15_REG_OFF>::Secure_write>(1);
write<Region_attr<REGION15_REG_OFF>::Subreg0>(1);
write<Region_attr<REGION15_REG_OFF>::Subreg1>(1);
write<Region_attr<REGION15_REG_OFF>::Subreg2>(1);
write<Region_attr<REGION15_REG_OFF>::Subreg3>(1);
/* Access to UART0, and WDT */
write<Region_low<REGION14_REG_OFF> >(0x10008000);
write<Region_high<REGION14_REG_OFF> >(0x10010000);
write<Region_attr<REGION14_REG_OFF>::Enable>(1);
write<Region_attr<REGION14_REG_OFF>::Size>(Region_attr<REGION14_REG_OFF>::Size::SZ_32K);
write<Region_attr<REGION14_REG_OFF>::Normal_read>(1);
write<Region_attr<REGION14_REG_OFF>::Normal_write>(1);
write<Region_attr<REGION14_REG_OFF>::Secure_read>(1);
write<Region_attr<REGION14_REG_OFF>::Secure_write>(1);
write<Region_attr<REGION14_REG_OFF>::Subreg0>(1);
write<Region_attr<REGION14_REG_OFF>::Subreg2>(1);
write<Region_attr<REGION14_REG_OFF>::Subreg3>(1);
write<Region_attr<REGION14_REG_OFF>::Subreg4>(1);
write<Region_attr<REGION14_REG_OFF>::Subreg5>(1);
write<Region_attr<REGION14_REG_OFF>::Subreg6>(1);
/* Access to SP804 2/3, and RTC */
write<Region_low<REGION13_REG_OFF> >(0x10010000);
write<Region_high<REGION13_REG_OFF> >(0x10018000);
write<Region_attr<REGION13_REG_OFF>::Enable>(1);
write<Region_attr<REGION13_REG_OFF>::Size>(Region_attr<REGION13_REG_OFF>::Size::SZ_32K);
write<Region_attr<REGION13_REG_OFF>::Normal_read>(1);
write<Region_attr<REGION13_REG_OFF>::Normal_write>(1);
write<Region_attr<REGION13_REG_OFF>::Secure_read>(1);
write<Region_attr<REGION13_REG_OFF>::Secure_write>(1);
write<Region_attr<REGION13_REG_OFF>::Subreg0>(1);
write<Region_attr<REGION13_REG_OFF>::Subreg1>(1);
write<Region_attr<REGION13_REG_OFF>::Subreg3>(1);
write<Region_attr<REGION13_REG_OFF>::Subreg4>(1);
write<Region_attr<REGION13_REG_OFF>::Subreg5>(1);
write<Region_attr<REGION13_REG_OFF>::Subreg6>(1);
/* Access to Ethernet and USB */
write<Region_low<REGION12_REG_OFF> >(0x4e000000);
write<Region_high<REGION12_REG_OFF> >(0x50000000);
write<Region_attr<REGION12_REG_OFF>::Enable>(1);
write<Region_attr<REGION12_REG_OFF>::Size>(Region_attr<REGION12_REG_OFF>::Size::SZ_32M);
write<Region_attr<REGION12_REG_OFF>::Normal_read>(1);
write<Region_attr<REGION12_REG_OFF>::Normal_write>(1);
write<Region_attr<REGION12_REG_OFF>::Secure_read>(1);
write<Region_attr<REGION12_REG_OFF>::Secure_write>(1);
/* clear interrupts */
write<Irq_clear>(0x3);
}
void* last_failed_access() {
void *ret = (void*) read<Fail_low>();
write<Irq_clear>(0x3);
return ret;
}
};
#endif /* _BASE_HW__SRC__SERVER__VMM__TSC_380_H_ */

1
tool/builddir/etc/build.conf.hw_vea9x4_tz
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@ -1 +0,0 @@
REPOSITORIES += $(GENODE_DIR)/repos/base-hw

4
tool/create_builddir
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@ -29,7 +29,6 @@ usage:
@echo " 'codezero_vpb926'"
@echo " 'hw_panda'"
@echo " 'hw_vea9x4'"
@echo " 'hw_vea9x4_tz'"
@echo " 'hw_pbxa9'"
@echo " 'hw_imx31'"
@echo " 'hw_imx53'"
@ -216,9 +215,6 @@ hw_pbxa9::
hw_vea9x4::
@echo "SPECS = genode hw_vea9x4" > $(BUILD_DIR)/etc/specs.conf
hw_vea9x4_tz::
@echo "SPECS = genode hw_vea9x4_tz" > $(BUILD_DIR)/etc/specs.conf
hw_panda::
@echo "SPECS = genode hw_panda" > $(BUILD_DIR)/etc/specs.conf