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imx31: remove platform completely (fix #1360)

This commit is contained in:
Stefan Kalkowski 2015-01-12 11:48:43 +01:00 committed by Christian Helmuth
parent 0f18ecc142
commit 901bff813d
13 changed files with 19 additions and 516 deletions
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17
repos/base-hw/doc/hw.txt
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@ -16,10 +16,7 @@ For further target specific informations, have a look at
'<GENODE_DIR>/repos/base-hw/doc/<TARGET>.txt' where '<TARGET>'
is one of the following:
'pbxa9' - Realview PBXA9
'vea9x4' - Versatile Express A9X4
'imx31' - Freescale i.MX31
'panda' - PandaBoard A2
'panda' - PandaBoard A2
Prerequisites
@ -61,10 +58,14 @@ build directory you want to create, and the hardware target to run Genode on.
Where '<TARGET>' is one of the following, depending on the hardware system
you aim at:
'pbxa9' - Realview PBXA9
'vea9x4' - Versatile Express A9X4
'imx31' - Freescale i.MX31
'panda' - PandaBoard A2
'arndale' - Arndale (Exynos5) board
'imx53' - i.MX53 based board
'imx53_tz' - i.MX53 based board using TrustZone
'odroid_xu' - Odroid XU (Exynos5) board
'panda' - PandaBoard A2
'pbxa9' - Realview PBXA9
'rpi' - Raspberry PI
'vea9x4' - Versatile Express A9X4
Please notice that not all of these targets might be emulateable with Qemu.
To be on the safe side use 'pbxa9'. For informations about how to boot

92
repos/base-hw/doc/imx31.txt
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@ -1,92 +0,0 @@
==================================================
Getting started with 'base-hw' on Freescale i.MX31
==================================================
Martin Stein
Abstract
########
This is a short tutorial that depicts a handy way to get a Genode ELF-image,
build with 'base-hw', started on the Freescale i.MX31. For informations
about how to build Genode images with 'base-hw', have a look at
'<GENODE_DIR>/repos/base-hw/doc/hw.txt'. This tutorial is dedicated to common
Linux systems, but all examples originate from a Ubuntu 11.10.
Tutorial
########
Connect the i.MX31 to your local Ethernet through its RJ45 connector.
Additionally connect the i.MX31 to your machine through its COM port.
We use the bootloader that is installed on the board by the manufacturer, it's
the LogicLoader by Logic Product Development, Version 2.3.5-IMX31_10 0001.
Now install the following packages to communicate with the i.MX31:
! apt-get install tftp-hpa minicom
Open '/etc/default/tftpd-hpa' with a text editor and ensure that it has
the following content:
! TFTP_USERNAME="tftp"
! TFTP_DIRECTORY="/var/lib/tftpboot"
! TFTP_ADDRESS="0.0.0.0:69"
! TFTP_OPTIONS="-l"
Tell TFTP wich image to provide:
! cd /var/lib/tftpboot/
! ln -s <GENODE_BOOT_ELF> image.elf
Where '<GENODE_BOOT_ELF>' is the absolute path of the targeted ELF image.
Start TFTP to enable the upload of the image:
! service tftp-hpa restart
Precautionary determine the inet address of your TFTP machine:
! ifconfig
Start Minicom in configuration mode:
! minicom -s
Go to 'Serial port setting' and ensure that the device is set to the
TTY of the COM port you've conntected the i.MX31 with. In my case it was
'/dev/ttyS0'. Configure the other settings for a baud rate of '115200',
8 bit char length, no parity and 1 stop bit. Quit Minicom and start
it once more in a dedicated terminal:
! minicom
Plug in the i.MX31 power connector or push the 'S1' button if the i.MX31 is
already powered. Minicom should now show the following message below some
bootloader info:
! losh>
We have to start DHCP first, so in the Minicom console type:
! ifconfig sm0 dhcp
Wait until DHCP is started:
! Starting DHCP on sm0 ...
! losh>
Then load the Genode image:
! load elf /tftp/<INET_ADDR>:/var/lib/tftpboot/image.elf
Where '<INET_ADDR>' is the inet address of your TFTP machine.
To execute the loaded image type:
! exec start
Now your Genode scenario should start and offer its debug output
in Minicom. You can boot other images by redirecting the link
'/var/lib/tftpboot/image.elf' accordingly, restarting your i.MX31
and instructing LogicLoader again as described above.

16
repos/base-hw/lib/mk/platform_imx31/core.mk
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@ -1,16 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Martin Stein
# \date 2012-10-04
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include/spec/imx31
INC_DIR += $(REP_DIR)/src/core/include/spec/imx
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += spec/imx31/platform_support.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/arm_v6/core.inc

18
repos/base-hw/mk/spec-hw_imx31.mk
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@ -1,18 +0,0 @@
#
# \brief Build configurations for 'base-hw' on Freescale i.MX31
# \author Martin Stein
# \date 2011-12-20
#
# denote wich specs are also fullfilled by this spec
SPECS += hw platform_imx31 epit
# configure multiprocessor mode
NR_OF_CPUS = 1
# set address where to link the text segment at
LD_TEXT_ADDR ?= 0x82000000
# include implied specs
include $(call select_from_repositories,mk/spec-hw.mk)
include $(call select_from_repositories,mk/spec-platform_imx31.mk)

6
repos/base-hw/src/core/include/spec/imx/serial.h
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@ -18,14 +18,14 @@
#include <board.h>
/* Genode includes */
#include <drivers/uart/imx31_uart_base.h>
#include <drivers/uart/imx_uart_base.h>
namespace Genode
{
/**
* Serial output driver for core
*/
class Serial : public Imx31_uart_base
class Serial : public Imx_uart_base
{
public:
@ -34,7 +34,7 @@ namespace Genode
*
* XXX: The 'baud_rate' argument is ignored for now.
*/
Serial(unsigned) : Imx31_uart_base(Board::UART_1_MMIO_BASE) { }
Serial(unsigned) : Imx_uart_base(Board::UART_1_MMIO_BASE) { }
};
}

102
repos/base-hw/src/core/include/spec/imx31/board.h
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@ -1,102 +0,0 @@
/*
* \brief Board driver for core
* \author Martin Stein
* \date 2012-11-01
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/* Genode includes */
#include <drivers/board_base.h>
namespace Genode
{
/**
* AHB-lite 2v6 to IP bus interface
*/
class Aips : public Mmio
{
/**
* Configuration of the masters
*/
struct Mpr { enum { ALL_UNBUFFERED_AND_FULLY_TRUSTED = 0x77777777 }; };
struct Mpr1 : Register<0x0, 32>, Mpr { };
struct Mpr2 : Register<0x4, 32>, Mpr { };
/**
* Configuration of the platform peripherals
*/
struct Pacr { enum { ALL_UNBUFFERED_AND_FULLY_UNPROTECTED = 0 }; };
struct Pacr1 : Register<0x20, 32>, Pacr { };
struct Pacr2 : Register<0x24, 32>, Pacr { };
struct Pacr3 : Register<0x28, 32>, Pacr { };
struct Pacr4 : Register<0x2c, 32>, Pacr { };
/**
* Configuration of the off-platform peripherals
*/
struct Opacr1 : Register<0x40, 32>, Pacr { };
struct Opacr2 : Register<0x44, 32>, Pacr { };
struct Opacr3 : Register<0x48, 32>, Pacr { };
struct Opacr4 : Register<0x4c, 32>, Pacr { };
struct Opacr5 : Register<0x50, 32>, Pacr { };
public:
/**
* Constructor
*/
Aips(addr_t const base) : Mmio(base) { }
/**
* Configure this module appropriately for the first kernel run
*/
void prepare_kernel()
{
/* avoid AIPS intervention at any memory access */
write<Mpr1>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
write<Mpr2>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
write<Pacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Pacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Pacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Pacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr5>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
}
};
/**
* Board driver for core
*/
struct Board : Board_base
{
/**
* Static AIPS 1 instance
*/
static Aips * aips_1() { static Aips a(AIPS_1_MMIO_BASE); return &a; }
/**
* Static AIPS 2 instance
*/
static Aips * aips_2() { static Aips a(AIPS_2_MMIO_BASE); return &a; }
/**
* Configure this module appropriately for the first kernel run
*/
static void prepare_kernel()
{
aips_1()->prepare_kernel();
aips_2()->prepare_kernel();
}
static void outer_cache_invalidate() { }
static void outer_cache_flush() { }
static bool is_smp() { return false; }
};
}
#endif /* _BOARD_H_ */

115
repos/base-hw/src/core/include/spec/imx31/pic.h
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@ -1,115 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Martin Stein
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _PIC_H_
#define _PIC_H_
namespace Genode
{
/**
* Programmable interrupt controller for core
*/
class Pic;
}
class Genode::Pic : public Mmio
{
private:
struct Intcntl : Register<0x0, 32> { }; /* IRQ control register */
struct Nimask : Register<0x4, 32> { }; /* normal IRQ mask reg. */
struct Intennum : Register<0x8, 32> { }; /* IRQ enable nr. reg. */
struct Intdisnum : Register<0xc, 32> { }; /* IRQ disable nr. reg. */
struct Intenableh : Register<0x10, 32> { }; /* IRQ enable register */
struct Intenablel : Register<0x14, 32> { }; /* IRQ enable register */
struct Inttypeh : Register<0x18, 32> { }; /* IRQ type register */
struct Inttypel : Register<0x1c, 32> { }; /* IRQ type register */
struct Intsrch : Register<0x48, 32> { }; /* IRQ source register */
struct Intsrcl : Register<0x4c, 32> { }; /* IRQ source register */
struct Nipndh : Register<0x58, 32> { }; /* normal IRQ pending */
struct Nipndl : Register<0x5c, 32> { }; /* normal IRQ pending */
/**
* Normal interrupt priority registers
*/
struct Nipriority : Register_array<0x20, 32, 8, 32> { };
/**
* Normal interrupt vector and status register
*/
struct Nivecsr : Register<0x40, 32>
{
struct Nvector : Bitfield<16, 16> { };
};
/**
* Validate request number 'i'
*/
bool _valid(unsigned const i) const { return i < NR_OF_IRQ; }
public:
enum { NR_OF_IRQ = 64 };
/**
* Constructor
*/
Pic() : Mmio(Board::AVIC_MMIO_BASE)
{
write<Intenablel>(0);
write<Intenableh>(0);
write<Nimask>(~0);
write<Intcntl>(0);
write<Inttypeh>(0);
write<Inttypel>(0);
for (unsigned i = 0; i < Nipriority::ITEMS; i++) {
write<Nipriority>(0, i); }
}
/**
* Try to receive an IRQ in 'i' and return wether it was successful
*/
bool take_request(unsigned & i)
{
i = read<Nivecsr::Nvector>();
return _valid(i);
}
/**
* Unmask IRQ 'i'
*/
void unmask(unsigned const i, unsigned) {
if (_valid(i)) { write<Intennum>(i); } }
/**
* Mask IRQ 'i'
*/
void mask(unsigned const i) { if (i < NR_OF_IRQ) write<Intdisnum>(i); }
/**
* Return wether IRQ 'irq_id' is inter-processor IRQ of CPU 'cpu_id'
*/
bool is_ip_interrupt(unsigned, unsigned) { return false; }
/*************
** Dummies **
*************/
void init_cpu_local() { }
void trigger_ip_interrupt(unsigned) { }
void finish_request() { /* done by source retraction or masking */ }
};
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _PIC_H_ */

72
repos/base-hw/src/core/spec/imx31/platform_support.cc
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@ -1,72 +0,0 @@
/*
* \brief Platform implementations specific for base-hw and i.MX31
* \author Norman Feske
* \date 2012-08-30
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* core includes */
#include <platform.h>
#include <board.h>
#include <pic.h>
#include <cpu.h>
using namespace Genode;
Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
/*
* The address range below 0x30000000 is used for secure ROM, ROM, and
* internal RAM.
*/
{ 0x30000000, 0x50000000 },
/*
* The address range between 0x8000000 and 0x9fffffff is designated for
* SDRAM. The remaining address range is populated with peripherals.
*/
{ 0xa0000000, 0x24000000 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Native_region * Platform::_core_only_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
/* core UART */
{ Board::UART_1_MMIO_BASE, Board::UART_1_MMIO_SIZE },
/* core timer */
{ Board::EPIT_1_MMIO_BASE, Board::EPIT_1_MMIO_SIZE },
/* interrupt controller */
{ Board::AVIC_MMIO_BASE, Board::AVIC_MMIO_SIZE },
/* bus interface controller */
{ Board::AIPS_1_MMIO_BASE, Board::AIPS_1_MMIO_SIZE },
{ Board::AIPS_2_MMIO_BASE, Board::AIPS_2_MMIO_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
Cpu::User_context::User_context() { cpsr = Psr::init_user(); }

14
repos/base/include/drivers/uart/imx31_uart_base.h → repos/base/include/drivers/uart/imx_uart_base.h
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@ -1,5 +1,5 @@
/*
* \brief Driver base for i.MX31 UART-module
* \brief Driver base for Freescale's i.MX UART-module
* \author Norman Feske
* \author Martin Stein
* \date 2012-08-30
@ -12,8 +12,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__UART__IMX31_UART_BASE_H_
#define _INCLUDE__DRIVERS__UART__IMX31_UART_BASE_H_
#ifndef _INCLUDE__DRIVERS__UART__IMX_UART_BASE_H_
#define _INCLUDE__DRIVERS__UART__IMX_UART_BASE_H_
/* Genode includes */
#include <util/mmio.h>
@ -21,9 +21,9 @@
namespace Genode
{
/**
* Driver base for i.MX31 UART-module
* Driver base for i.MX UART-module
*/
class Imx31_uart_base : Mmio
class Imx_uart_base : Mmio
{
/**
* Control register 1
@ -245,7 +245,7 @@ namespace Genode
*
* \param base device MMIO base
*/
explicit Imx31_uart_base(addr_t const base) : Mmio(base)
explicit Imx_uart_base(addr_t const base) : Mmio(base)
{
write<Cr1>(Cr1::init_value());
write<Cr2>(Cr2::init_value());
@ -270,5 +270,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__UART__IMX31_UART_BASE_H_ */
#endif /* _INCLUDE__DRIVERS__UART__IMX_UART_BASE_H_ */

63
repos/base/include/platform/imx31/drivers/board_base.h
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@ -1,63 +0,0 @@
/*
* \brief Board definitions for the i.MX31
* \author Martin Stein
* \author Norman Feske
* \date 2011-11-03
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__BOARD_BASE_H_
#define _INCLUDE__PLATFORM__BOARD_BASE_H_
/* Genode includes */
#include <util/mmio.h>
namespace Genode
{
/**
* i.MX31 motherboard
*/
struct Board_base
{
enum {
RAM_0_BASE = 0x80000000,
RAM_0_SIZE = 0x20000000,
MMIO_0_BASE = 0x30000000,
MMIO_0_SIZE = 0x50000000,
UART_1_IRQ = 45,
UART_1_MMIO_BASE = 0x43f90000,
UART_1_MMIO_SIZE = 0x00004000,
EPIT_1_IRQ = 28,
EPIT_1_MMIO_BASE = 0x53f94000,
EPIT_1_MMIO_SIZE = 0x00004000,
EPIT_2_IRQ = 27,
EPIT_2_MMIO_BASE = 0x53f98000,
EPIT_2_MMIO_SIZE = 0x00004000,
AVIC_MMIO_BASE = 0x68000000,
AVIC_MMIO_SIZE = 0x04000000,
AIPS_1_MMIO_BASE = 0x43F00000,
AIPS_1_MMIO_SIZE = 0x00004000,
AIPS_2_MMIO_BASE = 0x53F00000,
AIPS_2_MMIO_SIZE = 0x00004000,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
};
};
}
#endif /* _INCLUDE__PLATFORM__BOARD_BASE_H_ */

15
repos/base/mk/spec-platform_imx31.mk
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@ -1,15 +0,0 @@
#
# \brief Build-system configurations for Freescale i.MX31
# \author Martin Stein
# \date 2012-09-26
#
# denote wich specs are also fullfilled by this spec
SPECS += arm_v6
# add repository relative include paths
REP_INC_DIR += include/platform/imx31
# include implied specs
include $(call select_from_repositories,mk/spec-arm_v6.mk)

1
tool/builddir/etc/build.conf.hw_imx31
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@ -1 +0,0 @@
REPOSITORIES += $(GENODE_DIR)/repos/base-hw

4
tool/create_builddir
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@ -30,7 +30,6 @@ usage:
@echo " 'hw_panda'"
@echo " 'hw_vea9x4'"
@echo " 'hw_pbxa9'"
@echo " 'hw_imx31'"
@echo " 'hw_imx53'"
@echo " 'hw_imx53_tz'"
@echo " 'hw_arndale'"
@ -218,9 +217,6 @@ hw_vea9x4::
hw_panda::
@echo "SPECS = genode hw_panda" > $(BUILD_DIR)/etc/specs.conf
hw_imx31::
@echo "SPECS = genode hw_imx31" > $(BUILD_DIR)/etc/specs.conf
hw_imx53::
@echo "SPECS = genode hw_imx53" > $(BUILD_DIR)/etc/specs.conf