parent
875858b2cc
commit
0b77e8ea62
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@ -1,3 +1,5 @@
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REQUIRES = muen
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
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SRC_CC += bootstrap/spec/x86_64/platform_muen.cc
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SRC_CC += bootstrap/spec/x86_64/platform_muen.cc
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@ -123,7 +123,6 @@ class Bootstrap::Platform
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};
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};
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Board board { };
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Board board { };
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Bootstrap::Cpu cpu { };
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Ram_allocator ram_alloc { };
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Ram_allocator ram_alloc { };
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Memory_region const bootstrap_region;
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Memory_region const bootstrap_region;
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Genode::Constructible<Pd> core_pd { };
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Genode::Constructible<Pd> core_pd { };
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@ -15,9 +15,9 @@
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#include <spec/arm/cpu.h>
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#include <spec/arm/cpu.h>
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void Bootstrap::Cpu::invalidate_data_cache() {
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void Board::Cpu::invalidate_data_cache() {
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asm volatile ("mcr p15, 0, %[rd], c7, c6, 0" :: [rd]"r"(0) : ); }
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asm volatile ("mcr p15, 0, %[rd], c7, c6, 0" :: [rd]"r"(0) : ); }
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void Bootstrap::Cpu::clean_invalidate_data_cache() {
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void Board::Cpu::clean_invalidate_data_cache() {
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asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }
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asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }
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@ -128,7 +128,7 @@
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::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
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::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
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void Bootstrap::Cpu::invalidate_data_cache()
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void Board::Cpu::invalidate_data_cache()
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{
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{
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/**
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/**
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* Data Cache Invalidate by Set/Way for all Set/Way
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* Data Cache Invalidate by Set/Way for all Set/Way
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@ -139,7 +139,7 @@ void Bootstrap::Cpu::invalidate_data_cache()
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}
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}
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void Bootstrap::Cpu::clean_invalidate_data_cache()
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void Board::Cpu::clean_invalidate_data_cache()
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{
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{
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/**
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/**
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* Data Cache Clean by Set/Way for all Set/Way
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* Data Cache Clean by Set/Way for all Set/Way
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@ -14,7 +14,7 @@
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#include <spec/arm/cpu.h>
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#include <spec/arm/cpu.h>
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void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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{
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{
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/* invalidate TLB */
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/* invalidate TLB */
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Tlbiall::write(0);
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Tlbiall::write(0);
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@ -15,8 +15,8 @@
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unsigned Bootstrap::Platform::enable_mmu()
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unsigned Bootstrap::Platform::enable_mmu()
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{
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{
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Cpu::Sctlr::init();
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::Board::Cpu::Sctlr::init();
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Cpu::enable_mmu_and_caches((addr_t)core_pd->table_base);
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::Board::Cpu::enable_mmu_and_caches((addr_t)core_pd->table_base);
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return 0;
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return 0;
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}
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}
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@ -18,7 +18,7 @@
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namespace Bootstrap { struct Actlr; }
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namespace Bootstrap { struct Actlr; }
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struct Bootstrap::Actlr : Bootstrap::Cpu::Actlr
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struct Bootstrap::Actlr : Board::Cpu::Actlr
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{
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{
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struct Fw : Bitfield<0, 1> { };
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struct Fw : Bitfield<0, 1> { };
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struct L2_prefetch_enable : Bitfield<1, 1> { };
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struct L2_prefetch_enable : Bitfield<1, 1> { };
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@ -103,7 +103,7 @@ struct Scu : Genode::Mmio
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*/
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*/
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unsigned Bootstrap::Platform::enable_mmu()
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unsigned Bootstrap::Platform::enable_mmu()
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{
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{
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using namespace Bootstrap;
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using namespace Board;
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static volatile bool primary_cpu = true;
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static volatile bool primary_cpu = true;
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static Cpu_counter data_cache_invalidated;
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static Cpu_counter data_cache_invalidated;
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@ -13,7 +13,7 @@
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#include <spec/arm/cpu.h>
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#include <spec/arm/cpu.h>
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void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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{
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{
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/* invalidate TLB */
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/* invalidate TLB */
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Tlbiall::write(0);
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Tlbiall::write(0);
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@ -16,9 +16,9 @@
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#include <hw/spec/arm/cpu.h>
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#include <hw/spec/arm/cpu.h>
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namespace Bootstrap { struct Cpu; }
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namespace Board { struct Cpu; }
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struct Bootstrap::Cpu : Hw::Arm_cpu
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struct Board::Cpu : Hw::Arm_cpu
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{
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{
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struct Sctlr : Hw::Arm_cpu::Sctlr
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struct Sctlr : Hw::Arm_cpu::Sctlr
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{
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{
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@ -36,11 +36,11 @@ Bootstrap::Platform::Board::Board()
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}
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}
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bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
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bool Board::Cpu::errata(Board::Cpu::Errata err) {
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return (err == ARM_764369) ? true : false; }
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return (err == ARM_764369) ? true : false; }
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void Bootstrap::Cpu::wake_up_all_cpus(void * const entry)
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void Board::Cpu::wake_up_all_cpus(void * const entry)
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{
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{
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struct Src : Genode::Mmio
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struct Src : Genode::Mmio
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{
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{
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@ -152,6 +152,8 @@ static inline void switch_to_supervisor_mode()
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unsigned Bootstrap::Platform::enable_mmu()
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unsigned Bootstrap::Platform::enable_mmu()
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{
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{
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using namespace ::Board;
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static volatile bool primary_cpu = true;
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static volatile bool primary_cpu = true;
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board.pic.init_cpu_local();
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board.pic.init_cpu_local();
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Cpu::Sctlr::init();
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Cpu::Sctlr::init();
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Cpu::Cpsr::init();
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Cpu::Cpsr::init();
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cpu.invalidate_data_cache();
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Cpu::invalidate_data_cache();
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/* primary cpu wakes up all others */
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/* primary cpu wakes up all others */
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if (primary_cpu && NR_OF_CPUS > 1) {
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if (primary_cpu && NR_OF_CPUS > 1) {
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primary_cpu = false;
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primary_cpu = false;
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cpu.wake_up_all_cpus(&_start_setup_stack);
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Cpu::wake_up_all_cpus(&_start_setup_stack);
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}
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}
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cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
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return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
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}
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}
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void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
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void Board::Cpu::wake_up_all_cpus(void * const ip)
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{
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{
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*(void * volatile *)Board::IRAM_BASE = ip;
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*(void * volatile *)Board::IRAM_BASE = ip;
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asm volatile("dsb; sev;");
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asm volatile("dsb; sev;");
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/* primary cpu wakes up all others */
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/* primary cpu wakes up all others */
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if (primary_cpu && NR_OF_CPUS > 1) {
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if (primary_cpu && NR_OF_CPUS > 1) {
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cpu.invalidate_data_cache();
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Cpu::invalidate_data_cache();
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primary_cpu = false;
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primary_cpu = false;
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cpu.wake_up_all_cpus(&_start_setup_stack);
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Cpu::wake_up_all_cpus(&_start_setup_stack);
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}
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}
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cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
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return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
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}
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}
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void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
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void Board::Cpu::wake_up_all_cpus(void * const ip)
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{
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{
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struct Src : Genode::Mmio
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struct Src : Genode::Mmio
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{
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{
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board.pic.init_cpu_local();
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board.pic.init_cpu_local();
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Cpu::Sctlr::init();
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Cpu::Sctlr::init();
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Cpu::Cpsr::init();
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Cpu::Cpsr::init();
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cpu.invalidate_data_cache();
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Cpu::invalidate_data_cache();
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cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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return 0;
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return 0;
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}
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}
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PL310_MMIO_SIZE }) { }
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PL310_MMIO_SIZE }) { }
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bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) { return false; }
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bool Board::Cpu::errata(Board::Cpu::Errata) { return false; }
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void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
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void Board::Cpu::wake_up_all_cpus(void * const ip)
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{
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{
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struct Wakeup_generator : Genode::Mmio
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struct Wakeup_generator : Genode::Mmio
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{
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{
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Wakeup_generator(void * const ip) : Mmio(CORTEX_A9_WUGEN_MMIO_BASE)
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Wakeup_generator(void * const ip) : Mmio(CORTEX_A9_WUGEN_MMIO_BASE)
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{
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{
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write<Aux_core_boot_1>((addr_t)ip);
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write<Aux_core_boot_1>((Genode::addr_t)ip);
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write<Aux_core_boot_0::Cpu1_status>(1);
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write<Aux_core_boot_0::Cpu1_status>(1);
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}
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}
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};
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};
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PL310_MMIO_SIZE }) { }
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PL310_MMIO_SIZE }) { }
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bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) { return false; }
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bool Board::Cpu::errata(Board::Cpu::Errata) { return false; }
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void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
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void Board::Cpu::wake_up_all_cpus(void * const ip)
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{
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{
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/**
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/**
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* set the entrypoint for the other CPUs via the flags register
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* set the entrypoint for the other CPUs via the flags register
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@ -21,8 +21,6 @@ namespace Board {
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struct Pic {};
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struct Pic {};
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}
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}
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namespace Bootstrap { struct Cpu {}; }
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template <typename E, unsigned B, unsigned S>
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template <typename E, unsigned B, unsigned S>
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void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
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void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
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{ }
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{ }
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void Hw::Page_table::_translation_added(unsigned long, unsigned long) {
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void Hw::Page_table::_translation_added(unsigned long, unsigned long) {
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Bootstrap::Cpu::clean_invalidate_data_cache(); }
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Board::Cpu::clean_invalidate_data_cache(); }
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#endif /* _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_ */
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#endif /* _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_ */
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@ -37,6 +37,8 @@ Bootstrap::Platform::Board::Board()
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unsigned Bootstrap::Platform::enable_mmu()
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unsigned Bootstrap::Platform::enable_mmu()
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{
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{
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using ::Board::Cpu;
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struct Sctlr : Cpu::Sctlr
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struct Sctlr : Cpu::Sctlr
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{
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{
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struct W : Bitfield<3,1> { }; /* enable write buffer */
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struct W : Bitfield<3,1> { }; /* enable write buffer */
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#include <hw/spec/arm_64/cpu.h>
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#include <hw/spec/arm_64/cpu.h>
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#include <hw/spec/arm/lpae.h>
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#include <hw/spec/arm/lpae.h>
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namespace Bootstrap {
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using Cpu = Hw::Arm_64_cpu;
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};
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namespace Board {
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namespace Board {
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using namespace Hw::Rpi3_board;
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using namespace Hw::Rpi3_board;
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using Cpu = Hw::Arm_64_cpu;
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struct Pic {};
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struct Pic {};
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};
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};
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#include <platform.h>
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#include <platform.h>
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using Bootstrap::Cpu;
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using Board::Cpu;
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/**
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/**
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@ -19,12 +19,9 @@
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#include <hw/spec/x86_64/cpu.h>
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#include <hw/spec/x86_64/cpu.h>
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#include <hw/spec/x86_64/x86_64.h>
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#include <hw/spec/x86_64/x86_64.h>
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namespace Bootstrap {
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using Cpu = Hw::X86_64_cpu;
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}
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namespace Board {
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namespace Board {
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using namespace Hw::Pc_board;
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using namespace Hw::Pc_board;
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using Cpu = Hw::X86_64_cpu;
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struct Pic {};
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struct Pic {};
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}
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}
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@ -277,6 +277,8 @@ static inline void ipi_to_all(Lapic &lapic, unsigned const boot_frame,
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unsigned Bootstrap::Platform::enable_mmu()
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unsigned Bootstrap::Platform::enable_mmu()
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{
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{
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using ::Board::Cpu;
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Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
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Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
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addr_t const stack_base = reinterpret_cast<addr_t>(&__bootstrap_stack);
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addr_t const stack_base = reinterpret_cast<addr_t>(&__bootstrap_stack);
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@ -46,6 +46,8 @@ Bootstrap::Platform::Board::Board()
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unsigned Bootstrap::Platform::enable_mmu()
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unsigned Bootstrap::Platform::enable_mmu()
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{
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{
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using ::Board::Cpu;
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Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
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Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
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return 0;
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return 0;
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}
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}
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@ -29,17 +29,17 @@ Bootstrap::Platform::Board::Board()
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PL310_MMIO_SIZE }) { }
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PL310_MMIO_SIZE }) { }
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bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) {
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bool Cpu::errata(Board::Cpu::Errata) {
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return false; }
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return false; }
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void Bootstrap::Cpu::wake_up_all_cpus(void* ip) {
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void Cpu::wake_up_all_cpus(void* ip) {
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struct Wakeup_generator : Genode::Mmio
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struct Wakeup_generator : Genode::Mmio
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{
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{
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struct Core1_boot_addr : Register<0x0, 32> { };
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struct Core1_boot_addr : Register<0x0, 32> { };
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Wakeup_generator(void * const ip) : Mmio(CORE1_ENTRY)
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Wakeup_generator(void * const ip) : Mmio(CORE1_ENTRY)
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{
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{
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write<Core1_boot_addr>((addr_t)ip);
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write<Core1_boot_addr>((Genode::addr_t)ip);
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}
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}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue