145 lines
4.3 KiB
C++
145 lines
4.3 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and Raspberry Pi3
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* \author Stefan Kalkowski
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* \date 2019-05-11
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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using Board::Cpu;
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/**
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* Leave out the first page (being 0x0) from bootstraps RAM allocator,
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* some code does not feel happy with addresses being zero
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*/
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Bootstrap::Platform::Board::Board()
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: early_ram_regions(Memory_region { ::Board::RAM_BASE + 0x1000,
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::Board::RAM_SIZE - 0x1000 }),
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late_ram_regions(Memory_region { ::Board::RAM_BASE, 0x1000 }),
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core_mmio(Memory_region { ::Board::UART_BASE, ::Board::UART_SIZE },
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Memory_region { ::Board::LOCAL_IRQ_CONTROLLER_BASE,
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::Board::LOCAL_IRQ_CONTROLLER_SIZE },
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Memory_region { ::Board::IRQ_CONTROLLER_BASE,
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::Board::IRQ_CONTROLLER_SIZE }) {}
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static inline void prepare_non_secure_world()
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{
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bool el2 = Cpu::Id_pfr0::El2::get(Cpu::Id_pfr0::read());
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Cpu::Scr::access_t scr = Cpu::Scr::read();
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Cpu::Scr::Ns::set(scr, 1); /* set non-secure bit */
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Cpu::Scr::Rw::set(scr, 1); /* exec in aarch64 */
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Cpu::Scr::Smd::set(scr, 1); /* disable smc call */
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Cpu::Scr::write(scr);
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Cpu::Spsr::access_t pstate = 0;
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Cpu::Spsr::Sp::set(pstate, 1); /* select non-el0 stack pointer */
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Cpu::Spsr::El::set(pstate, el2 ? Cpu::Current_el::EL2
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: Cpu::Current_el::EL1);
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Cpu::Spsr::F::set(pstate, 1);
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Cpu::Spsr::I::set(pstate, 1);
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Cpu::Spsr::A::set(pstate, 1);
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Cpu::Spsr::D::set(pstate, 1);
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Cpu::Spsr_el3::write(pstate);
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#ifndef SWITCH_TO_ELX
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#define SWITCH_TO_ELX(el) \
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"mov x0, sp \n" \
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"msr sp_" #el ", x0 \n" \
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"adr x0, 1f \n" \
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"msr elr_el3, x0 \n" \
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"eret \n" \
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"1:"
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if (el2)
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asm volatile(SWITCH_TO_ELX(el2) ::: "x0");
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else
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asm volatile(SWITCH_TO_ELX(el1) ::: "x0");
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#undef SWITCH_TO_ELX
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#else
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#error "macro SWITCH_TO_ELX already defined"
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#endif
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}
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static inline void prepare_hypervisor()
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{
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Cpu::Hcr::access_t scr = Cpu::Hcr::read();
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Cpu::Hcr::Rw::set(scr, 1); /* exec in aarch64 */
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Cpu::Hcr::write(scr);
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Cpu::Spsr::access_t pstate = 0;
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Cpu::Spsr::Sp::set(pstate, 1); /* select non-el0 stack pointer */
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Cpu::Spsr::El::set(pstate, Cpu::Current_el::EL1);
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Cpu::Spsr::F::set(pstate, 1);
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Cpu::Spsr::I::set(pstate, 1);
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Cpu::Spsr::A::set(pstate, 1);
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Cpu::Spsr::D::set(pstate, 1);
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Cpu::Spsr_el2::write(pstate);
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asm volatile("mov x0, sp \n"
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"msr sp_el1, x0 \n"
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"adr x0, 1f \n"
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"msr elr_el2, x0 \n"
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"eret \n"
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"1:");
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}
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unsigned Bootstrap::Platform::enable_mmu()
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{
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while (Cpu::current_privilege_level() > Cpu::Current_el::EL1) {
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if (Cpu::current_privilege_level() == Cpu::Current_el::EL3)
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prepare_non_secure_world();
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else
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prepare_hypervisor();
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}
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Cpu::Vbar_el1::write(Hw::Mm::supervisor_exception_vector().base);
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/* set memory attributes in indirection register */
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Cpu::Mair::access_t mair = 0;
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Cpu::Mair::Attr0::set(mair, Cpu::Mair::NORMAL_MEMORY_UNCACHED);
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Cpu::Mair::Attr1::set(mair, Cpu::Mair::DEVICE_MEMORY);
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Cpu::Mair::Attr2::set(mair, Cpu::Mair::NORMAL_MEMORY_CACHED);
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Cpu::Mair::Attr3::set(mair, Cpu::Mair::DEVICE_MEMORY);
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Cpu::Mair::write(mair);
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Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::Baddr::masked((Genode::addr_t)core_pd->table_base);
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Cpu::Ttbr0_el1::write(ttbr);
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Cpu::Ttbr1_el1::write(ttbr);
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Cpu::Tcr_el1::access_t tcr = 0;
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Cpu::Tcr_el1::T0sz::set(tcr, 25);
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Cpu::Tcr_el1::T1sz::set(tcr, 25);
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Cpu::Tcr_el1::Irgn0::set(tcr, 1);
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Cpu::Tcr_el1::Irgn1::set(tcr, 1);
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Cpu::Tcr_el1::Orgn0::set(tcr, 1);
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Cpu::Tcr_el1::Orgn1::set(tcr, 1);
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Cpu::Tcr_el1::Sh0::set(tcr, 0b10);
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Cpu::Tcr_el1::Sh1::set(tcr, 0b10);
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Cpu::Tcr_el1::Ips::set(tcr, 0b10);
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Cpu::Tcr_el1::As::set(tcr, 1);
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Cpu::Tcr_el1::write(tcr);
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Cpu::Sctlr_el1::access_t sctlr = Cpu::Sctlr_el1::read();
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Cpu::Sctlr_el1::C::set(sctlr, 1);
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Cpu::Sctlr_el1::I::set(sctlr, 1);
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Cpu::Sctlr_el1::A::set(sctlr, 0);
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Cpu::Sctlr_el1::M::set(sctlr, 1);
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Cpu::Sctlr_el1::Sa0::set(sctlr, 1);
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Cpu::Sctlr_el1::Sa::set(sctlr, 0);
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Cpu::Sctlr_el1::write(sctlr);
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return 0;
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}
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