ec6c19a487
The memory barrier prevents the compiler from changing the program order of memory accesses in such a way that accesses to the guarded resource get outside the guarded stage. As cmpxchg() defines the start of the guarded stage it also represents an effective memory barrier. On x86, the architecture ensures to not reorder writes with older reads, writes to memory with other writes (except in cases that are not relevant for our locks), or read/write instructions with I/O instructions, locked instructions, and serializing instructions. However on ARM, the architectural memory model allows not only that memory accesses take local effect in another order as their program order but also that different observers (components that can access memory like data-busses, TLBs and branch predictors) observe these effects each in another order. Thus, a correct program order isn't sufficient for a correct observation order. An additional architectural preservation of the memory barrier is needed to achieve this. Fixes #692 |
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| .. | ||
| 32bit/base | ||
| 64bit/base | ||
| arm | ||
| arm_v5/cpu | ||
| arm_v6/cpu | ||
| arm_v7/cpu | ||
| base | ||
| cap_session | ||
| cpu | ||
| cpu_session | ||
| dataspace | ||
| drivers | ||
| io_mem_session | ||
| io_port_session | ||
| irq_session | ||
| log_session | ||
| pager | ||
| parent | ||
| pd_session | ||
| platform | ||
| platform_exynos5 | ||
| ram_session | ||
| rm_session | ||
| rom_session | ||
| root | ||
| session | ||
| signal_session | ||
| thread | ||
| trace_session | ||
| util | ||
| x86/cpu | ||
| x86_32/cpu | ||
| x86_64/cpu | ||
| README | ||
This directory contains include files of interfaces that are exported by components to be used by other components. Each subdirectory corresponds to the component exporting the interface.