base: introduce caching attributes (fix #1184)

On ARM it's relevant to not only distinguish between ordinary cached memory
and write-combined one, but also having non-cached memory too. To insert the
appropriated page table entries e.g.: in the base-hw kernel, we need to preserve
the information about the kind of memory from allocation until the pager
resolves a page fault. Therefore, this commit introduces a new Cache_attribute
type, and replaces the write_combined boolean with the new type where necessary.
This commit is contained in:
Stefan Kalkowski 2014-06-19 16:37:31 +02:00 committed by Norman Feske
parent 9580954d81
commit 786fe805da
60 changed files with 216 additions and 160 deletions

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@ -14,6 +14,7 @@
#ifndef _INCLUDE__BASE__IPC_PAGER_H_
#define _INCLUDE__BASE__IPC_PAGER_H_
#include <base/cache.h>
#include <base/ipc.h>
#include <base/stdint.h>
#include <base/native_types.h>
@ -37,7 +38,7 @@ namespace Genode {
* Constructor
*/
Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute const cacheability, bool io_mem,
unsigned l2size = PAGE_SIZE_LOG2,
bool rw = true)
:

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@ -58,6 +58,15 @@ extern void *memcpy(void *dest, const void *src, __SIZE_TYPE__);
#undef max
#endif
#undef printf
/*
* Turn '#define cacheable' (as defined in the codezero headers) into an enum
* value. Otherwise, the define will conflict with variables named 'cacheable'.
*/
enum { _codezero_cacheable = cacheable /* #define value */ };
#undef cacheable
enum { cacheable = _codezero_cacheable };
} }
namespace Codezero {

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@ -15,6 +15,7 @@
#define _INCLUDE__BASE__IPC_PAGER_H_
/* Genode includes */
#include <base/cache.h>
#include <base/ipc.h>
#include <base/stdint.h>
#include <base/native_types.h>
@ -41,14 +42,14 @@ namespace Genode {
* Constructor
*/
Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute cacheability, bool io_mem,
unsigned l2size = L4_LOG2_PAGESIZE,
bool rw = true, bool grant = false)
:
_dst_addr(dst_addr),
_fpage(Fiasco::l4_fpage(src_addr, l2size, rw, grant))
{
if (write_combined)
if (cacheability == WRITE_COMBINED)
_fpage.fp.cache = Fiasco::L4_FPAGE_BUFFERABLE;
}

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@ -16,6 +16,7 @@
#define _INCLUDE__BASE__IPC_PAGER_H_
/* Genode includes */
#include <base/cache.h>
#include <base/ipc.h>
#include <base/stdint.h>
#include <base/native_types.h>
@ -33,12 +34,13 @@ namespace Genode {
{
private:
addr_t _dst_addr;
addr_t _src_addr;
bool _write_combined;
unsigned _log2size;
bool _rw;
bool _grant;
addr_t _dst_addr;
addr_t _src_addr;
Cache_attribute _cacheability;
bool _iomem;
unsigned _log2size;
bool _rw;
bool _grant;
public:
@ -46,34 +48,30 @@ namespace Genode {
* Constructor
*/
Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute c, bool io_mem,
unsigned l2size = L4_LOG2_PAGESIZE,
bool rw = true, bool grant = false)
: _dst_addr(dst_addr), _src_addr(src_addr),
_write_combined(write_combined), _log2size(l2size),
_cacheability(c), _iomem(io_mem), _log2size(l2size),
_rw(rw), _grant(grant) { }
/**
* Construct invalid flexpage
*/
Mapping() : _dst_addr(0), _src_addr(0), _write_combined(false),
_log2size(0), _rw(false), _grant(false) { }
Mapping() : _dst_addr(0), _src_addr(0), _cacheability(UNCACHED),
_iomem(false), _log2size(0), _rw(false), _grant(false) { }
Fiasco::l4_umword_t dst_addr() const { return _dst_addr; }
bool grant() const { return _grant; }
Fiasco::l4_fpage_t fpage() const
{
// TODO: write combined
//if (write_combined)
// _fpage.fp.cache = Fiasco::L4_FPAGE_BUFFERABLE;
unsigned char rights = _rw ? Fiasco::L4_FPAGE_RWX : Fiasco::L4_FPAGE_RX;
return Fiasco::l4_fpage(_src_addr, _log2size, rights);
}
bool write_combined() const { return _write_combined; }
Cache_attribute cacheability() const { return _cacheability; }
bool iomem() { return _iomem; }
/**
* Prepare map operation is not needed on Fiasco.OC, since we clear the
* dataspace before this function is called.

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@ -87,12 +87,20 @@ void Ipc_pager::reply_and_wait_for_fault()
l4_umword_t grant = _reply_mapping.grant() ? L4_MAP_ITEM_GRANT : 0;
l4_utcb_mr()->mr[0] = _reply_mapping.dst_addr() | L4_ITEM_MAP | grant;
/*
* XXX Does L4_FPAGE_BUFFERABLE imply L4_FPAGE_UNCACHEABLE?
*/
if (_reply_mapping.write_combined())
switch (_reply_mapping.cacheability()) {
case WRITE_COMBINED:
l4_utcb_mr()->mr[0] |= L4_FPAGE_BUFFERABLE << 4;
break;
case CACHED:
l4_utcb_mr()->mr[0] |= L4_FPAGE_CACHEABLE << 4;
break;
case UNCACHED:
if (!_reply_mapping.iomem())
l4_utcb_mr()->mr[0] |= L4_FPAGE_BUFFERABLE << 4;
else
l4_utcb_mr()->mr[0] |= L4_FPAGE_UNCACHEABLE << 4;
break;
}
l4_utcb_mr()->mr[1] = _reply_mapping.fpage().raw;
_tag = l4_ipc_send_and_wait(_last, l4_utcb(), snd_tag,

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@ -29,7 +29,7 @@ void Ram_session_component::_clear_ds(Dataspace_component *ds)
{
memset((void *)ds->phys_addr(), 0, ds->size());
if (ds->write_combined())
if (ds->cacheability() != CACHED)
Fiasco::l4_cache_dma_coherent(ds->phys_addr(), ds->phys_addr() + ds->size());
}

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@ -14,6 +14,7 @@
#ifndef _INCLUDE__BASE__IPC_PAGER_H_
#define _INCLUDE__BASE__IPC_PAGER_H_
#include <base/cache.h>
#include <base/ipc.h>
#include <base/stdint.h>
#include <base/native_types.h>
@ -28,7 +29,7 @@ namespace Genode {
* Constructor
*/
Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute, bool io_mem,
unsigned l2size = 12, bool rw = true) { }
/**

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@ -60,12 +60,12 @@ namespace Genode
struct Genode::Mapping
{
addr_t virt_address;
addr_t phys_address;
bool write_combined;
bool io_mem;
unsigned size_log2;
bool writable;
addr_t virt_address;
addr_t phys_address;
Cache_attribute cacheable;
bool io_mem;
unsigned size_log2;
bool writable;
/**
* Constructor for invalid mappings
@ -75,7 +75,7 @@ struct Genode::Mapping
/**
* Constructor for valid mappings
*/
Mapping(addr_t const va, addr_t const pa, bool const wc,
Mapping(addr_t const va, addr_t const pa, Cache_attribute const c,
bool const io, unsigned const sl2, bool const w);
/**

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@ -22,17 +22,18 @@ using namespace Genode;
** Mapping **
*************/
Mapping::Mapping(addr_t const va, addr_t const pa, bool const wc,
bool const io, unsigned const sl2, bool const w)
Mapping::Mapping(addr_t const va, addr_t const pa,
Cache_attribute const c, bool const io,
unsigned const sl2, bool const w)
:
virt_address(va), phys_address(pa), write_combined(wc),
virt_address(va), phys_address(pa), cacheable(c),
io_mem(io), size_log2(sl2), writable(w)
{ }
Mapping::Mapping()
:
virt_address(0), phys_address(0), write_combined(0),
virt_address(0), phys_address(0), cacheable(CACHED),
io_mem(0), size_log2(0), writable(0)
{ }

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@ -25,9 +25,14 @@ Arm::memory_region_attr(Page_flags const & flags)
typedef typename T::Tex Tex;
typedef typename T::C C;
typedef typename T::B B;
if(flags.device) { return 0; }
if(flags.cacheable) { return Tex::bits(5) | B::bits(1); }
return Tex::bits(6) | C::bits(1);
if (flags.device) { return 0; }
switch (flags.cacheable) {
case CACHED: return Tex::bits(5) | B::bits(1);
case WRITE_COMBINED: return B::bits(1);
case UNCACHED: return Tex::bits(1);
}
return 0;
}
#endif /* _ARM_V6__TRANSLATION_TABLE_H_ */

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@ -26,8 +26,13 @@ Arm::memory_region_attr(Page_flags const & flags)
typedef typename T::C C;
typedef typename T::B B;
if (flags.device) { return Tex::bits(2); }
if (flags.cacheable) { return Tex::bits(5) | B::bits(1); }
return Tex::bits(6) | C::bits(1);
switch (flags.cacheable) {
case CACHED: return Tex::bits(5) | B::bits(1);
case WRITE_COMBINED: return B::bits(1);
case UNCACHED: return Tex::bits(1);
}
return 0;
}
#endif /* _ARM_V7__TRANSLATION_TABLE_H_ */

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@ -14,6 +14,8 @@
#ifndef _TLB__PAGE_FLAGS_H_
#define _TLB__PAGE_FLAGS_H_
#include <base/cache.h>
namespace Genode
{
/**
@ -21,34 +23,35 @@ namespace Genode
*/
struct Page_flags
{
bool writeable;
bool executable;
bool privileged;
bool global;
bool device;
bool cacheable;
bool writeable;
bool executable;
bool privileged;
bool global;
bool device;
Cache_attribute cacheable;
/**
* Create flag POD for Genode pagers
*/
static const Page_flags
apply_mapping(bool const writeable,
bool const write_combined,
Cache_attribute const cacheable,
bool const io_mem) {
return Page_flags { writeable, true, false, false,
io_mem, !write_combined && !io_mem }; }
io_mem, cacheable }; }
/**
* Create flag POD for kernel when it creates the core space
*/
static const Page_flags map_core_area(bool const io_mem) {
return Page_flags { true, true, false, false, io_mem, !io_mem }; }
return Page_flags { true, true, false, false, io_mem,
io_mem ? UNCACHED : CACHED}; }
/**
* Create flag POD for the mode transition region
*/
static const Page_flags mode_transition() {
return Page_flags { true, true, true, true, false, true }; }
return Page_flags { true, true, true, true, false, CACHED }; }
};
}

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@ -128,7 +128,7 @@ Platform_thread::Platform_thread(const char * const label,
Ram_session_component * const ram =
dynamic_cast<Ram_session_component *>(core_env()->ram_session());
assert(ram);
try { _utcb = ram->alloc(sizeof(Native_utcb), 1); }
try { _utcb = ram->alloc(sizeof(Native_utcb), CACHED); }
catch (...) {
PERR("failed to allocate UTCB");
throw Cpu_session::Out_of_metadata();

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@ -51,7 +51,7 @@ void Ram_session_component::_clear_ds (Dataspace_component * ds)
memset(virt_addr, 0, page_rounded_size);
/* uncached dataspaces need to be flushed */
if (ds->write_combined())
if (ds->cacheability() != CACHED)
Kernel::update_data_region((addr_t)virt_addr, page_rounded_size);
/* unmap dataspace from core */

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@ -65,7 +65,7 @@ int Pager_activation_base::apply_mapping()
Page_flags const flags =
Page_flags::apply_mapping(_mapping.writable,
_mapping.write_combined,
_mapping.cacheable,
_mapping.io_mem);
/* insert mapping into translation table */

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@ -59,7 +59,7 @@ Vm_session_component::Vm_session_component(Rpc_entrypoint *ds_ep,
size_t ram_quota)
: _ds_ep(ds_ep), _ram_alloc(ram_alloc), _vm_id(0),
_ds_addr(_alloc_ds(&ram_quota)),
_ds(_ds_size(), _ds_addr, _ds_addr, false, true, 0),
_ds(_ds_size(), _ds_addr, _ds_addr, UNCACHED, true, 0),
_ds_cap(static_cap_cast<Dataspace>(_ds_ep->manage(&_ds)))
{
/* alloc needed memory */

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@ -84,7 +84,8 @@ class Context_area_ram_session : public Genode::Ram_session
{
public:
Genode::Ram_dataspace_capability alloc(Genode::size_t size, bool) {
Genode::Ram_dataspace_capability alloc(Genode::size_t size,
Genode::Cache_attribute) {
return Genode::Ram_dataspace_capability(); }
void free(Genode::Ram_dataspace_capability) { }

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@ -52,7 +52,7 @@ namespace Genode {
* Constructor
*/
Dataspace_component(size_t size, addr_t addr,
bool /* write_combined */, bool writable,
Cache_attribute, bool writable,
Dataspace_owner * owner)
: _size(size), _addr(addr), _fd(-1), _writable(writable),
_owner(owner) { }
@ -68,7 +68,7 @@ namespace Genode {
* reasons and should not be used.
*/
Dataspace_component(size_t size, addr_t core_local_addr,
addr_t phys_addr, bool write_combined,
addr_t phys_addr, Cache_attribute,
bool writable, Dataspace_owner * _owner)
:
_size(size), _addr(phys_addr), _fd(-1), _owner(_owner)

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@ -65,7 +65,7 @@ Rom_session_component::Rom_session_component(Rom_fs *rom_fs,
int const fd = lx_open(fname, O_RDONLY | LX_O_CLOEXEC, S_IRUSR | S_IXUSR);
_ds = Dataspace_component(fsize, 0, false, false, 0);
_ds = Dataspace_component(fsize, 0, CACHED, false, 0);
_ds.fd(fd);
_ds.fname(fname);

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@ -15,6 +15,7 @@
#define _INCLUDE__BASE__IPC_PAGER_H_
/* Genode includes */
#include <base/cache.h>
#include <base/ipc.h>
#include <base/stdint.h>
#include <base/native_types.h>
@ -43,12 +44,12 @@ namespace Genode {
* Constructor
*/
Mapping(addr_t dst_addr, addr_t map_addr,
bool write_combined, bool io_mem,
Cache_attribute c, bool io_mem,
unsigned size_log2 = PAGE_SIZE_LOG2,
bool rw = true)
:
_dst_addr(dst_addr), _core_local_addr(map_addr),
_write_combined(write_combined), _size_log2(size_log2),
_write_combined(c != CACHED), _size_log2(size_log2),
_rw(rw)
{ }

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@ -14,6 +14,7 @@
#ifndef _INCLUDE__BASE__IPC_PAGER_H_
#define _INCLUDE__BASE__IPC_PAGER_H_
#include <base/cache.h>
#include <base/ipc.h>
#include <base/stdint.h>
#include <base/native_types.h>
@ -40,7 +41,7 @@ namespace Genode {
* Constructor
*/
Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute cacheability, bool io_mem,
unsigned l2size = 12, bool rw = true);
/**

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@ -62,7 +62,7 @@ static inline Okl4::L4_ThreadId_t thread_get_my_global_id()
*************/
Mapping::Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute cacheability, bool io_mem,
unsigned l2size, bool rw)
:
_fpage(L4_FpageLog2(dst_addr, l2size)),

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@ -15,6 +15,7 @@
#define _INCLUDE__BASE__IPC_PAGER_H_
/* Genode includes */
#include <base/cache.h>
#include <base/native_types.h>
#include <base/ipc.h>
#include <base/stdint.h>
@ -37,20 +38,13 @@ namespace Genode {
Pistachio::L4_GrantItem_t _grant_item;
};
/*
* On Pistachio, the write-combining attribute is not part of a mapping
* but it can be applied to a flexpage via the memory-control system
* call. Therefore, we need to keep the flag in an extra member variable.
*/
bool _write_combined; /* enable write-combined access to I/O memory */
public:
/**
* Constructor
*/
Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem,
Cache_attribute, bool io_mem,
unsigned l2size = Pistachio::get_page_size_log2(),
bool rw = true, bool grant = false);

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@ -32,10 +32,8 @@ using namespace Pistachio;
*************/
Mapping::Mapping(addr_t dst_addr, addr_t src_addr,
bool write_combined, bool io_mem, unsigned l2size,
Cache_attribute, bool io_mem, unsigned l2size,
bool rw, bool grant)
:
_write_combined(write_combined)
{
L4_Fpage_t fpage = L4_FpageLog2(src_addr, l2size);

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@ -104,7 +104,7 @@ addr_t Io_mem_session_component::_map_local(addr_t base, size_t size)
L4_Fpage(base + offset, page_size),
L4_Fpage(local_base + offset, page_size));
if (_write_combined) {
if (_cacheable == WRITE_COMBINED) {
int res = L4_Set_PageAttribute(L4_Fpage(local_base + offset, page_size),
L4_WriteCombiningMemory);
if (res != 1)

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@ -0,0 +1,20 @@
/*
* \brief Generic cache declarations
* \author Stefan Kalkowski
* \date 2014-06-17
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__BASE__CACHE_H_
#define _INCLUDE__BASE__CACHE_H_
namespace Genode {
enum Cache_attribute { UNCACHED, WRITE_COMBINED, CACHED };
}
#endif /* _INCLUDE__BASE__CACHE_H_ */

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@ -25,7 +25,8 @@ namespace Genode {
explicit Ram_session_client(Ram_session_capability session)
: Rpc_client<Ram_session>(session) { }
Ram_dataspace_capability alloc(size_t size, bool cached = true) {
Ram_dataspace_capability alloc(size_t size,
Cache_attribute cached = CACHED) {
return call<Rpc_alloc>(size, cached); }
void free(Ram_dataspace_capability ds) { call<Rpc_free>(ds); }

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@ -17,6 +17,7 @@
#include <base/stdint.h>
#include <base/capability.h>
#include <base/exception.h>
#include <base/cache.h>
#include <dataspace/capability.h>
#include <ram_session/capability.h>
#include <session/session.h>
@ -49,7 +50,7 @@ namespace Genode {
* Allocate RAM dataspace
*
* \param size size of RAM dataspace
* \param cached true for cached memory, false for allocating
* \param cached selects cacheability attributes of the memory,
* uncached memory, i.e., for DMA buffers
*
* \throw Quota_exceeded
@ -57,7 +58,7 @@ namespace Genode {
* \return capability to new RAM dataspace
*/
virtual Ram_dataspace_capability alloc(size_t size,
bool cached = true) = 0;
Cache_attribute cached = CACHED) = 0;
/**
* Free RAM dataspace
@ -116,7 +117,7 @@ namespace Genode {
GENODE_RPC_THROW(Rpc_alloc, Ram_dataspace_capability, alloc,
GENODE_TYPE_LIST(Quota_exceeded, Out_of_metadata),
size_t, bool);
size_t, Cache_attribute);
GENODE_RPC(Rpc_free, void, free, Ram_dataspace_capability);
GENODE_RPC(Rpc_ref_account, int, ref_account, Ram_session_capability);
GENODE_RPC(Rpc_transfer_quota, int, transfer_quota, Ram_session_capability, size_t);

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@ -87,7 +87,7 @@ struct Genode::Expanding_ram_session_client : Upgradeable_client<Genode::Ram_ses
Expanding_ram_session_client(Ram_session_capability cap)
: Upgradeable_client<Genode::Ram_session_client>(cap) { }
Ram_dataspace_capability alloc(size_t size, bool cached = true)
Ram_dataspace_capability alloc(size_t size, Cache_attribute cached = UNCACHED)
{
/*
* If the RAM session runs out of quota, issue a resource request

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@ -135,7 +135,7 @@ class Context_area_ram_session : public Ram_session
public:
Ram_dataspace_capability alloc(size_t size, bool cached)
Ram_dataspace_capability alloc(size_t size, Cache_attribute cached)
{
/* find free context */
unsigned i;
@ -161,7 +161,7 @@ class Context_area_ram_session : public Ram_session
PDBG("phys_base = %p, size = 0x%zx", phys_base, size);
context_ds[i] = new (&_ds_slab)
Dataspace_component(size, 0, (addr_t)phys_base, false, true, 0);
Dataspace_component(size, 0, (addr_t)phys_base, CACHED, true, 0);
Dataspace_capability cap = Dataspace_capability::local_cap(context_ds[i]);
return static_cap_cast<Ram_dataspace>(cap);

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@ -70,7 +70,7 @@ namespace Genode {
** RAM-session interface **
***************************/
Ram_dataspace_capability alloc(size_t size, bool cached)
Ram_dataspace_capability alloc(size_t size, Cache_attribute cached)
{
Lock::Guard lock_guard(_lock);
return RAM_SESSION_IMPL::alloc(size, cached);

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@ -41,8 +41,8 @@ namespace Genode {
addr_t _core_local_addr; /* address of core-local mapping */
size_t const _size; /* size of dataspace in bytes */
bool const _is_io_mem; /* dataspace is I/O mem, not to be touched */
bool const _write_combined; /* access I/O memory write-combined, or
RAM uncacheable respectively */
Cache_attribute const _cache; /* access memory cached, write-combined, or
uncached respectively */
bool const _writable; /* false if dataspace is read-only */
List<Rm_region> _regions; /* regions this is attached to */
@ -73,7 +73,7 @@ namespace Genode {
Dataspace_component()
:
_phys_addr(0), _core_local_addr(0), _size(0),
_is_io_mem(false), _write_combined(false), _writable(false),
_is_io_mem(false), _cache(CACHED), _writable(false),
_owner(0), _managed(false) { }
/**
@ -82,12 +82,12 @@ namespace Genode {
* This constructor is used by RAM and ROM dataspaces.
*/
Dataspace_component(size_t size, addr_t core_local_addr,
bool write_combined, bool writable,
Cache_attribute cache, bool writable,
Dataspace_owner *owner)
:
_phys_addr(core_local_addr), _core_local_addr(core_local_addr),
_size(round_page(size)), _is_io_mem(false),
_write_combined(write_combined), _writable(writable),
_cache(cache), _writable(writable),
_owner(owner), _managed(false) { }
/**
@ -101,11 +101,11 @@ namespace Genode {
* space is needed to send a mapping to another address space.
*/
Dataspace_component(size_t size, addr_t core_local_addr,
addr_t phys_addr, bool write_combined,
addr_t phys_addr, Cache_attribute cache,
bool writable, Dataspace_owner *owner)
:
_phys_addr(phys_addr), _core_local_addr(core_local_addr),
_size(size), _is_io_mem(true), _write_combined(write_combined),
_size(size), _is_io_mem(true), _cache(cache),
_writable(writable), _owner(owner), _managed(false) { }
/**
@ -120,9 +120,9 @@ namespace Genode {
*/
virtual Native_capability sub_rm_session() { return Dataspace_capability(); }
addr_t core_local_addr() const { return _core_local_addr; }
bool is_io_mem() const { return _is_io_mem; }
bool write_combined() const { return _write_combined; }
addr_t core_local_addr() const { return _core_local_addr; }
bool is_io_mem() const { return _is_io_mem; }
Cache_attribute cacheability() const { return _cache; }
/**
* Return dataspace base address to be used for map operations

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@ -35,10 +35,10 @@ namespace Genode {
*/
struct Dataspace_attr
{
size_t size;
addr_t core_local_addr;
addr_t phys_addr;
bool write_combined;
size_t size;
addr_t core_local_addr;
addr_t phys_addr;
Cache_attribute cacheable;
/**
* Base address of request used for freeing mem-ranges
@ -59,11 +59,11 @@ namespace Genode {
* An invalid dataspace is represented by setting all
* arguments to zero.
*/
Dataspace_attr(size_t s, addr_t cla, addr_t pa, bool write_combined,
Dataspace_attr(size_t s, addr_t cla, addr_t pa, Cache_attribute c,
addr_t req_base)
:
size(s), core_local_addr(cla), phys_addr(pa),
write_combined(write_combined), req_base(req_base) { }
cacheable(c), req_base(req_base) { }
};
struct Io_dataspace_component : Dataspace_component
@ -76,7 +76,7 @@ namespace Genode {
Io_dataspace_component(Dataspace_attr da)
:
Dataspace_component(da.size, da.core_local_addr,
da.phys_addr, da.write_combined,
da.phys_addr, da.cacheable,
true, 0),
req_base(da.req_base) { }
@ -88,7 +88,7 @@ namespace Genode {
Io_dataspace_component _ds;
Rpc_entrypoint *_ds_ep;
Io_mem_dataspace_capability _ds_cap;
bool _write_combined;
Cache_attribute _cacheable;
Dataspace_attr _prepare_io_mem(const char *args, Range_allocator *ram_alloc);

View File

@ -161,7 +161,7 @@ namespace Genode {
** RAM Session interface **
***************************/
Ram_dataspace_capability alloc(size_t, bool);
Ram_dataspace_capability alloc(size_t, Cache_attribute);
void free(Ram_dataspace_capability);
int ref_account(Ram_session_capability);
int transfer_quota(Ram_session_capability, size_t);

View File

@ -263,7 +263,7 @@ namespace Genode {
*/
Rm_dataspace_component(size_t size)
:
Dataspace_component(size, 0, false, false, 0)
Dataspace_component(size, 0, CACHED, false, 0)
{ _managed = true; }

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@ -37,11 +37,11 @@ Io_mem_session_component::_prepare_io_mem(const char *args,
addr_t base = req_base & ~(get_page_size() - 1);
size_t size = end - base;
_write_combined = false;
_cacheable = UNCACHED;
Arg a = Arg_string::find_arg(args, "wc");
if (a.valid())
_write_combined = a.bool_value(0);
if (a.valid() && a.bool_value(0))
_cacheable = WRITE_COMBINED;
/* check for RAM collision */
int ret;
@ -69,9 +69,9 @@ Io_mem_session_component::_prepare_io_mem(const char *args,
if (verbose)
PDBG("I/O mem [%lx,%lx) => [%lx,%lx)%s",
base, base + size, local_addr, local_addr + size,
_write_combined ? " (write-combined)" : "");
(_cacheable == WRITE_COMBINED) ? " (write-combined)" : "");
return Dataspace_attr(size, local_addr, base, _write_combined, req_base);
return Dataspace_attr(size, local_addr, base, _cacheable, req_base);
}

View File

@ -106,7 +106,7 @@ void Ram_session_component::_remove_ref_account_member(Ram_session_component *me
}
Ram_dataspace_capability Ram_session_component::alloc(size_t ds_size, bool cached)
Ram_dataspace_capability Ram_session_component::alloc(size_t ds_size, Cache_attribute cached)
{
/* zero-sized dataspaces are not allowed */
if (!ds_size) return Ram_dataspace_capability();
@ -171,7 +171,7 @@ Ram_dataspace_capability Ram_session_component::alloc(size_t ds_size, bool cache
* when resolving page faults.
*/
ds = new (&_ds_slab)
Dataspace_component(ds_size, (addr_t)ds_addr, !cached, true, this);
Dataspace_component(ds_size, (addr_t)ds_addr, cached, true, this);
} catch (Allocator::Out_of_memory) {
PWRN("Could not allocate metadata");
/* cleanup unneeded resources */

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@ -280,7 +280,7 @@ int Rm_client::pager(Ipc_pager &pager)
Mapping mapping(dst_fault_area.base(),
src_fault_area.base(),
src_dataspace->write_combined(),
src_dataspace->cacheability(),
src_dataspace->is_io_mem(),
map_size_log2,
src_dataspace->writable());

View File

@ -25,7 +25,7 @@ Rom_session_component::Rom_session_component(Rom_fs *rom_fs,
:
_rom_module(_find_rom(rom_fs, args)),
_ds(_rom_module ? _rom_module->size() : 0,
_rom_module ? _rom_module->addr() : 0, false, false, 0),
_rom_module ? _rom_module->addr() : 0, CACHED, false, 0),
_ds_ep(ds_ep)
{
/* ROM module not found */

View File

@ -54,7 +54,7 @@ class Genode::Slab_backend_alloc : public Genode::Allocator,
};
addr_t _base; /* virt. base address */
bool _cached; /* non-/cached RAM */
Cache_attribute _cached; /* non-/cached RAM */
Ram_dataspace_capability _ds_cap[ELEMENTS]; /* dataspaces to put in VM */
addr_t _ds_phys[ELEMENTS]; /* physical bases of dataspaces */
int _index; /* current index in ds_cap */
@ -86,7 +86,7 @@ class Genode::Slab_backend_alloc : public Genode::Allocator,
public:
Slab_backend_alloc(bool cached)
Slab_backend_alloc(Cache_attribute cached)
: Rm_connection(0, VM_SIZE), _cached(cached), _index(0),
_range(env()->heap())
{
@ -220,7 +220,7 @@ class Malloc
public:
Malloc(Slab_backend_alloc *alloc, bool cached)
Malloc(Slab_backend_alloc *alloc, Genode::Cache_attribute cached)
: _back_allocator(alloc), _cached(cached), _start(alloc->start()),
_end(alloc->end())
{
@ -312,8 +312,8 @@ class Malloc
*/
static Malloc *mem()
{
static Slab_backend_alloc _b(true);
static Malloc _m(&_b, true);
static Slab_backend_alloc _b(Genode::CACHED);
static Malloc _m(&_b, Genode::CACHED);
return &_m;
}
};

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@ -14,13 +14,17 @@
#ifndef _ARM__PLATFORM__LX_MEM_
#define _ARM__PLATFORM__LX_MEM_
#include <base/cache.h>
class Backend_memory {
public:
static Genode::Ram_dataspace_capability alloc(Genode::addr_t size,
bool cached) {
return Genode::env()->ram_session()->alloc(size, cached); }
Genode::Cache_attribute c)
{
return Genode::env()->ram_session()->alloc(size, c);
}
static void free(Genode::Ram_dataspace_capability cap) {
return Genode::env()->ram_session()->free(cap); }

View File

@ -291,7 +291,7 @@ namespace Nic {
/**
* Root component, handling new session requests
*/
class Root : public Packet_root<Root_component, Session_component, true>
class Root : public Packet_root<Root_component, Session_component, CACHED>
{
public:

View File

@ -74,7 +74,8 @@ class Packet_session_component : public RPC
/**
* Root component, handling new session requests
*/
template <typename ROOT_COMPONENT, typename SESSION_COMPONENT, bool CACHED>
template <typename ROOT_COMPONENT, typename SESSION_COMPONENT,
Genode::Cache_attribute CACHEABILITY>
class Packet_root : public ROOT_COMPONENT
{
private:
@ -116,8 +117,8 @@ class Packet_session_component : public RPC
}
return new (ROOT_COMPONENT::md_alloc())
SESSION_COMPONENT(Backend_memory::alloc(tx_buf_size, CACHED),
Backend_memory::alloc(rx_buf_size, CACHED),
SESSION_COMPONENT(Backend_memory::alloc(tx_buf_size, CACHEABILITY),
Backend_memory::alloc(rx_buf_size, CACHEABILITY),
_ep, _device);
}

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@ -14,12 +14,14 @@
#ifndef _X86__PLATFORM__LX_MEM_
#define _X86__PLATFORM__LX_MEM_
#include <base/cache.h>
class Backend_memory {
public:
static Genode::Ram_dataspace_capability alloc(Genode::addr_t size,
bool cached);
Genode::Cache_attribute);
static void free(Genode::Ram_dataspace_capability cap);
};

View File

@ -56,7 +56,7 @@ class Genode::Slab_backend_alloc : public Genode::Allocator,
};
addr_t _base; /* virt. base address */
bool _cached; /* non-/cached RAM */
Genode::Cache_attribute _cached; /* non-/cached RAM */
Ram_dataspace_capability _ds_cap[ELEMENTS]; /* dataspaces to put in VM */
addr_t _ds_phys[ELEMENTS]; /* physical bases of dataspaces */
int _index; /* current index in ds_cap */
@ -88,7 +88,7 @@ class Genode::Slab_backend_alloc : public Genode::Allocator,
public:
Slab_backend_alloc(bool cached)
Slab_backend_alloc(Genode::Cache_attribute cached)
: Rm_connection(0, VM_SIZE), _cached(cached), _index(0),
_range(env()->heap())
{
@ -206,11 +206,11 @@ class Malloc
typedef Genode::Slab_alloc Slab_alloc;
typedef Genode::Slab_backend_alloc Slab_backend_alloc;
Slab_backend_alloc *_back_allocator;
Slab_alloc *_allocator[NUM_SLABS];
bool _cached; /* cached or un-cached memory */
addr_t _start; /* VM region of this allocator */
addr_t _end;
Slab_backend_alloc *_back_allocator;
Slab_alloc *_allocator[NUM_SLABS];
Genode::Cache_attribute _cached; /* cached or un-cached memory */
addr_t _start; /* VM region of this allocator */
addr_t _end;
/**
* Set 'value' at 'addr'
@ -240,7 +240,7 @@ class Malloc
public:
Malloc(Slab_backend_alloc *alloc, bool cached)
Malloc(Slab_backend_alloc *alloc, Genode::Cache_attribute cached)
: _back_allocator(alloc), _cached(cached), _start(alloc->start()),
_end(alloc->end())
{
@ -326,8 +326,8 @@ class Malloc
*/
static Malloc *mem()
{
static Slab_backend_alloc _b(true);
static Malloc _m(&_b, true);
static Slab_backend_alloc _b(Genode::CACHED);
static Malloc _m(&_b, Genode::CACHED);
return &_m;
}
@ -336,8 +336,8 @@ class Malloc
*/
static Malloc *dma()
{
static Slab_backend_alloc _b(false);
static Malloc _m(&_b, false);
static Slab_backend_alloc _b(Genode::UNCACHED);
static Malloc _m(&_b, Genode::UNCACHED);
return &_m;
}
};

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@ -367,15 +367,15 @@ void Ram_object::free() { Genode::env()->ram_session()->free(ram_cap()); }
void Dma_object::free() { pci.free_dma_buffer(pci_device_cap, ram_cap()); }
Genode::Ram_dataspace_capability Backend_memory::alloc(Genode::addr_t size,
bool cached)
Genode::Ram_dataspace_capability
Backend_memory::alloc(Genode::addr_t size, Genode::Cache_attribute cached)
{
using namespace Genode;
Memory_object_base *o;
Genode::Ram_dataspace_capability cap;
if (cached) {
cap = env()->ram_session()->alloc(size, cached);
if (cached == CACHED) {
cap = env()->ram_session()->alloc(size);
o = new (env()->heap()) Ram_object(cap);
} else {
cap = pci.alloc_dma_buffer(pci_device_cap, size);

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@ -157,7 +157,7 @@ class Storage_device : public Genode::List<Storage_device>::Element,
bool dma_enabled() { return true; }
Genode::Ram_dataspace_capability alloc_dma_buffer(Genode::size_t size) {
return Backend_memory::alloc(size, false); }
return Backend_memory::alloc(size, Genode::UNCACHED); }
void free_dma_buffer(Genode::Ram_dataspace_capability cap) {
return Backend_memory::free(cap); }

View File

@ -62,7 +62,7 @@ namespace Allocator {
typedef Genode::Allocator_avl Allocator_avl;
addr_t _base; /* virt. base address */
bool _cached; /* non-/cached RAM */
Cache_attribute _cached; /* non-/cached RAM */
Ram_dataspace_capability _ds_cap[ELEMENTS]; /* dataspaces to put in VM */
addr_t _ds_phys[ELEMENTS]; /* physical bases of dataspaces */
int _index = 0; /* current index in ds_cap */
@ -107,7 +107,7 @@ namespace Allocator {
public:
Backend_alloc(bool cached)
Backend_alloc(Cache_attribute cached)
: Rm_connection(0, VM_SIZE), _cached(cached),
_range(Genode::env()->heap())
{
@ -195,7 +195,7 @@ namespace Allocator {
public:
Fap(bool cached)
: _back_allocator(cached) { }
: _back_allocator(cached ? CACHED : UNCACHED) { }
void *alloc(size_t size, int align = 0)
{