4ef2b0ed2e
When bringing up the kernel on multiple cores, there is a time span where some cores already have caches enabled and some don't. Core-local storage that may be used during this time must be aligned at least to the maximum line size among global caches. Otherwise, a cached core may unintentionally prefetch data of a yet uncached core into a global cache. This may corrupt the view of the uncached core as soon as it enables caches. However, to determine the exact alignment for every single ARM platform isn't sensible. Instead, we can align to the minimum page size assuming that a cache never wants to prefetch from multiple pages at once and thus fulfills "line size <= page size". Fixes #1937 |
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