Commit Graph

16 Commits

Author SHA1 Message Date
Stefan Kalkowski
657646e76e hw: adjust core bootstrap to fit generic process
* Introduce hw-specific crt0 for core that calls e.g.: init_main_thread
* re-map core's main thread UTCB to fit the right context area location
* switch core's main thread's stack to fit the right context area location

Fix #1440
2015-03-19 08:57:19 +01:00
Reto Buerki
32521cfd71 hw: Declare mtc_size constant in arm/cpu_support.h
This constant specifies the size of the mode transition control region.
2015-03-13 12:17:28 +01:00
Stefan Kalkowski
7582396e9c hw_arndale: enable ARM virtualization extensions
* enables world-switch using ARM virtualization extensions
* split TrustZone and virtualization extensions hardly from platforms,
  where it is not used
* extend 'Vm_session' interface to enable configuration of guest-physical memory
* introduce VM destruction syscall
* add virtual machine monitor for hw_arndale that emulates a simplified version
  of ARM's Versatile Express Cortex A15 board for a Linux guest OS

Fixes #1405
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
07c8d1652e hw_arndale: setup ARM hypervisor mode
To enable support of hardware virtualization for ARM on the Arndale board,
the cpu needs to be prepared to enter the non-secure mode, as long as it does
not already run in it. Therefore, especially the interrupt controller and
some TrustZone specific system registers need to be prepared. Moreover,
the exception vector for the hypervisor needs to be set up properly, before
booting normally in the supervisor mode of the non-secure world.

Ref #1405
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
322be1b4fb hw: LPAE for Cortex a15 (fix #1387) 2015-02-16 13:40:37 +01:00
Stefan Kalkowski
102444b82b hw: remove pointless, wasted memory in pd object
(ref #1387)
2015-02-16 13:40:37 +01:00
Martin Stein
5dea0b40aa hw: don't use ARM CPU-state stuff in generic code
Fixes #1404
2015-02-16 13:40:36 +01:00
Martin Stein
b8ba3a7a22 hw: rename Kernel::Processor Kernel::Cpu
Kernel::Processor was a confusing remnant from the old scheme where we had a
Processor_driver (now Genode::Cpu) and a Processor (now Kernel::Cpu).
This commit also updates the in-code documentation and the variable and
function naming accordingly.

fix #1274
2014-11-28 12:02:35 +01:00
Stefan Kalkowski
3befb64afe hw: correctly flush cache on ARM (fix #1257)
* When flushing the data and unified cache on ARM, clean and invalidate
  instead of just cleaning the corresponding cache lines
* After zero-ing a freshly constructed dataspace in core, invalidate
  corresponding cache lines from the instruction cache
2014-10-10 13:02:30 +02:00
Stefan Kalkowski
f0fae2a5f2 hw: set TTBR0 according to CPU facilities
Fixes #1195
2014-10-10 13:02:30 +02:00
Martin Stein
14e9a89cba hw: no superfluous ORing of zeros and clean up
fix #710
2014-08-15 10:19:49 +02:00
Martin Stein
9da42dde2f hw & arm_v7: mode transition via transit ttbr0
Previously, we did the protection-domain switches without a transitional
translation table that contains only global mappings. This was fine as long
as the CPU did no speculative memory accesses. However, to enabling branch
prediction triggers such accesses. Thus, if we don't want to invalidate
predictors on every context switch, we need to switch more carefully.

ref #474
2014-08-15 10:19:48 +02:00
Martin Stein
03cd76821c hw & arm: exceptions to asserts in transl. table
ref #474
2014-08-15 10:19:48 +02:00
Martin Stein
d48d0e7b43 hw: rename processor CPU
fix #1217
2014-08-15 10:19:48 +02:00
Martin Stein
1cba71208f hw: cpu_support to kernel/thread_base
ref #1217
2014-08-15 10:19:48 +02:00
Martin Stein
a5cf09fa6e hw: re-organize file structure
fix #1197
2014-08-15 10:19:48 +02:00