parent
4c74f4792c
commit
4800bcf5a0
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@ -26,6 +26,11 @@ namespace Board {
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using L2_cache = Hw::Pl310;
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using L2_cache = Hw::Pl310;
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L2_cache & l2_cache();
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L2_cache & l2_cache();
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enum {
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CORTEX_A9_PRIVATE_TIMER_CLK = 396000000, /* timer clk runs half the CPU freq */
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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};
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}
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}
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#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */
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#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */
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@ -25,6 +25,11 @@ namespace Board {
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using L2_cache = Hw::Pl310;
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using L2_cache = Hw::Pl310;
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L2_cache & l2_cache();
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L2_cache & l2_cache();
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enum {
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CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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};
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}
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}
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#endif /* _CORE__SPEC__NIT6_SOLOX__BOARD_H_ */
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#endif /* _CORE__SPEC__NIT6_SOLOX__BOARD_H_ */
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@ -26,6 +26,11 @@ namespace Board {
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using Pic = Hw::Gicv2;
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using Pic = Hw::Gicv2;
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L2_cache & l2_cache();
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L2_cache & l2_cache();
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enum {
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CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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};
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}
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}
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#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */
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#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */
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@ -44,8 +44,6 @@ namespace Imx6 {
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/* CPU */
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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/* L2 cache controller */
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/* L2 cache controller */
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PL310_MMIO_BASE = 0x00a02000,
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PL310_MMIO_BASE = 0x00a02000,
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