diff --git a/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h b/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h
index 0176522ec..800304f37 100644
--- a/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h
+++ b/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h
@@ -26,6 +26,11 @@ namespace Board {
 	using L2_cache = Hw::Pl310;
 
 	L2_cache & l2_cache();
+
+	enum {
+		CORTEX_A9_PRIVATE_TIMER_CLK = 396000000, /* timer clk runs half the CPU freq */
+		CORTEX_A9_PRIVATE_TIMER_DIV = 100,
+	};
 }
 
 #endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */
diff --git a/repos/base-hw/src/core/spec/nit6_solox/board.h b/repos/base-hw/src/core/spec/nit6_solox/board.h
index 6f75b227e..2d94bfb60 100644
--- a/repos/base-hw/src/core/spec/nit6_solox/board.h
+++ b/repos/base-hw/src/core/spec/nit6_solox/board.h
@@ -25,6 +25,11 @@ namespace Board {
 	using L2_cache = Hw::Pl310;
 
 	L2_cache & l2_cache();
+
+	enum {
+		CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
+		CORTEX_A9_PRIVATE_TIMER_DIV = 100,
+	};
 }
 
 #endif /* _CORE__SPEC__NIT6_SOLOX__BOARD_H_ */
diff --git a/repos/base-hw/src/core/spec/wand_quad/board.h b/repos/base-hw/src/core/spec/wand_quad/board.h
index 1426385f9..792a86c47 100644
--- a/repos/base-hw/src/core/spec/wand_quad/board.h
+++ b/repos/base-hw/src/core/spec/wand_quad/board.h
@@ -26,6 +26,11 @@ namespace Board {
 	using Pic      = Hw::Gicv2;
 	
 	L2_cache & l2_cache();
+
+	enum {
+		CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
+		CORTEX_A9_PRIVATE_TIMER_DIV = 100,
+	};
 }
 
 #endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */
diff --git a/repos/base/include/drivers/defs/imx6.h b/repos/base/include/drivers/defs/imx6.h
index bc374cbde..a34a768a3 100644
--- a/repos/base/include/drivers/defs/imx6.h
+++ b/repos/base/include/drivers/defs/imx6.h
@@ -44,8 +44,6 @@ namespace Imx6 {
 		/* CPU */
 		CORTEX_A9_PRIVATE_MEM_BASE  = 0x00a00000,
 		CORTEX_A9_PRIVATE_MEM_SIZE  = 0x00002000,
-		CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
-		CORTEX_A9_PRIVATE_TIMER_DIV = 100,
 
 		/* L2 cache controller */
 		PL310_MMIO_BASE = 0x00a02000,