Basic drivers for UART modules PL011 and TL16C750
This commit is contained in:
Martin Stein
Christian Helmuth
parent
a936cba296
commit
2b0c613336
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/*
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* \brief Driver base for the PrimeCell UART PL011 Revision r1p3
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* \author Martin stein
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* \date 2011-10-17
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE__INCLUDE__DRIVERS__UART__PL011_BASE_H_
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#define _BASE__INCLUDE__DRIVERS__UART__PL011_BASE_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Genode
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{
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/**
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* Driver base for the PrimeCell UART PL011 Revision r1p3
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*/
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class Pl011_base : Mmio
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{
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protected:
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enum {
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MAX_BAUD_RATE = 0xfffffff,
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ASCII_LINE_FEED = 10,
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ASCII_CARRIAGE_RETURN = 13,
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};
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/**
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* Data register
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*/
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struct Uartdr : public Register<0x00, 16>
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{
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struct Data : Bitfield<0,8> { };
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struct Fe : Bitfield<8,1> { };
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struct Pe : Bitfield<9,1> { };
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struct Be : Bitfield<10,1> { };
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struct Oe : Bitfield<11,1> { };
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};
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/**
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* Flag register
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*/
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struct Uartfr : public Register<0x18, 16>
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{
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struct Cts : Bitfield<0,1> { };
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struct Dsr : Bitfield<1,1> { };
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struct Dcd : Bitfield<2,1> { };
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struct Busy : Bitfield<3,1> { };
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struct Rxfe : Bitfield<4,1> { };
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struct Txff : Bitfield<5,1> { };
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struct Rxff : Bitfield<6,1> { };
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struct Txfe : Bitfield<7,1> { };
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struct Ri : Bitfield<8,1> { };
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};
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/**
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* Integer baud rate register
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*/
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struct Uartibrd : public Register<0x24, 16>
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{
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struct Ibrd : Bitfield<0,15> { };
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};
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/**
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* Fractional Baud Rate Register
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*/
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struct Uartfbrd : public Register<0x28, 8>
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{
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struct Fbrd : Bitfield<0,6> { };
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};
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/**
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* Line Control Register
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*/
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struct Uartlcrh : public Register<0x2c, 16>
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{
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struct Wlen : Bitfield<5,2> {
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enum {
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WORD_LENGTH_8BITS = 3,
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WORD_LENGTH_7BITS = 2,
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WORD_LENGTH_6BITS = 1,
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WORD_LENGTH_5BITS = 0,
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};
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};
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};
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/**
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* Control Register
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*/
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struct Uartcr : public Register<0x30, 16>
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{
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struct Uarten : Bitfield<0,1> { };
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struct Txe : Bitfield<8,1> { };
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struct Rxe : Bitfield<9,1> { };
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};
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/**
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* Interrupt Mask Set/Clear
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*/
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struct Uartimsc : public Register<0x38, 16>
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{
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struct Imsc : Bitfield<0,11> { };
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};
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/**
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* Idle until the device is ready for action
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*/
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void _wait_until_ready() { while (read<Uartfr::Busy>()) ; }
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public:
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/**
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* Constructor
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* \param base Device MMIO base
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* \param clock Device reference clock frequency
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* \param baud_rate Targeted UART baud rate
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*/
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inline Pl011_base(addr_t const base, uint32_t const clock,
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uint32_t const baud_rate);
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/**
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* Send ASCII char 'c' over the UART interface
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*/
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inline void put_char(char const c);
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};
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}
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Genode::Pl011_base::Pl011_base(addr_t const base, uint32_t const clock,
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uint32_t const baud_rate) : Mmio(base)
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{
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write<Uartcr>(Uartcr::Uarten::bits(1) |
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Uartcr::Txe::bits(1) |
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Uartcr::Rxe::bits(1));
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/**
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* We can't print an error or throw C++ exceptions
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* because we must expect both to be uninitialized yet,
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* so its better to hold the program counter in here for debugging
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*/
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if (baud_rate > MAX_BAUD_RATE) while(1) ;
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/**
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* Calculate fractional and integer part of baud rate
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* divisor to initialize IBRD and FBRD
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*/
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uint32_t const adjusted_br = baud_rate << 4;
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double const divisor = (double)clock / adjusted_br;
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Uartibrd::access_t const ibrd = (Uartibrd::access_t)divisor;
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Uartfbrd::access_t const fbrd = (Uartfbrd::access_t)(((divisor - ibrd)
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* 64) + 0.5);
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write<Uartfbrd::Fbrd>(fbrd);
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write<Uartibrd::Ibrd>(ibrd);
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write<Uartlcrh::Wlen>(Uartlcrh::Wlen::WORD_LENGTH_8BITS);
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/**
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* Unmask all interrupts
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*/
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write<Uartimsc::Imsc>(0);
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_wait_until_ready();
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}
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void Genode::Pl011_base::put_char(char const c)
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{
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/* Wait as long as the transmission buffer is full */
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while (read<Uartfr::Txff>()) ;
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/* Auto complete new line commands */
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if (c == ASCII_LINE_FEED) write<Uartdr::Data>(ASCII_CARRIAGE_RETURN);
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/* Transmit character */
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write<Uartdr::Data>(c);
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_wait_until_ready();
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}
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#endif /* _BASE__INCLUDE__DRIVERS__UART__PL011_BASE_H_ */
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@ -0,0 +1,225 @@
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/*
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* \brief Base UART driver for the Texas instruments TL16C750 module
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* \author Martin stein
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* \date 2011-10-17
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE__INCLUDE__DRIVERS__UART__TL16C750_BASE_H_
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#define _BASE__INCLUDE__DRIVERS__UART__TL16C750_BASE_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Genode
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{
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enum {
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ASCII_LINE_FEED = 10,
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ASCII_CARRIAGE_RETURN = 13,
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};
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/**
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* Base driver Texas instruments TL16C750 UART module
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*
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* \detail In contrast to the abilities of the TL16C750, this driver
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* targets only the basic UART functionalities.
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*/
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class Tl16c750_base : public Mmio
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{
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/**
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* Least significant divisor part
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*/
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struct Uart_dll : Register<0x0, 32>
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{
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struct Clock_lsb : Bitfield<0, 8> { };
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};
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/**
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* Transmit holding register
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*/
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struct Uart_thr : Register<0x0, 32>
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{
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struct Thr : Bitfield<0, 8> { };
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};
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/**
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* Most significant divisor part
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*/
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struct Uart_dlh : Register<0x4, 32>
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{
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struct Clock_msb : Bitfield<0, 6> { };
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};
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/**
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* Interrupt enable register
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*/
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struct Uart_ier : Register<0x4, 32>
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{
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struct Rhr_it : Bitfield<0, 1> { };
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struct Thr_it : Bitfield<1, 1> { };
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struct Line_sts_it : Bitfield<2, 1> { };
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struct Modem_sts_it : Bitfield<3, 1> { };
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struct Sleep_mode : Bitfield<4, 1> { };
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struct Xoff_it : Bitfield<5, 1> { };
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struct Rts_it : Bitfield<6, 1> { };
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struct Cts_it : Bitfield<7, 1> { };
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};
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/**
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* FIFO control register
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*/
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struct Uart_fcr : Register<0x8, 32>
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{
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struct Fifo_enable : Bitfield<0, 1> { };
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};
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/**
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* Line control register
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*/
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struct Uart_lcr : Register<0xc, 32>
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{
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struct Char_length : Bitfield<0, 2>
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{
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enum { _8_BIT = 3 };
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};
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struct Nb_stop : Bitfield<2, 1>
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{
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enum { _1_STOP_BIT = 0 };
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};
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struct Parity_en : Bitfield<3, 1> { };
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struct Break_en : Bitfield<6, 1> { };
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struct Div_en : Bitfield<7, 1> { };
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struct Reg_mode : Bitfield<0, 8>
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{
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enum { OPERATIONAL = 0, CONFIG_A = 0x80, CONFIG_B = 0xbf };
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};
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};
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/**
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* Modem control register
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*/
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struct Uart_mcr : Register<0x10, 32>
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{
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struct Tcr_tlr : Bitfield<6, 1> { };
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};
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/**
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* Line status register
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*/
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struct Uart_lsr : Register<0x14, 32>
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{
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struct Tx_fifo_empty : Bitfield<5, 1> { };
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};
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/**
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* Mode definition register 1
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*/
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struct Uart_mdr1 : Register<0x20, 32>
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{
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struct Mode_select : Bitfield<0, 3>
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{
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enum { UART_16X = 0, DISABLED = 7 };
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};
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};
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/**
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* System control register
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*/
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struct Uart_sysc : Register<0x54, 32>
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{
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struct Softreset : Bitfield<1, 1> { };
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};
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/**
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* System status register
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*/
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struct Uart_syss : Register<0x58, 32>
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{
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struct Resetdone : Bitfield<0, 1> { };
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};
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public:
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/**
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* Constructor
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*
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* \param base MMIO base address
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* \param clock Reference clock
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* \param baud_rate Targeted baud rate
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*/
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Tl16c750_base(addr_t const base, unsigned long const clock,
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unsigned long const baud_rate) : Mmio(base)
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{
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/* Reset and disable UART */
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write<Uart_sysc::Softreset>(1);
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while (!read<Uart_syss::Resetdone>()) ;
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write<Uart_mdr1::Mode_select>(Uart_mdr1::Mode_select::DISABLED);
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/* Enable access to 'Uart_fcr' and 'Uart_ier' */
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write<Uart_lcr::Reg_mode>(Uart_lcr::Reg_mode::OPERATIONAL);
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/* Configure FIFOs, we don't use any interrupts or DMA,
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* thus FIFO trigger and DMA configurations are dispensable */
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write<Uart_fcr::Fifo_enable>(1);
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/* Disable interrupts and sleep mode */
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write<Uart_ier>(Uart_ier::Rhr_it::bits(0)
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| Uart_ier::Thr_it::bits(0)
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| Uart_ier::Line_sts_it::bits(0)
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| Uart_ier::Modem_sts_it::bits(0)
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| Uart_ier::Sleep_mode::bits(0)
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| Uart_ier::Xoff_it::bits(0)
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| Uart_ier::Rts_it::bits(0)
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| Uart_ier::Cts_it::bits(0));
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/* Enable access to 'Uart_dlh' and 'Uart_dll' */
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write<Uart_lcr::Reg_mode>(Uart_lcr::Reg_mode::CONFIG_B);
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/* Load the new divisor value (this driver solely uses
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* 'UART_16X' mode )*/
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enum { UART_16X_DIVIDER_LOG2 = 4 };
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unsigned long const adjusted_br = baud_rate << UART_16X_DIVIDER_LOG2;
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double const divisor = (double)clock / adjusted_br;
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unsigned long const divisor_uint = (unsigned long)divisor;
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write<Uart_dll::Clock_lsb>(divisor_uint);
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write<Uart_dlh::Clock_msb>(divisor_uint>>Uart_dll::Clock_lsb::WIDTH);
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/* Configure protocol formatting and thereby return to
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* operational mode */
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write<Uart_lcr>(Uart_lcr::Char_length::bits(Uart_lcr::Char_length::_8_BIT)
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| Uart_lcr::Nb_stop::bits(Uart_lcr::Nb_stop::_1_STOP_BIT)
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| Uart_lcr::Parity_en::bits(0)
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| Uart_lcr::Break_en::bits(0)
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| Uart_lcr::Div_en::bits(0));
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/* Switch to UART mode, we don't use hardware or software flow
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* control, thus according configurations are dispensable*/
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write<Uart_mdr1::Mode_select>(Uart_mdr1::Mode_select::UART_16X);
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}
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/**
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* Transmit ASCII char 'c'
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*/
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void put_char(char const c)
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{
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/* Wait as long as the transmission buffer is full */
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while (!read<Uart_lsr::Tx_fifo_empty>()) ;
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/* Auto complete new line commands */
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if (c == ASCII_LINE_FEED)
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write<Uart_thr::Thr>(ASCII_CARRIAGE_RETURN);
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/* Transmit character */
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write<Uart_thr::Thr>(c);
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}
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};
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}
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#endif /* _BASE__INCLUDE__DRIVERS__UART__TL16C750_BASE_H_ */
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