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Retire Exynos 5 support (fix #3725)

This commit is contained in:
Stefan Kalkowski 2020-04-07 00:42:50 +02:00 committed by Christian Helmuth
parent 941e918b46
commit 0e49336b96
106 changed files with 15 additions and 7551 deletions
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120
repos/base-foc/config/arndale.kernel
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@ -1,120 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# Fiasco configuration
#
CONFIG_HAS_FPU_OPTION=y
CONFIG_HAS_LAZY_FPU=y
CONFIG_HAS_VIRT_OBJ_SPACE_OPTION=y
CONFIG_HAS_SERIAL_OPTION=y
CONFIG_HAS_JDB_DISASM_OPTION=y
CONFIG_HAS_JDB_GZIP_OPTION=y
CONFIG_HAS_MP_OPTION=y
CONFIG_HAS_CPU_VIRT=y
#
# Target configuration
#
# CONFIG_IA32 is not set
# CONFIG_AMD64 is not set
CONFIG_ARM=y
# CONFIG_MIPS is not set
# CONFIG_PF_INTEGRATOR is not set
# CONFIG_PF_REALVIEW is not set
# CONFIG_PF_SUNXI is not set
# CONFIG_PF_BCM283X is not set
# CONFIG_PF_SA1100 is not set
# CONFIG_PF_XSCALE is not set
# CONFIG_PF_ARMADA38X is not set
# CONFIG_PF_KIRKWOOD is not set
# CONFIG_PF_TEGRA is not set
# CONFIG_PF_LAYERSCAPE is not set
# CONFIG_PF_IMX is not set
# CONFIG_PF_ARM_VIRT is not set
# CONFIG_PF_RCAR3 is not set
CONFIG_PF_EXYNOS=y
# CONFIG_PF_S3C2410 is not set
# CONFIG_PF_OMAP is not set
# CONFIG_PF_ZYNQ is not set
# CONFIG_PF_ZYNQMP is not set
CONFIG_BSP_NAME="exynos"
CONFIG_CAN_ARM_CPU_CORTEX_A15=y
CONFIG_ARM_V7=y
CONFIG_ARM_V6PLUS=y
CONFIG_ARM_V7PLUS=y
CONFIG_PF_EXYNOS5=y
CONFIG_CPU_SUSPEND=y
CONFIG_PF_EXYNOS_PKG_IDS=""
# CONFIG_PF_EXYNOS4_4210 is not set
# CONFIG_PF_EXYNOS4_4412 is not set
CONFIG_PF_EXYNOS5_5250=y
# CONFIG_PF_EXYNOS5_5410 is not set
CONFIG_PF_EXYNOS_UART_NATIVE=y
CONFIG_PF_EXYNOS_UART_NR=2
CONFIG_PF_EXYNOS_TIMER_MCT=y
# CONFIG_PF_EXYNOS_TIMER_PWM is not set
# CONFIG_PF_EXYNOS_TIMER_GEN is not set
CONFIG_ABI_VF=y
CONFIG_ARM_CORTEX_A15=y
# CONFIG_CPU_VIRT is not set
CONFIG_FPU=y
CONFIG_LAZY_FPU=y
CONFIG_HAVE_ARM_SECMONIF_NONE=y
CONFIG_HAVE_ARM_SECMONIF_MC=y
# CONFIG_ARM_ALIGNMENT_CHECK is not set
CONFIG_ARM_EM_STD=y
# CONFIG_ARM_EM_NS is not set
# CONFIG_ARM_EM_TZ is not set
# CONFIG_ARM_SMC_USER is not set
# CONFIG_ARM_ENABLE_SWP is not set
# CONFIG_ARM_LPAE is not set
CONFIG_ARM_CPU_ERRATA=y
#
# Kernel options
#
CONFIG_MP=y
CONFIG_MP_MAX_CPUS=4
CONFIG_CONTEXT_4K=y
# CONFIG_FINE_GRAINED_CPUTIME is not set
CONFIG_SCHED_FIXED_PRIO=y
CONFIG_VIRT_OBJ_SPACE=y
#
# Debugging
#
CONFIG_INLINE=y
# CONFIG_NDEBUG is not set
# CONFIG_NO_FRAME_PTR is not set
# CONFIG_STACK_DEPTH is not set
# CONFIG_LIST_ALLOC_SANITY is not set
CONFIG_SERIAL=y
CONFIG_JDB=y
# CONFIG_JDB_LOGGING is not set
# CONFIG_JDB_DISASM is not set
CONFIG_JDB_GZIP=y
# CONFIG_JDB_ACCOUNTING is not set
# CONFIG_WARN_NONE is not set
CONFIG_WARN_WARNING=y
# CONFIG_WARN_ANY is not set
#
# ARM debugging options
#
# CONFIG_VMEM_ALLOC_TEST is not set
# CONFIG_DEBUG_KERNEL_PAGE_FAULTS is not set
#
# Compiling
#
CONFIG_CC="gcc"
CONFIG_CXX="g++"
CONFIG_HOST_CC="gcc"
CONFIG_HOST_CXX="g++"
# CONFIG_MAINTAINER_MODE is not set
CONFIG_LABEL=""
# CONFIG_EXPERIMENTAL is not set
CONFIG_PERF_CNT=y
CONFIG_BIT32=y
CONFIG_WARN_LEVEL=1
CONFIG_XARCH="arm"
CONFIG_ABI="vf"

84
repos/base-foc/config/arndale.user
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@ -1,84 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# L4Re Configuration
#
CONFIG_ARCH_ENABLE_STACK_PROTECTOR=y
# CONFIG_BUILD_ARCH_amd64 is not set
CONFIG_BUILD_ARCH_arm=y
# CONFIG_BUILD_ARCH_arm64 is not set
# CONFIG_BUILD_ARCH_mips is not set
# CONFIG_BUILD_ARCH_ppc32 is not set
# CONFIG_BUILD_ARCH_sparc is not set
# CONFIG_BUILD_ARCH_x86 is not set
CONFIG_BUILD_ARCH="arm"
CONFIG_BUILD_ABI_l4f=y
CONFIG_BUILD_ABI="l4f"
# CONFIG_CPU_ARM_ARMV4 is not set
# CONFIG_CPU_ARM_ARMV4T is not set
# CONFIG_CPU_ARM_ARMV5 is not set
# CONFIG_CPU_ARM_ARMV5T is not set
# CONFIG_CPU_ARM_ARMV5TE is not set
# CONFIG_CPU_ARM_ARMV6 is not set
# CONFIG_CPU_ARM_ARMV6T2 is not set
# CONFIG_CPU_ARM_ARMV6ZK is not set
CONFIG_CPU_ARM_ARMV7A=y
CONFIG_CPU="armv7a"
CONFIG_CPU_ARMV6KPLUS=y
CONFIG_CPU_ARMV6PLUS=y
# CONFIG_PLATFORM_TYPE_exynos4 is not set
# CONFIG_PLATFORM_TYPE_imx35 is not set
# CONFIG_PLATFORM_TYPE_zedboard is not set
# CONFIG_PLATFORM_TYPE_beagleboard is not set
# CONFIG_PLATFORM_TYPE_rv_pbx is not set
CONFIG_PLATFORM_TYPE_exynos5=y
# CONFIG_PLATFORM_TYPE_kirkwood is not set
# CONFIG_PLATFORM_TYPE_ls1012afrdm is not set
# CONFIG_PLATFORM_TYPE_pandaboard is not set
# CONFIG_PLATFORM_TYPE_arm_virt is not set
# CONFIG_PLATFORM_TYPE_tegra2 is not set
# CONFIG_PLATFORM_TYPE_rv is not set
# CONFIG_PLATFORM_TYPE_rv_vexpress_a15 is not set
# CONFIG_PLATFORM_TYPE_cubieboard2 is not set
# CONFIG_PLATFORM_TYPE_omap3_am33xx is not set
# CONFIG_PLATFORM_TYPE_parallella is not set
# CONFIG_PLATFORM_TYPE_rpi_b is not set
# CONFIG_PLATFORM_TYPE_imx21 is not set
# CONFIG_PLATFORM_TYPE_rcar3 is not set
# CONFIG_PLATFORM_TYPE_ls1021atwr is not set
# CONFIG_PLATFORM_TYPE_tegra3 is not set
# CONFIG_PLATFORM_TYPE_imx7 is not set
# CONFIG_PLATFORM_TYPE_imx28 is not set
# CONFIG_PLATFORM_TYPE_omap3evm is not set
# CONFIG_PLATFORM_TYPE_zynqmp is not set
# CONFIG_PLATFORM_TYPE_imx6 is not set
# CONFIG_PLATFORM_TYPE_imx6ul is not set
# CONFIG_PLATFORM_TYPE_armada38x is not set
# CONFIG_PLATFORM_TYPE_omap5 is not set
# CONFIG_PLATFORM_TYPE_rv_vexpress is not set
# CONFIG_PLATFORM_TYPE_imx51 is not set
# CONFIG_PLATFORM_TYPE_rpi_a is not set
# CONFIG_PLATFORM_TYPE_integrator is not set
# CONFIG_PLATFORM_TYPE_custom is not set
CONFIG_PLATFORM_TYPE="exynos5"
CONFIG_DROPS_STDDIR="/path/to/l4re"
CONFIG_DROPS_INSTDIR="/path/to/l4re"
CONFIG_BID_COLORED_PHASES=y
#
# Building
#
CONFIG_YACC="yacc"
CONFIG_LEX="flex"
CONFIG_CTAGS="ctags"
CONFIG_ETAGS="etags"
CONFIG_HAVE_LDSO=y
CONFIG_INT_CPP_NAME_SWITCH=y
CONFIG_INT_LD_NAME_SWITCH=y
# CONFIG_BID_STRIP_PROGS is not set
# CONFIG_BID_GCC_OMIT_FP is not set
CONFIG_BID_GCC_ENABLE_STACK_PROTECTOR=y
# CONFIG_BID_GCC_STACK_PROTECTOR_ALL is not set
CONFIG_BID_GCC_STACK_PROTECTOR=y
# CONFIG_BID_BUILD_DOC is not set
# CONFIG_RELEASE_MODE is not set
CONFIG_MAKECONFS_ADD=""

121
repos/base-foc/config/odroid_x2.kernel
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@ -1,121 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# Fiasco configuration
#
CONFIG_HAS_FPU_OPTION=y
CONFIG_HAS_LAZY_FPU=y
CONFIG_HAS_VIRT_OBJ_SPACE_OPTION=y
CONFIG_HAS_SERIAL_OPTION=y
CONFIG_HAS_JDB_DISASM_OPTION=y
CONFIG_HAS_JDB_GZIP_OPTION=y
CONFIG_HAS_MP_OPTION=y
#
# Target configuration
#
# CONFIG_IA32 is not set
# CONFIG_AMD64 is not set
CONFIG_ARM=y
# CONFIG_MIPS is not set
# CONFIG_PF_INTEGRATOR is not set
# CONFIG_PF_REALVIEW is not set
# CONFIG_PF_SUNXI is not set
# CONFIG_PF_BCM283X is not set
# CONFIG_PF_SA1100 is not set
# CONFIG_PF_XSCALE is not set
# CONFIG_PF_ARMADA38X is not set
# CONFIG_PF_KIRKWOOD is not set
# CONFIG_PF_TEGRA is not set
# CONFIG_PF_LAYERSCAPE is not set
# CONFIG_PF_IMX is not set
# CONFIG_PF_ARM_VIRT is not set
# CONFIG_PF_RCAR3 is not set
CONFIG_PF_EXYNOS=y
# CONFIG_PF_S3C2410 is not set
# CONFIG_PF_OMAP is not set
# CONFIG_PF_ZYNQ is not set
# CONFIG_PF_ZYNQMP is not set
CONFIG_BSP_NAME="exynos"
CONFIG_CAN_ARM_CPU_CORTEX_A9=y
CONFIG_CAN_ARM_CACHE_L2CXX0=y
CONFIG_ARM_V7=y
CONFIG_ARM_V6PLUS=y
CONFIG_ARM_V7PLUS=y
CONFIG_PF_EXYNOS4=y
CONFIG_PF_EXYNOS_PKG_IDS=""
# CONFIG_PF_EXYNOS4_4210 is not set
CONFIG_PF_EXYNOS4_4412=y
# CONFIG_PF_EXYNOS5_5250 is not set
# CONFIG_PF_EXYNOS5_5410 is not set
CONFIG_PF_EXYNOS_UART_NATIVE=y
CONFIG_PF_EXYNOS_UART_NR=1
CONFIG_PF_EXYNOS_TIMER_MCT=y
# CONFIG_PF_EXYNOS_TIMER_MP is not set
# CONFIG_PF_EXYNOS_TIMER_PWM is not set
# CONFIG_PF_EXYNOS_EXTGIC is not set
CONFIG_ABI_VF=y
CONFIG_ARM_CORTEX_A9=y
CONFIG_FPU=y
CONFIG_LAZY_FPU=y
CONFIG_HAVE_ARM_SECMONIF_NONE=y
CONFIG_HAVE_ARM_SECMONIF_MC=y
# CONFIG_ARM_ALIGNMENT_CHECK is not set
# CONFIG_ARM_EM_STD is not set
CONFIG_ARM_EM_NS=y
# CONFIG_ARM_EM_TZ is not set
# CONFIG_ARM_SECMONIF_NONE is not set
CONFIG_ARM_SECMONIF_MC=y
# CONFIG_ARM_SMC_USER is not set
CONFIG_ARM_CACHE_L2CXX0=y
# CONFIG_ARM_ENABLE_SWP is not set
# CONFIG_ARM_CPU_ERRATA is not set
#
# Kernel options
#
CONFIG_MP=y
CONFIG_MP_MAX_CPUS=4
CONFIG_CONTEXT_4K=y
# CONFIG_FINE_GRAINED_CPUTIME is not set
CONFIG_SCHED_FIXED_PRIO=y
CONFIG_VIRT_OBJ_SPACE=y
#
# Debugging
#
CONFIG_INLINE=y
# CONFIG_NDEBUG is not set
CONFIG_NO_FRAME_PTR=y
# CONFIG_STACK_DEPTH is not set
# CONFIG_LIST_ALLOC_SANITY is not set
CONFIG_SERIAL=y
CONFIG_JDB=y
# CONFIG_JDB_LOGGING is not set
# CONFIG_JDB_DISASM is not set
CONFIG_JDB_GZIP=y
# CONFIG_JDB_ACCOUNTING is not set
# CONFIG_WARN_NONE is not set
CONFIG_WARN_WARNING=y
# CONFIG_WARN_ANY is not set
#
# ARM debugging options
#
# CONFIG_VMEM_ALLOC_TEST is not set
# CONFIG_DEBUG_KERNEL_PAGE_FAULTS is not set
#
# Compiling
#
CONFIG_CC="gcc"
CONFIG_CXX="g++"
CONFIG_HOST_CC="gcc"
CONFIG_HOST_CXX="g++"
# CONFIG_MAINTAINER_MODE is not set
CONFIG_LABEL=""
# CONFIG_EXPERIMENTAL is not set
CONFIG_PERF_CNT=y
CONFIG_BIT32=y
CONFIG_WARN_LEVEL=1
CONFIG_XARCH="arm"
CONFIG_ABI="vf"

84
repos/base-foc/config/odroid_x2.user
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@ -1,84 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# L4Re Configuration
#
CONFIG_ARCH_ENABLE_STACK_PROTECTOR=y
# CONFIG_BUILD_ARCH_amd64 is not set
CONFIG_BUILD_ARCH_arm=y
# CONFIG_BUILD_ARCH_arm64 is not set
# CONFIG_BUILD_ARCH_mips is not set
# CONFIG_BUILD_ARCH_ppc32 is not set
# CONFIG_BUILD_ARCH_sparc is not set
# CONFIG_BUILD_ARCH_x86 is not set
CONFIG_BUILD_ARCH="arm"
CONFIG_BUILD_ABI_l4f=y
CONFIG_BUILD_ABI="l4f"
# CONFIG_CPU_ARM_ARMV4 is not set
# CONFIG_CPU_ARM_ARMV4T is not set
# CONFIG_CPU_ARM_ARMV5 is not set
# CONFIG_CPU_ARM_ARMV5T is not set
# CONFIG_CPU_ARM_ARMV5TE is not set
# CONFIG_CPU_ARM_ARMV6 is not set
# CONFIG_CPU_ARM_ARMV6T2 is not set
# CONFIG_CPU_ARM_ARMV6ZK is not set
CONFIG_CPU_ARM_ARMV7A=y
CONFIG_CPU="armv7a"
CONFIG_CPU_ARMV6KPLUS=y
CONFIG_CPU_ARMV6PLUS=y
CONFIG_PLATFORM_TYPE_exynos4=y
# CONFIG_PLATFORM_TYPE_imx35 is not set
# CONFIG_PLATFORM_TYPE_zedboard is not set
# CONFIG_PLATFORM_TYPE_beagleboard is not set
# CONFIG_PLATFORM_TYPE_rv_pbx is not set
# CONFIG_PLATFORM_TYPE_exynos5 is not set
# CONFIG_PLATFORM_TYPE_kirkwood is not set
# CONFIG_PLATFORM_TYPE_ls1012afrdm is not set
# CONFIG_PLATFORM_TYPE_pandaboard is not set
# CONFIG_PLATFORM_TYPE_arm_virt is not set
# CONFIG_PLATFORM_TYPE_tegra2 is not set
# CONFIG_PLATFORM_TYPE_rv is not set
# CONFIG_PLATFORM_TYPE_rv_vexpress_a15 is not set
# CONFIG_PLATFORM_TYPE_cubieboard2 is not set
# CONFIG_PLATFORM_TYPE_omap3_am33xx is not set
# CONFIG_PLATFORM_TYPE_parallella is not set
# CONFIG_PLATFORM_TYPE_rpi_b is not set
# CONFIG_PLATFORM_TYPE_imx21 is not set
# CONFIG_PLATFORM_TYPE_rcar3 is not set
# CONFIG_PLATFORM_TYPE_ls1021atwr is not set
# CONFIG_PLATFORM_TYPE_tegra3 is not set
# CONFIG_PLATFORM_TYPE_imx7 is not set
# CONFIG_PLATFORM_TYPE_imx28 is not set
# CONFIG_PLATFORM_TYPE_omap3evm is not set
# CONFIG_PLATFORM_TYPE_zynqmp is not set
# CONFIG_PLATFORM_TYPE_imx6 is not set
# CONFIG_PLATFORM_TYPE_imx6ul is not set
# CONFIG_PLATFORM_TYPE_armada38x is not set
# CONFIG_PLATFORM_TYPE_omap5 is not set
# CONFIG_PLATFORM_TYPE_rv_vexpress is not set
# CONFIG_PLATFORM_TYPE_imx51 is not set
# CONFIG_PLATFORM_TYPE_rpi_a is not set
# CONFIG_PLATFORM_TYPE_integrator is not set
# CONFIG_PLATFORM_TYPE_custom is not set
CONFIG_PLATFORM_TYPE="exynos4"
CONFIG_DROPS_STDDIR="/path/to/l4re"
CONFIG_DROPS_INSTDIR="/path/to/l4re"
CONFIG_BID_COLORED_PHASES=y
#
# Building
#
CONFIG_YACC="yacc"
CONFIG_LEX="flex"
CONFIG_CTAGS="ctags"
CONFIG_ETAGS="etags"
CONFIG_HAVE_LDSO=y
CONFIG_INT_CPP_NAME_SWITCH=y
CONFIG_INT_LD_NAME_SWITCH=y
# CONFIG_BID_STRIP_PROGS is not set
# CONFIG_BID_GCC_OMIT_FP is not set
CONFIG_BID_GCC_ENABLE_STACK_PROTECTOR=y
# CONFIG_BID_GCC_STACK_PROTECTOR_ALL is not set
CONFIG_BID_GCC_STACK_PROTECTOR=y
# CONFIG_BID_BUILD_DOC is not set
# CONFIG_RELEASE_MODE is not set
CONFIG_MAKECONFS_ADD=""

3
repos/base-foc/lib/mk/spec/arndale/kernel-foc.mk
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@ -1,3 +0,0 @@
KERNEL_CONFIG := $(REP_DIR)/config/arndale.kernel
include $(REP_DIR)/lib/mk/kernel-foc.inc

5
repos/base-foc/lib/mk/spec/arndale/syscall-foc.mk
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@ -1,5 +0,0 @@
L4_CONFIG := $(call select_from_repositories,config/arndale.user)
L4_BIN_DIR := $(LIB_CACHE_DIR)/syscall-foc/arndale-build/bin/arm_armv7a
include $(REP_DIR)/lib/mk/spec/arm/syscall-foc.inc

3
repos/base-foc/lib/mk/spec/odroid_x2/kernel-foc.mk
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@ -1,3 +0,0 @@
KERNEL_CONFIG := $(REP_DIR)/config/odroid_x2.kernel
include $(REP_DIR)/lib/mk/kernel-foc.inc

5
repos/base-foc/lib/mk/spec/odroid_x2/syscall-foc.mk
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@ -1,5 +0,0 @@
L4_CONFIG := $(call select_from_repositories,config/odroid_x2.user)
L4_BIN_DIR := $(LIB_CACHE_DIR)/syscall-foc/odroid_x2-build/bin/arm_armv7a
include $(REP_DIR)/lib/mk/spec/arm/syscall-foc.inc

7
repos/base-foc/recipes/src/base-foc-arndale/README
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@ -1,7 +0,0 @@
This archive contains the Fiasco.OC-specific part of Genode.
It also contains the source code of the Fiasco.OC kernel in the
'src/kernel/foc' directory.
Please note that Fiasco.OC has a license distinct from Genode. Fiasco.OC's
license can be found at 'src/kernel/foc/COPYING-GPL-2'.

3
repos/base-foc/recipes/src/base-foc-arndale/content.mk
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@ -1,3 +0,0 @@
BOARD := arndale
include $(GENODE_DIR)/repos/base-foc/recipes/src/base-foc_content.inc

1
repos/base-foc/recipes/src/base-foc-arndale/hash
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@ -1 +0,0 @@
2020-04-16 8e020d500f28d1cd6c8ffe26e74f1c9ceb715cb2

1
repos/base-foc/recipes/src/base-foc-arndale/used_apis
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@ -1 +0,0 @@
base

18
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-arndale.mk
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@ -1,18 +0,0 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/arndale
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arndale/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s
NR_OF_CPUS = 2
#
# we need more specific compiler hints for some 'special' assembly code
# override -march=armv7-a because it conflicts with -mcpu=cortex-a15
#
CC_MARCH = -mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp
include $(REP_DIR)/lib/mk/bootstrap-hw.inc

10
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-odroid_xu.mk
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@ -1,10 +0,0 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/odroid_xu
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/odroid_xu/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s
include $(REP_DIR)/lib/mk/bootstrap-hw.inc

33
repos/base-hw/lib/mk/spec/arm_v7/core-hw-arndale.mk
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@ -1,33 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-02-09
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/arndale
INC_DIR += $(REP_DIR)/src/core/spec/arm/virtualization
# add C++ sources
SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm/gicv2.cc
SRC_CC += spec/arm/virtualization/gicv2.cc
SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc
SRC_CC += spec/arm/virtualization/platform_services.cc
SRC_CC += spec/arm/virtualization/vm_session_component.cc
SRC_CC += vm_session_common.cc
SRC_CC += vm_session_component.cc
# add assembly sources
SRC_S += spec/arm_v7/virtualization/exception_vector.s
NR_OF_CPUS = 2
#
# we need more specific compiler hints for some 'special' assembly code
# override -march=armv7-a because it conflicts with -mcpu=cortex-a15
#
CC_MARCH = -mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/exynos5/core-hw.inc

16
repos/base-hw/lib/mk/spec/arm_v7/core-hw-odroid_xu.mk
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@ -1,16 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-02-09
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/odroid_xu
# add C++ sources
SRC_CC += spec/arm/gicv2.cc
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += platform_services.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/exynos5/core-hw.inc

14
repos/base-hw/lib/mk/spec/exynos5/core-hw.inc
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@ -1,14 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Martin Stein
# \date 2011-12-16
#
# add include paths
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/exynos5
# add C++ sources
SRC_CC += spec/arm/exynos_mct.cc
# include less specific configuration
include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a15/core-hw.inc

7
repos/base-hw/recipes/src/base-hw-arndale/content.mk
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@ -1,7 +0,0 @@
BOARD = arndale
include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
content: enable_board_spec
enable_board_spec: etc/specs.conf
echo "SPECS += arndale" >> etc/specs.conf

1
repos/base-hw/recipes/src/base-hw-arndale/hash
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@ -1 +0,0 @@
2020-04-16 1e7c44e2b6b3a2a9a687a734f8d7a8772eba1944

2
repos/base-hw/recipes/src/base-hw-arndale/used_apis
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@ -1,2 +0,0 @@
base-hw
base

7
repos/base-hw/recipes/src/base-hw-odroid_xu/content.mk
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@ -1,7 +0,0 @@
BOARD = odroid_xu
include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
content: enable_board_spec
enable_board_spec: etc/specs.conf
echo "SPECS += odroid_xu" >> etc/specs.conf

1
repos/base-hw/recipes/src/base-hw-odroid_xu/hash
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@ -1 +0,0 @@
2020-04-16 bc10b21e3f2785dec9a7b7a19340a031a834eaee

2
repos/base-hw/recipes/src/base-hw-odroid_xu/used_apis
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@ -1,2 +0,0 @@
base-hw
base

28
repos/base-hw/src/bootstrap/spec/arndale/board.h
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@ -1,28 +0,0 @@
/*
* \brief Arndale specific board definitions
* \author Stefan Kalkowski
* \date 2017-04-03
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#include <hw/spec/arm/arndale_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Arndale_board;
using Pic = Hw::Gicv2;
static constexpr bool NON_SECURE = true;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */

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repos/base-hw/src/bootstrap/spec/arndale/cpu.cc
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/*
* \brief CPU-specific initialization code for Arndale
* \author Stefan Kalkowski
* \date 2016-01-07
*/
/*
* Copyright (C) 2016-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core includes */
#include <cpu.h>
#include <translation_table.h>
void Genode::Cpu::init(Genode::Translation_table & table)
{
prepare_nonsecure_world();
prepare_hypervisor(table);
switch_to_supervisor_mode();
}

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repos/base-hw/src/bootstrap/spec/arndale/platform.cc
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/*
* \brief Parts of platform that are specific to Arndale
* \author Martin Stein
* \date 2012-04-27
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <spec/arm/cortex_a7_a15_virtualization.h>
#include <platform.h>
extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
static inline void switch_to_supervisor_mode()
{
using Cpsr = Hw::Arm_cpu::Psr;
Cpsr::access_t cpsr = 0;
Cpsr::M::set(cpsr, Cpsr::M::SVC);
Cpsr::F::set(cpsr, 1);
Cpsr::I::set(cpsr, 1);
asm volatile (
"msr sp_svc, sp \n" /* copy current mode's sp */
"msr lr_svc, lr \n" /* copy current mode's lr */
"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
"msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */
"adr lr, 1f \n" /* load exception return address */
"eret \n" /* exception return */
"1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack));
}
unsigned Bootstrap::Platform::enable_mmu()
{
static volatile bool primary_cpu = true;
static unsigned long timer_freq = 24000000;
/* locally initialize interrupt controller */
::Board::Pic pic { };
volatile unsigned long * mct_control = (unsigned long*) 0x101C0240;
*mct_control = 0x100;
prepare_nonsecure_world(timer_freq);
prepare_hypervisor((addr_t)core_pd->table_base);
switch_to_supervisor_mode();
Cpu::Sctlr::init();
Cpu::Cpsr::init();
/* primary cpu wakes up all others */
if (primary_cpu && NR_OF_CPUS > 1) {
Cpu::invalidate_data_cache();
primary_cpu = false;
Cpu::wake_up_all_cpus(&_start_setup_stack);
}
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
}
void Board::Cpu::wake_up_all_cpus(void * const ip)
{
*(void * volatile *)Board::IRAM_BASE = ip;
asm volatile("dsb; sev;");
}

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repos/base-hw/src/bootstrap/spec/odroid_xu/board.h
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/*
* \brief Odroid XU specific board definitions
* \author Stefan Kalkowski
* \date 2017-04-03
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#include <hw/spec/arm/odroid_xu_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Odroid_xu_board;
using Pic = Hw::Gicv2;
static constexpr bool NON_SECURE = false;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */

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repos/base-hw/src/bootstrap/spec/odroid_xu/platform.cc
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/*
* \brief Parts of platform that are specific to Odroid XU
* \author Martin Stein
* \date 2012-04-27
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE },
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
unsigned Bootstrap::Platform::enable_mmu()
{
/* locally initialize interrupt controller */
::Board::Pic pic { };
Cpu::Sctlr::init();
Cpu::Cpsr::init();
Cpu::invalidate_data_cache();
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return 0;
}

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/*
* \brief Timer driver for core
* \author Stefan Kalkowski
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* core include */
#include <kernel/timer.h>
#include <board.h>
#include <platform.h>
#include <drivers/timer/util.h>
using namespace Genode;
using namespace Kernel;
unsigned Timer::interrupt_id() const
{
switch (_device.cpu_id) {
case 0: return Board::MCT_IRQ_L0;
case 1: return Board::MCT_IRQ_L1;
default: return 0;
}
}
Board::Timer::Timer(unsigned cpu_id)
:
Mmio(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)),
local(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)
+ (cpu_id ? L1 : L0)),
ticks_per_ms(calc_ticks_per_ms(Board::MCT_CLOCK)),
cpu_id(cpu_id)
{
static unsigned initialized = 0;
if (initialized++) return;
Mct_cfg::access_t mct_cfg = 0;
Mct_cfg::Prescaler::set(mct_cfg, PRESCALER);
Mct_cfg::Div_mux::set(mct_cfg, DIV_MUX);
write<Mct_cfg>(mct_cfg);
}
Board::Timer::Local::Local(Genode::addr_t base)
: Mmio(base)
{
write<Int_enb>(Int_enb::Frceie::bits(1));
acked_write<Tcntb, Wstat::Tcntb>(0xffffffff);
acked_write<Frcntb, Wstat::Frcntb>(0xffffffff);
Tcon::access_t tcon = 0;
Tcon::Frc_start::set(tcon, 1);
Tcon::Timer_start::set(tcon, 1);
acked_write<Tcon, Wstat::Tcon>(tcon);
}
void Timer::_start_one_shot(time_t const ticks)
{
using Device = Board::Timer;
_device.local.cnt = _device.local.read<Device::Local::Tcnto>();
_device.local.write<Device::Local::Int_cstat::Frccnt>(1);
_device.local.acked_write<Device::Local::Frcntb,
Device::Local::Wstat::Frcntb>(ticks);
}
time_t Timer::_duration() const
{
using Tcnto = Board::Timer::Local::Tcnto;
unsigned long ret = _device.local.cnt - _device.local.read<Tcnto>();
return ret;
}
time_t Timer::ticks_to_us(time_t const ticks) const {
return timer_ticks_to_us(ticks, _device.ticks_per_ms); }
time_t Timer::us_to_ticks(time_t const us) const {
return (us / 1000) * _device.ticks_per_ms; }
time_t Timer::_max_value() const {
return 0xffffffff; }

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/*
* \brief Timer driver for core
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Kernel OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_
#define _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_
/* Kernel includes */
#include <util/mmio.h>
/* base-hw includes */
#include <kernel/types.h>
namespace Board { class Timer; }
struct Board::Timer : Genode::Mmio
{
enum {
PRESCALER = 1,
DIV_MUX = 0,
};
/**
* MCT configuration
*/
struct Mct_cfg : Register<0x0, 32>
{
struct Prescaler : Bitfield<0, 8> { };
struct Div_mux : Bitfield<8, 3> { };
};
/*****************
** Local timer **
*****************/
enum Local_timer_offset { L0 = 0x300, L1 = 0x400 };
struct Local : Genode::Mmio {
struct Tcntb : Register<0x0, 32> { };
struct Tcnto : Register<0x4, 32> { };
struct Icntb : Register<0x8, 32> { };
struct Icnto : Register<0xc, 32> { };
struct Frcntb : Register<0x10, 32> { };
struct Frcnto : Register<0x14, 32> { };
struct Tcon : Register<0x20, 32>
{
struct Timer_start : Bitfield<0, 1> { };
struct Irq_start : Bitfield<1, 1> { };
struct Irq_type : Bitfield<2, 1> { };
struct Frc_start : Bitfield<3, 1> { };
};
struct Int_cstat : Register<0x30, 32, true>
{
struct Intcnt : Bitfield<0, 1> { };
struct Frccnt : Bitfield<1, 1> { };
};
struct Int_enb : Register<0x34, 32>
{
struct Inteie : Bitfield<0, 1> { };
struct Frceie : Bitfield<1, 1> { };
};
struct Wstat : Register<0x40, 32, true>
{
struct Tcntb : Bitfield<0, 1> { };
struct Icntb : Bitfield<1, 1> { };
struct Frcntb : Bitfield<2, 1> { };
struct Tcon : Bitfield<3, 1> { };
};
Tcnto::access_t cnt = { 0 };
/**
* Write to reg that replies via ack bit and clear ack bit
*/
template <typename DEST, typename ACK>
void acked_write(typename DEST::Register_base::access_t const v)
{
typedef typename DEST::Register_base Dest;
typedef typename ACK::Bitfield_base Ack;
write<Dest>(v);
while (!read<Ack>());
write<Ack>(1);
}
void update_cnt() { cnt = read<Tcnto>(); }
Local(Genode::addr_t base);
};
/**
* Calculate amount of ticks per ms for specific input clock
*
* \param clock input clock
*/
Kernel::time_t static calc_ticks_per_ms(unsigned const clock) {
return clock / (PRESCALER + 1) / (1 << DIV_MUX) / 1000; }
Local local;
unsigned const ticks_per_ms;
unsigned const cpu_id;
Timer(unsigned cpu_id);
};
#endif /* _SRC__CORE__SPEC__ARM__EXYNOS_MCT_H_ */

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/*
* \brief Platform specific services for Arndale
* \brief Platform specific services for ARM with virtualization
* \author Stefan Kalkowski
* \date 2014-07-08
*/

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repos/base-hw/src/core/spec/arndale/board.h
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/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2017-04-27
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ARNDALE__BOARD_H_
#define _CORE__SPEC__ARNDALE__BOARD_H_
#include <spec/arm/virtualization/gicv2.h>
#include <hw/spec/arm/arndale_board.h>
#include <spec/arm/exynos_mct.h>
#include <spec/arm/cpu/vm_state_virtualization.h>
#include <spec/arm/virtualization/board.h>
namespace Kernel { class Cpu; }
namespace Board {
using namespace Hw::Arndale_board;
struct Virtual_local_pic {};
enum { VCPU_MAX = 1 };
}
#endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */

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repos/base-hw/src/core/spec/odroid_xu/board.h
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/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2017-04-27
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ODROID_XU__BOARD_H_
#define _CORE__SPEC__ODROID_XU__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/odroid_xu_board.h>
#include <spec/arm/exynos_mct.h>
namespace Board {
using namespace Hw::Odroid_xu_board;
using Pic = Hw::Gicv2;
}
#endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/arndale_board.h
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/*
* \brief Arndale specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-15
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
#include <drivers/defs/arndale.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/boot_info.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Arndale_board {
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_ */

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/*
* \brief Odroid XU specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
#include <drivers/defs/odroid_xu.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/boot_info.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Odroid_xu_board {
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_ */

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/*
* \brief MMIO and IRQ definitions for the InSignal Arndale 5 board
* \author Martin stein
* \date 2013-01-09
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__ARNDALE_H_
#define _INCLUDE__DRIVERS__DEFS__ARNDALE_H_
/* Genode includes */
#include <drivers/defs/exynos5.h>
namespace Arndale {
using namespace Exynos5;
enum
{
/* clock management unit */
CMU_MMIO_BASE = 0x10010000,
CMU_MMIO_SIZE = 0x24000,
/* power management unit */
PMU_MMIO_BASE = 0x10040000,
PMU_MMIO_SIZE = 0x5000,
/* USB */
USB_HOST20_IRQ = 103,
USB_DRD30_IRQ = 104,
/* UART */
UART_2_CLOCK = 100000000,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__ARNDALE_H_ */

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repos/base/include/drivers/defs/exynos5.h
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/*
* \brief MMIO and IRQ definitions common to Exynos5 SoC
* \author Stefan Kalkowski
* \date 2013-11-25
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <drivers/defs/arm_v7.h>
#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
namespace Exynos5 {
using namespace Arm_v7;
enum {
/* normal RAM */
RAM_0_BASE = 0x40000000,
RAM_0_SIZE = 0x80000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
/* interrupt controller */
IRQ_CONTROLLER_BASE = 0x10480000,
IRQ_CONTROLLER_SIZE = 0x00010000,
IRQ_CONTROLLER_VT_CTRL_BASE = 0x10484000,
IRQ_CONTROLLER_VT_CTRL_SIZE = 0x1000,
IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
/* UART */
UART_2_MMIO_BASE = 0x12C20000,
UART_2_MMIO_SIZE = 0x1000,
UART_2_IRQ = 85,
/* pulse-width-modulation timer */
PWM_MMIO_BASE = 0x12dd0000,
PWM_MMIO_SIZE = 0x1000,
PWM_CLOCK = 66000000,
PWM_IRQ_0 = 68,
/* multicore timer */
MCT_MMIO_BASE = 0x101c0000,
MCT_MMIO_SIZE = 0x1000,
MCT_CLOCK = 24000000,
MCT_IRQ_L0 = 152,
MCT_IRQ_L1 = 153,
/* IRAM */
IRAM_BASE = 0x02020000,
/* SATA/AHCI */
SATA_IRQ = 147,
/* SD card */
SDMMC0_IRQ = 107,
/******************************
** HDMI memory map and irqs **
******************************/
/* Mixer base */
MIXER_BASE = 0x14450000,
/* HDMI base */
HDMI_BASE = 0x14530000,
/* I2C BASE */
I2C_BASE = 0x12ce0000,
/* I2C */
I2C_HDMI_IRQ = 96,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_ */

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repos/base/include/drivers/defs/odroid_x2.h
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/*
* \brief MMIO and IRQ definitions of the Odroid-x2 board
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto López León <humberto@uclv.cu>
* \author Reinier Millo Sánchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__ODROID_X2_H_
#define _INCLUDE__DRIVERS__DEFS__ODROID_X2_H_
namespace Odroid_x2 {
enum
{
/* clock management unit */
CMU_MMIO_BASE = 0x10030000,
CMU_MMIO_SIZE = 0x18000,
/* power management unit */
PMU_MMIO_BASE = 0x10020000,
PMU_MMIO_SIZE = 0x5000, /* TODO Check the region size */
/* UART */
UART_1_MMIO_BASE = 0x13810000,
UART_1_IRQ = 85,
UART_1_CLOCK = 100000000, /* TODO Check SCLK_UART1 */
UART_2_MMIO_BASE = 0x13820000,
UART_2_IRQ = 86,
UART_2_CLOCK = 100000000, /* TODO Check SCLK_UART2 */
MCT_IRQ_L0 = 28,
MCT_IRQ_L1 = 28,
MCT_IRQ_L2 = 28,
MCT_IRQ_L3 = 28,
TIMER_IRQ = 28,
/* USB IRQ */
USB_HOST20_IRQ = 102,
/******************************
** HDMI memory map and irqs **
******************************/
/* Mixer base */
MIXER_BASE = 0x12C10000,
/* HDMI base */
HDMI_BASE = 0x12D00000,
/* IC2 BASE */
I2C_BASE = 0x138E0000,
/* HDMI IRQ */
I2C_HDMI_IRQ = 125,
/* GPIO */
GPIO1_MMIO_BASE = 0x11400000,
GPIO1_MMIO_SIZE = 0x0F88,
GPIO1_IRQ = 79, /* TODO Check the irq number */
GPIO2_MMIO_BASE = 0x11000000,
GPIO2_MMIO_SIZE = 0x0F88,
GPIO2_IRQ = 79, /* TODO Check the irq number */
GPIO3_MMIO_BASE = 0x03860000,
GPIO3_MMIO_SIZE = 0x0F88,
GPIO3_IRQ = 79, /* TODO Check the irq number */
GPIO4_MMIO_BASE = 0x106E0000,
GPIO4_MMIO_SIZE = 0x0F88,
GPIO4_IRQ = 79, /* TODO Check the irq number */
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__ODROID_X2_H_ */

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repos/base/include/drivers/defs/odroid_xu.h
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/*
* \brief MMIO and IRQ definitions for the Odroid XU board
* \author Stefan Kalkowski
* \date 2013-11-25
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__ODROID_XU_H_
#define _INCLUDE__DRIVERS__DEFS__ODROID_XU_H_
/* Genode includes */
#include <drivers/defs/exynos5.h>
namespace Odroid_xu {
using namespace Exynos5;
enum {
/* UART */
UART_2_CLOCK = 62668800,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__ODROID_XU_H_ */

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/*
* \brief Driver for the Exynos UART
* \author Martin stein
* \date 2013-01-09
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__UART__EXYNOS_H_
#define _INCLUDE__DRIVERS__UART__EXYNOS_H_
/* Genode includes */
#include <util/mmio.h>
namespace Genode { class Exynos_uart; }
/**
* Exynos UART driver base
*/
class Genode::Exynos_uart: Mmio
{
protected:
/**
* Line control
*/
struct Ulcon : Register<0x0, 32>
{
struct Word_length : Bitfield<0, 2> { enum { _8_BIT = 3 }; };
struct Stop_bits : Bitfield<2, 1> { enum { _1_BIT = 0 }; };
struct Parity_mode : Bitfield<3, 3> { enum { NONE = 0 }; };
struct Infrared_mode : Bitfield<6, 1> { };
/**
* Initialization value
*/
static access_t init_value()
{
return Word_length::bits(Word_length::_8_BIT) |
Stop_bits::bits(Stop_bits::_1_BIT) |
Parity_mode::bits(Parity_mode::NONE) |
Infrared_mode::bits(0);
}
};
/**
* Control
*/
struct Ucon : Register<0x4, 32>
{
struct Receive_mode : Bitfield<0, 2> { enum { IRQ_POLL = 1 }; };
struct Transmit_mode : Bitfield<2, 2> { enum { IRQ_POLL = 1 }; };
struct Send_brk_signal : Bitfield<4, 1> { };
struct Loop_back_mode : Bitfield<5, 1> { };
struct Rx_err_irq : Bitfield<6, 1> { };
struct Rx_timeout : Bitfield<7, 1> { };
struct Rx_irq_type : Bitfield<8, 1> { enum { LEVEL = 1 }; };
struct Tx_irq_type : Bitfield<9, 1> { enum { LEVEL = 1 }; };
struct Rx_to_dma_susp : Bitfield<10, 1> { };
struct Rx_to_empty_rx : Bitfield<11, 1> { };
struct Rx_to_interval : Bitfield<12, 4> { };
struct Rx_dma_bst_size : Bitfield<16, 3> { };
struct Tx_dma_bst_size : Bitfield<20, 3> { };
/**
* Initialization value
*/
static access_t init_value()
{
return Receive_mode::bits(Receive_mode::IRQ_POLL) |
Transmit_mode::bits(Transmit_mode::IRQ_POLL) |
Rx_timeout::bits(1);
}
};
/**
* FIFO control
*/
struct Ufcon : Register<0x8, 32>
{
struct Fifo_en : Bitfield<0, 1> { };
struct Rx_fifo_rst : Bitfield<1, 1> { };
struct Tx_fifo_rst : Bitfield<2, 1> { };
};
/**
* Modem control
*/
struct Umcon : Register<0xc, 32>
{
struct Send_request : Bitfield<0, 1> { };
struct Modem_irq : Bitfield<3, 1> { };
struct Auto_flow_ctl : Bitfield<4, 1> { };
struct Rts_trigger : Bitfield<5, 3> { };
/**
* Initialization value
*/
static access_t init_value()
{
return Send_request::bits(0) |
Modem_irq::bits(0) |
Auto_flow_ctl::bits(0) |
Rts_trigger::bits(0);
}
};
/**
* FIFO status
*/
struct Ufstat : Register<0x18, 32>
{
struct Rx_fifo_count : Bitfield<0, 8> { };
struct Rx_fifo_full : Bitfield<8, 1> { };
struct Tx_fifo_full : Bitfield<24, 1> { };
};
/**
* Transmit buffer
*/
struct Utxh : Register<0x20, 32>
{
struct Transmit_data : Bitfield<0, 8> { };
};
/**
* Receive buffer
*/
struct Urxh : Register<0x24, 32>
{
struct Receive_data : Bitfield<0, 8> { };
};
/**
* Baud Rate Divisor
*/
struct Ubrdiv : Register<0x28, 32>
{
struct Baud_rate_div : Bitfield<0, 16> { };
};
/**
* Fractional part of Baud Rate Divisor
*/
struct Ufracval : Register<0x2c, 32>
{
struct Baud_rate_frac : Bitfield<0, 4> { };
};
/**
* Interrupt mask register
*/
template <unsigned OFF>
struct Uintx : Register<OFF, 32>
{
struct Rxd : Register<OFF, 32>::template Bitfield<0, 1> { };
struct Error : Register<OFF, 32>::template Bitfield<1, 1> { };
struct Txd : Register<OFF, 32>::template Bitfield<2, 1> { };
struct Modem : Register<OFF, 32>::template Bitfield<3, 1> { };
};
using Uintp = Uintx<0x30>;
using Uintm = Uintx<0x38>;
void _rx_enable()
{
write<Ufcon::Fifo_en>(1);
/* mask all IRQs except receive IRQ */
write<Uintm>(Uintm::Error::bits(1) |
Uintm::Txd::bits(1) |
Uintm::Modem::bits(1));
/* clear pending IRQs */
write<Uintp>(Uintp::Rxd::bits(1) |
Uintp::Error::bits(1) |
Uintp::Txd::bits(1) |
Uintp::Modem::bits(1));
}
bool _rx_avail() {
return (read<Ufstat>() & (Ufstat::Rx_fifo_count::bits(0xff)
| Ufstat::Rx_fifo_full::bits(1))); }
/**
* Return character received via UART
*/
char _rx_char()
{
(void)read<Ufcon>();
char c = read<Urxh::Receive_data>();
/* clear pending RX IRQ */
write<Uintp>(Uintp::Rxd::bits(1));
return c;
}
public:
/**
* Constructor
*
* \param base MMIO base address
* \param clock reference clock
* \param baud_rate targeted baud rate
*/
Exynos_uart(addr_t const base, unsigned const clock,
unsigned const baud_rate) : Mmio(base)
{
/* RX and TX FIFO reset */
write<Ufcon::Rx_fifo_rst>(1);
write<Ufcon::Tx_fifo_rst>(1);
while (read<Ufcon::Rx_fifo_rst>() || read<Ufcon::Tx_fifo_rst>()) ;
/* init control registers */
write<Ulcon>(Ulcon::init_value());
write<Ucon>(Ucon::init_value());
write<Umcon>(Umcon::init_value());
/* apply baud rate */
float const div_val = ((float)clock / (baud_rate * 16)) - 1;
Ubrdiv::access_t const ubrdiv = div_val;
Ufracval::access_t const ufracval =
((float)div_val - ubrdiv) * 16;
write<Ubrdiv::Baud_rate_div>(ubrdiv);
write<Ufracval::Baud_rate_frac>(ufracval);
}
/**
* Print character 'c' through the UART
*/
void put_char(char const c)
{
while (read<Ufstat::Tx_fifo_full>()) ;
write<Utxh::Transmit_data>(c);
}
};
#endif /* _INCLUDE__DRIVERS__UART__EXYNOS_H_ */

6
repos/base/mk/spec/arndale.mk
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@ -1,6 +0,0 @@
SPECS += exynos5
REP_INC_DIR += include/spec/arndale
include $(BASE_DIR)/mk/spec/exynos5.mk

5
repos/base/mk/spec/exynos5.mk
View File

@ -1,5 +0,0 @@
SPECS += arm_v7a framebuffer usb
REP_INC_DIR += include/spec/exynos5
include $(BASE_DIR)/mk/spec/arm_v7a.mk

6
repos/base/mk/spec/odroid_x2.mk
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@ -1,6 +0,0 @@
SPECS += arm_v7a exynos4 usb framebuffer gpio
REP_INC_DIR += include/spec/odroid_x2
REP_INC_DIR += include/spec/exynos4
include $(BASE_DIR)/mk/spec/arm_v7a.mk

6
repos/base/mk/spec/odroid_xu.mk
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@ -1,6 +0,0 @@
SPECS += exynos5
REP_INC_DIR += include/spec/odroid_xu
include $(BASE_DIR)/mk/spec/exynos5.mk

9
repos/base/run/platform_drv.inc
View File

@ -3,10 +3,8 @@ proc have_platform_drv {} {
return 0
}
return [expr [have_spec arndale] \
|| [have_spec imx53] \
return [expr [have_spec imx53] \
|| [have_spec rpi] \
|| [have_spec odroid_x2] \
|| [have_spec x86]]
}
@ -34,11 +32,9 @@ proc need_usb_hid { } {
# Return name of the USB driver binary
#
proc usb_host_drv_binary { } {
if {[have_spec arndale]} { return arndale_usb_host_drv }
if {[have_spec rpi]} { return rpi_usb_host_drv }
if {[have_spec imx6q_sabrelite]} { return imx6q_sabrelite_usb_host_drv }
if {[have_spec imx8q_evk]} { return imx8q_evk_usb_host_drv }
if {[have_spec odroid_x2]} { return odroid_x2_usb_host_drv }
if {[have_spec x86]} { return x86_pc_usb_host_drv }
return no_usb_drv_available
}
@ -68,7 +64,6 @@ proc gpio_drv { } {
if {[have_spec rpi]} { return rpi_gpio_drv }
if {[have_spec imx53]} { return imx53_gpio_drv }
if {[have_spec imx6]} { return imx6_gpio_drv }
if {[have_spec exynos4]} { return exynos4_gpio_drv }
return no_gpio_drv_available
}
@ -94,9 +89,7 @@ proc append_platform_drv_build_components {} {
}
proc platform_drv_binary {} {
if {[have_spec arndale] } { return arndale_platform_drv }
if {[have_spec imx53] } { return imx53_platform_drv }
if {[have_spec odroid_x2]} { return odroid_x2_platform_drv }
if {[have_spec rpi] } { return rpi_platform_drv }
if {[have_spec x86] } { return platform_drv }
return no_platform_drv_available

1
repos/dde_linux/recipes/src/usb_drv/used_apis
View File

@ -3,7 +3,6 @@ os
nic_session
usb_session
gpio_session
regulator_session
input_session
block_session
platform_session

1
repos/dde_linux/recipes/src/usb_host_drv/used_apis
View File

@ -2,7 +2,6 @@ base
os
usb_session
gpio_session
regulator_session
platform_session
timer_session
report_session

29
repos/dde_linux/src/drivers/usb/include/spec/odroid_x2/usb_masks.h
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@ -1,29 +0,0 @@
/*
* \brief USB registers masks for Odroid-x2
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopez Leon <humberto@uclv.cu>
* \author Reinir Millo Sanchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is distributed under the terms of the GNU General Public License
* version 2.
*/
#ifndef _USB_MASKS_H_
#define _USB_MASKS_H_
enum {
PHY0_NORMAL_MASK = 0x39 << 0,
PHY0_SWRST_MASK = 0x7 << 0,
PHY1_STD_NORMAL_MASK = 0x7 << 6,
EXYNOS4X12_HSIC0_NORMAL_MASK = 0x7 << 9,
EXYNOS4X12_HSIC1_NORMAL_MASK = 0x7 << 12,
EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK = 0xf << 7,
EXYNOS4X12_PHY1_SWRST_MASK = 0xf << 3,
};
#endif /* _USB_MASKS_H_ */

356
repos/dde_linux/src/drivers/usb/spec/arndale/platform.cc
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@ -1,356 +0,0 @@
/*
* \brief EHCI for Arndale initializaion code
* \author Sebastian Sumpf
* \date 2013-02-20
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is distributed under the terms of the GNU General Public License
* version 2.
*/
/* Genode */
#include <drivers/defs/arndale.h>
#include <base/attached_io_mem_dataspace.h>
#include <io_mem_session/connection.h>
#include <regulator_session/connection.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
/* Emulation */
#include <lx_emul.h>
#include <platform.h>
using namespace Genode;
enum {
EHCI_BASE = 0x12110000,
DWC3_BASE = 0x12000000,
DWC3_PHY_BASE = 0x12100000,
GPIO_BASE = 0x11400000,
EHCI_IRQ = Arndale::USB_HOST20_IRQ,
DWC3_IRQ = Arndale::USB_DRD30_IRQ,
};
static resource _ehci[] =
{
{ EHCI_BASE, EHCI_BASE + 0xfff, "ehci", IORESOURCE_MEM },
{ EHCI_IRQ, EHCI_IRQ, "ehci-irq", IORESOURCE_IRQ },
};
static resource _dwc3[] =
{
{ DWC3_BASE, DWC3_BASE + 0xcfff, "dwc3", IORESOURCE_MEM },
{ DWC3_IRQ, DWC3_IRQ, "dwc3-irq", IORESOURCE_IRQ },
};
/**
* EHCI controller
*/
struct Ehci : Genode::Mmio
{
Ehci(addr_t const mmio_base) : Mmio(mmio_base)
{
write<Cmd>(0);
/* reset */
write<Cmd::Reset>(1);
while(read<Cmd::Reset>())
msleep(1);
}
struct Cmd : Register<0x10, 32>
{
struct Reset : Bitfield<1, 1> { };
};
};
/**
* Gpio handling
*/
struct Gpio_bank {
unsigned con;
unsigned dat;
};
static inline
unsigned con_mask(unsigned val) { return 0xf << ((val) << 2); }
static inline
unsigned con_sfr(unsigned x, unsigned v) { return (v) << ((x) << 2); }
static void gpio_cfg_pin(Gpio_bank *bank, int gpio, int cfg)
{
unsigned int value;
value = readl(&bank->con);
value &= ~con_mask(gpio);
value |= con_sfr(gpio, cfg);
writel(value, &bank->con);
}
static void gpio_direction_output(Gpio_bank *bank, int gpio, int en)
{
unsigned int value;
enum { GPIO_OUTPUT = 0x1 };
gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
value = readl(&bank->dat);
value &= ~(0x1 << gpio);
if (en)
value |= 0x1 << gpio;
writel(value, &bank->dat);
}
static void arndale_ehci_init(Genode::Env &env)
{
enum Gpio_offset { D1 = 0x180, X3 = 0xc60 };
/* enable USB3 clock and power up */
static Regulator::Connection reg_clk(env, Regulator::CLK_USB20);
reg_clk.state(true);
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB20);
reg_pwr.state(true);
/* reset hub via GPIO */
Io_mem_connection io_gpio(env, GPIO_BASE, 0x1000);
addr_t gpio_base = (addr_t)env.rm().attach(io_gpio.dataspace());
Gpio_bank *d1 = reinterpret_cast<Gpio_bank *>(gpio_base + D1);
Gpio_bank *x3 = reinterpret_cast<Gpio_bank *>(gpio_base + X3);
/* hub reset */
gpio_direction_output(x3, 5, 0);
/* hub connect */
gpio_direction_output(d1, 7, 0);
gpio_direction_output(x3, 5, 1);
gpio_direction_output(d1, 7, 1);
env.rm().detach(gpio_base);
/* reset ehci controller */
Io_mem_connection io_ehci(env, EHCI_BASE, 0x1000);
addr_t ehci_base = (addr_t)env.rm().attach(io_ehci.dataspace());
Ehci ehci(ehci_base);
env.rm().detach(ehci_base);
}
struct Phy_usb3 : Genode::Mmio
{
struct Link_system : Register<0x4, 32>
{
struct Fladj : Bitfield<1, 6> { };
struct Ehci_version_control : Bitfield<27, 1> { };
};
struct Phy_utmi : Register<0x8, 32> { };
struct Phy_clk_rst : Register<0x10, 32>
{
struct Common_onn : Bitfield<0, 1> { };
struct Port_reset : Bitfield<1, 1> { };
struct Ref_clk_sel : Bitfield<2, 2> { };
struct Retenablen : Bitfield<4, 1> { };
struct Fsel : Bitfield<5, 6> { };
struct Mpll_mult : Bitfield<11, 7> { };
struct Ref_ssp_en : Bitfield<19, 1> { };
struct Ssc_en : Bitfield<20, 1> { };
struct Ssc_ref_clk_sel : Bitfield<23, 8> { };
};
struct Phy_reg0 : Register<0x14, 32> { };
struct Phy_param0 : Register<0x1c, 32>
{
struct Loss_level : Bitfield<26, 5> { };
struct Ref_use_pad : Bitfield<31, 1> { };
};
struct Phy_param1 : Register<0x20, 32>
{
struct Pcs_txdeemph : Bitfield<0, 5> { };
};
struct Phy_test : Register<0x28, 32>
{
struct Power_down_ssb_hsb : Bitfield<2, 2> { };
};
struct Phy_batchg : Register<0x30, 32>
{
struct Utmi_clksel : Bitfield<2, 1> { };
};
struct Phy_resume : Register<0x34, 32> { };
Phy_usb3 (Genode::Env &env, addr_t const base) : Mmio(base)
{
Timer::Connection timer(env);
/* reset */
write<Phy_reg0>(0);
/* clock source */
write<Phy_param0::Ref_use_pad>(0);
/* set Loss-of-Signal Detector sensitivity */
write<Phy_param0::Loss_level>(0x9);
write<Phy_resume>(0);
/*
* Setting the Frame length Adj value[6:1] to default 0x20
* See xHCI 1.0 spec, 5.2.4
*/
write<Link_system::Ehci_version_control>(1);
write<Link_system::Fladj>(0x20);
/* set Tx De-Emphasis level */
write<Phy_param1::Pcs_txdeemph>(0x1c);
/* set clock */
write<Phy_batchg::Utmi_clksel>(1);
/* PHYTEST POWERDOWN Control */
write<Phy_test::Power_down_ssb_hsb>(0);
/* UTMI power */
enum { OTG_DISABLE = (1 << 6) };
write<Phy_utmi>(OTG_DISABLE);
/* setup clock */
Phy_clk_rst::access_t clk = 0;
/*
* Use same reference clock for high speed
* as for super speed
*/
Phy_clk_rst::Ref_clk_sel::set(clk, 0x2);
/* 24 MHz */
Phy_clk_rst::Fsel::set(clk, 0x2a);
Phy_clk_rst::Mpll_mult::set(clk, 0x68);
Phy_clk_rst::Ssc_ref_clk_sel::set(clk, 0x88);
/* port reset */
Phy_clk_rst::Port_reset::set(clk, 1);
/* digital power supply in normal operating mode */
Phy_clk_rst::Retenablen::set(clk, 1);
/* enable ref clock for SS function */
Phy_clk_rst::Ref_ssp_en::set(clk, 1);
/* enable spread spectrum */
Phy_clk_rst::Ssc_en::set(clk, 1);
/* power down HS Bias and PLL blocks in suspend mode */
Phy_clk_rst::Common_onn::set(clk, 1);
write<Phy_clk_rst>(clk);
timer.usleep(10);
write<Phy_clk_rst::Port_reset>(0);
}
};
static void arndale_xhci_init(Genode::Env &env)
{
/* enable USB3 clock and power up */
static Regulator::Connection reg_clk(env, Regulator::CLK_USB30);
reg_clk.state(true);
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB30);
reg_pwr.state(true);
/* setup PHY */
Attached_io_mem_dataspace io_phy(env, DWC3_PHY_BASE, 0x1000);
Phy_usb3 phy(env, (addr_t)io_phy.local_addr<addr_t>());
}
extern "C" void module_ehci_exynos_init();
extern "C" void module_usbnet_init();
extern "C" void module_asix_driver_init();
extern "C" void module_ax88179_178a_driver_init();
extern "C" void module_dwc3_driver_init();
extern "C" void module_xhci_plat_init();
extern "C" void module_asix_init();
void ehci_setup(Services *services)
{
if (services->nic)
module_asix_driver_init();
/* register EHCI controller */
module_ehci_exynos_init();
/* setup controller */
arndale_ehci_init(services->env);
/* setup EHCI-controller platform device */
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
pdev->name = (char *)"exynos-ehci";
pdev->id = 0;
pdev->num_resources = 2;
pdev->resource = _ehci;
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
static u64 dma_mask = ~(u64)0;
pdev->dev.dma_mask = &dma_mask;
pdev->dev.coherent_dma_mask = ~0;
platform_device_register(pdev);
}
void xhci_setup(Services *services)
{
if (services->nic)
module_ax88179_178a_driver_init();
module_dwc3_driver_init();
module_xhci_plat_init();
arndale_xhci_init(services->env);
/* setup DWC3-controller platform device */
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
pdev->name = (char *)"dwc3";
pdev->id = 0;
pdev->num_resources = 2;
pdev->resource = _dwc3;
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
static u64 dma_mask = ~(u64)0;
pdev->dev.dma_mask = &dma_mask;
pdev->dev.coherent_dma_mask = ~0;
platform_device_register(pdev);
}
void platform_hcd_init(Genode::Env &, Services *services)
{
/* register network */
if (services->nic)
module_usbnet_init();
if (services->ehci)
ehci_setup(services);
if (services->xhci)
xhci_setup(services);
}

1
repos/dde_linux/src/drivers/usb/spec/arndale/regulator/consts.h
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@ -1 +0,0 @@
#include <spec/exynos5/regulator/consts.h>

22
repos/dde_linux/src/drivers/usb/spec/arndale/target.mk
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@ -1,22 +0,0 @@
TARGET = arndale_usb_drv
REQUIRES = arm_v7
SRC_C += $(addprefix net/usb/, usbnet.c asix_devices.c asix_common.c ax88172a.c \
ax88179_178a.c)
SRC_C += usb/host/ehci-exynos.c
include $(REP_DIR)/src/drivers/usb/xhci.inc
include $(REP_DIR)/src/drivers/usb/spec/arm_v7/target.inc
CC_OPT += -DCONFIG_USB_EHCI_TT_NEWSCHED -DCONFIG_USB_DWC3_HOST=1 \
-DCONFIG_USB_DWC3_GADGET=0 -DCONFIG_USB_OTG_UTILS -DCONFIG_USB_XHCI_PLATFORM -DDWC3_QUIRK
INC_DIR += $(LX_CONTRIB_DIR)/arch/arm/plat-samsung/include
SRC_CC += platform.cc
#DWC3
SRC_C += $(addprefix usb/dwc3/, dwc3-exynos.c host.c core.c)
#XHCI
SRC_C += usb/host/xhci-plat.c
vpath platform.cc $(LIB_DIR)/spec/arndale

216
repos/dde_linux/src/drivers/usb/spec/odroid_x2/platform.cc
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@ -1,216 +0,0 @@
/*
* \brief EHCI for Odroid-x2 initializaion code
* \author Sebastian Sumpf
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopez Leon <humberto@uclv.cu>
* \author Reinir Millo Sanchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is distributed under the terms of the GNU General Public License
* version 2.
*/
/* Genode */
#include <drivers/defs/odroid_x2.h>
#include <base/attached_io_mem_dataspace.h>
#include <io_mem_session/connection.h>
#include <regulator_session/connection.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
#include <gpio_session/connection.h>
/* Emulation */
#include <lx_emul.h>
#include <platform.h>
#include <usb_masks.h>
using namespace Genode;
enum {
/*The EHCI base is taken from linux kernel */
EHCI_BASE = 0x12580000,
GPIO_BASE = 0x11000000,
USBOTG = 0x125B0000,
EHCI_IRQ = Odroid_x2::USB_HOST20_IRQ,
};
static resource _ehci[] =
{
{ EHCI_BASE, EHCI_BASE + 0xfff, "ehci", IORESOURCE_MEM },
{ EHCI_IRQ, EHCI_IRQ, "ehci-irq", IORESOURCE_IRQ },
};
/**
* EHCI controller
*/
struct Ehci : Genode::Mmio
{
Ehci(addr_t const mmio_base) : Mmio(mmio_base)
{
write<Cmd>(0);
/* reset */
write<Cmd::Reset>(1);
while(read<Cmd::Reset>())
msleep(1);
}
struct Cmd : Register<0x10, 32>
{
struct Reset : Bitfield<1, 1> { };
};
};
/**
* USB OTG handling
*/
struct Usb_Otg : Genode::Mmio
{
Usb_Otg(Genode::Env &env, Genode::addr_t base):Genode::Mmio (base)
{
Timer::Connection timer(env);
unsigned int rstcon_mask = 0;
unsigned int phyclk_mask = 5;
unsigned int phypwr_mask = 0;
/*set the clock of device*/
write<Phyclk>(phyclk_mask);
rstcon_mask= read<Phyclk>();
/* set to normal of Device */
phypwr_mask= read<Phypwr>() & ~PHY0_NORMAL_MASK;
write<Phypwr>(phypwr_mask);
/* set to normal of Host */
phypwr_mask=read<Phypwr>();
phypwr_mask &= ~(PHY1_STD_NORMAL_MASK
|EXYNOS4X12_HSIC0_NORMAL_MASK
|EXYNOS4X12_HSIC1_NORMAL_MASK);
write<Phypwr>(phypwr_mask);
/* reset both PHY and Link of Device */
rstcon_mask = read<Rstcon>() | PHY0_SWRST_MASK;
write<Rstcon>(rstcon_mask);
timer.usleep(10);
rstcon_mask &= ~PHY0_SWRST_MASK;
write<Rstcon>(rstcon_mask);
/* reset both PHY and Link of Host */
rstcon_mask = read<Rstcon>()
|EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
|EXYNOS4X12_PHY1_SWRST_MASK;
write<Rstcon>(rstcon_mask);
timer.usleep(10);
rstcon_mask &= ~(EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
|EXYNOS4X12_PHY1_SWRST_MASK);
write<Rstcon>(rstcon_mask);
timer.usleep(10);
}
struct Phypwr : Register <0x0,32>{};
struct Phyclk : Register <0x4,32>{};
struct Rstcon : Register <0x8,32>{};
};
static void clock_pwr_init(Env &env)
{
/* enable USB2 clock and power up */
static Regulator::Connection reg_clk(env, Regulator::CLK_USB20);
reg_clk.state(true);
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB20);
reg_pwr.state(true);
}
static void usb_phy_init(Genode::Env &env)
{
Io_mem_connection io_usbotg(env, USBOTG, 0x1000);
addr_t usbotg_base = (addr_t)env.rm().attach(io_usbotg.dataspace());
Usb_Otg usbotg(env, usbotg_base);
env.rm().detach(usbotg_base);
}
static void odroidx2_ehci_init(Genode::Env &env)
{
clock_pwr_init(env);
usb_phy_init(env);
/* reset hub via GPIO */
enum { X30 = 294, X34 = 298, X35 = 299 };
Gpio::Connection gpio_x30(env, X30);
Gpio::Connection gpio_x34(env, X34);
Gpio::Connection gpio_x35(env, X35);
/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
gpio_x30.write(true);
/* Disconnect, Reset, Connect */
gpio_x34.write(false);
gpio_x35.write(false);
gpio_x35.write(true);
gpio_x34.write(true);
/* reset ehci controller */
Io_mem_connection io_ehci(env, EHCI_BASE, 0x1000);
addr_t ehci_base = (addr_t)env.rm().attach(io_ehci.dataspace());
Ehci ehci(ehci_base);
env.rm().detach(ehci_base);
}
extern "C" void module_ehci_exynos_init();
extern "C" int module_usbnet_init();
extern "C" int module_smsc95xx_driver_init();
void ehci_setup(Services *services)
{
/* register network */
if (services->nic){
module_usbnet_init();
module_smsc95xx_driver_init();
}
/* register EHCI controller */
module_ehci_exynos_init();
/* setup controller */
odroidx2_ehci_init(services->env);
/* setup EHCI-controller platform device */
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
pdev->name = (char *)"exynos-ehci";
pdev->id = 0;
pdev->num_resources = 2;
pdev->resource = _ehci;
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
static u64 dma_mask = ~(u64)0;
pdev->dev.dma_mask = &dma_mask;
pdev->dev.coherent_dma_mask = ~0;
platform_device_register(pdev);
}
void platform_hcd_init(Genode::Env &, Services *services)
{
/* register network */
if (services->nic){
module_usbnet_init();
module_smsc95xx_driver_init();
}
/* register ehci */
if (services->ehci)
ehci_setup(services);
}

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repos/dde_linux/src/drivers/usb/spec/odroid_x2/regulator/consts.h
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@ -1 +0,0 @@
#include <spec/exynos4/regulator/consts.h>

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repos/dde_linux/src/drivers/usb/spec/odroid_x2/target.mk
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@ -1,17 +0,0 @@
TARGET = odroid_x2_usb_drv
REQUIRES = arm_v7
SRC_C += $(addprefix net/usb/, usbnet.c smsc95xx.c)
SRC_C += usb/host/ehci-exynos.c
include $(REP_DIR)/src/drivers/usb/spec/arm_v7/target.inc
CC_OPT += -DCONFIG_USB_EHCI_TT_NEWSCHED \
-DCONFIG_USB_OTG_UTILS
SRC_CC += platform.cc
INC_DIR += $(LIB_INC_DIR)/spec/odroid_x2
vpath platform.cc $(LIB_DIR)/spec/odroid_x2

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repos/dde_linux/src/drivers/usb_host/spec/arndale/platform.cc
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@ -1,340 +0,0 @@
/*
* \brief EHCI for Arndale initialization code
* \author Sebastian Sumpf
* \date 2013-02-20
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is distributed under the terms of the GNU General Public License
* version 2.
*/
/* Genode */
#include <drivers/defs/arndale.h>
#include <base/attached_io_mem_dataspace.h>
#include <io_mem_session/connection.h>
#include <regulator/consts.h>
#include <regulator_session/connection.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
/* Emulation */
#include <lx_emul.h>
#include <platform.h>
using namespace Genode;
enum {
EHCI_BASE = 0x12110000,
DWC3_BASE = 0x12000000,
DWC3_PHY_BASE = 0x12100000,
GPIO_BASE = 0x11400000,
EHCI_IRQ = Arndale::USB_HOST20_IRQ,
DWC3_IRQ = Arndale::USB_DRD30_IRQ,
};
static resource _ehci[] =
{
{ EHCI_BASE, EHCI_BASE + 0xfff, "ehci", IORESOURCE_MEM },
{ EHCI_IRQ, EHCI_IRQ, "ehci-irq", IORESOURCE_IRQ },
};
static resource _dwc3[] =
{
{ DWC3_BASE, DWC3_BASE + 0xcfff, "dwc3", IORESOURCE_MEM },
{ DWC3_IRQ, DWC3_IRQ, "dwc3-irq", IORESOURCE_IRQ },
};
/**
* EHCI controller
*/
struct Ehci : Genode::Mmio
{
Ehci(addr_t const mmio_base) : Mmio(mmio_base)
{
write<Cmd>(0);
/* reset */
write<Cmd::Reset>(1);
while(read<Cmd::Reset>())
msleep(1);
}
struct Cmd : Register<0x10, 32>
{
struct Reset : Bitfield<1, 1> { };
};
};
/**
* Gpio handling
*/
struct Gpio_bank {
unsigned con;
unsigned dat;
};
static inline
unsigned con_mask(unsigned val) { return 0xf << ((val) << 2); }
static inline
unsigned con_sfr(unsigned x, unsigned v) { return (v) << ((x) << 2); }
static void gpio_cfg_pin(Gpio_bank *bank, int gpio, int cfg)
{
unsigned int value;
value = readl(&bank->con);
value &= ~con_mask(gpio);
value |= con_sfr(gpio, cfg);
writel(value, &bank->con);
}
static void gpio_direction_output(Gpio_bank *bank, int gpio, int en)
{
unsigned int value;
enum { GPIO_OUTPUT = 0x1 };
gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
value = readl(&bank->dat);
value &= ~(0x1 << gpio);
if (en)
value |= 0x1 << gpio;
writel(value, &bank->dat);
}
static void arndale_ehci_init(Genode::Env &env)
{
enum Gpio_offset { D1 = 0x180, X3 = 0xc60 };
/* enable USB3 clock and power up */
static Regulator::Connection reg_clk(env, Regulator::CLK_USB20);
reg_clk.state(true);
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB20);
reg_pwr.state(true);
/* reset hub via GPIO */
Io_mem_connection io_gpio(env, GPIO_BASE, 0x1000);
addr_t gpio_base = (addr_t)env.rm().attach(io_gpio.dataspace());
Gpio_bank *d1 = reinterpret_cast<Gpio_bank *>(gpio_base + D1);
Gpio_bank *x3 = reinterpret_cast<Gpio_bank *>(gpio_base + X3);
/* hub reset */
gpio_direction_output(x3, 5, 0);
/* hub connect */
gpio_direction_output(d1, 7, 0);
gpio_direction_output(x3, 5, 1);
gpio_direction_output(d1, 7, 1);
env.rm().detach(gpio_base);
/* reset ehci controller */
Io_mem_connection io_ehci(env, EHCI_BASE, 0x1000);
addr_t ehci_base = (addr_t)env.rm().attach(io_ehci.dataspace());
Ehci ehci(ehci_base);
env.rm().detach(ehci_base);
}
struct Phy_usb3 : Genode::Mmio
{
struct Link_system : Register<0x4, 32>
{
struct Fladj : Bitfield<1, 6> { };
struct Ehci_version_control : Bitfield<27, 1> { };
};
struct Phy_utmi : Register<0x8, 32> { };
struct Phy_clk_rst : Register<0x10, 32>
{
struct Common_onn : Bitfield<0, 1> { };
struct Port_reset : Bitfield<1, 1> { };
struct Ref_clk_sel : Bitfield<2, 2> { };
struct Retenablen : Bitfield<4, 1> { };
struct Fsel : Bitfield<5, 6> { };
struct Mpll_mult : Bitfield<11, 7> { };
struct Ref_ssp_en : Bitfield<19, 1> { };
struct Ssc_en : Bitfield<20, 1> { };
struct Ssc_ref_clk_sel : Bitfield<23, 8> { };
};
struct Phy_reg0 : Register<0x14, 32> { };
struct Phy_param0 : Register<0x1c, 32>
{
struct Loss_level : Bitfield<26, 5> { };
struct Ref_use_pad : Bitfield<31, 1> { };
};
struct Phy_param1 : Register<0x20, 32>
{
struct Pcs_txdeemph : Bitfield<0, 5> { };
};
struct Phy_test : Register<0x28, 32>
{
struct Power_down_ssb_hsb : Bitfield<2, 2> { };
};
struct Phy_batchg : Register<0x30, 32>
{
struct Utmi_clksel : Bitfield<2, 1> { };
};
struct Phy_resume : Register<0x34, 32> { };
Phy_usb3 (Genode::Env & env, addr_t const base) : Mmio(base)
{
Timer::Connection timer(env);
/* reset */
write<Phy_reg0>(0);
/* clock source */
write<Phy_param0::Ref_use_pad>(0);
/* set Loss-of-Signal Detector sensitivity */
write<Phy_param0::Loss_level>(0x9);
write<Phy_resume>(0);
/*
* Setting the Frame length Adj value[6:1] to default 0x20
* See xHCI 1.0 spec, 5.2.4
*/
write<Link_system::Ehci_version_control>(1);
write<Link_system::Fladj>(0x20);
/* set Tx De-Emphasis level */
write<Phy_param1::Pcs_txdeemph>(0x1c);
/* set clock */
write<Phy_batchg::Utmi_clksel>(1);
/* PHYTEST POWERDOWN Control */
write<Phy_test::Power_down_ssb_hsb>(0);
/* UTMI power */
enum { OTG_DISABLE = (1 << 6) };
write<Phy_utmi>(OTG_DISABLE);
/* setup clock */
Phy_clk_rst::access_t clk = 0;
/*
* Use same reference clock for high speed
* as for super speed
*/
Phy_clk_rst::Ref_clk_sel::set(clk, 0x2);
/* 24 MHz */
Phy_clk_rst::Fsel::set(clk, 0x2a);
Phy_clk_rst::Mpll_mult::set(clk, 0x68);
Phy_clk_rst::Ssc_ref_clk_sel::set(clk, 0x88);
/* port reset */
Phy_clk_rst::Port_reset::set(clk, 1);
/* digital power supply in normal operating mode */
Phy_clk_rst::Retenablen::set(clk, 1);
/* enable ref clock for SS function */
Phy_clk_rst::Ref_ssp_en::set(clk, 1);
/* enable spread spectrum */
Phy_clk_rst::Ssc_en::set(clk, 1);
/* power down HS Bias and PLL blocks in suspend mode */
Phy_clk_rst::Common_onn::set(clk, 1);
write<Phy_clk_rst>(clk);
timer.usleep(10);
write<Phy_clk_rst::Port_reset>(0);
}
};
static void arndale_xhci_init(Genode::Env &env)
{
/* enable USB3 clock and power up */
static Regulator::Connection reg_clk(env, Regulator::CLK_USB30);
reg_clk.state(true);
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB30);
reg_pwr.state(true);
/* setup PHY */
Attached_io_mem_dataspace io_phy(env, DWC3_PHY_BASE, 0x1000);
Phy_usb3 phy(env, (addr_t)io_phy.local_addr<addr_t>());
}
extern "C" void module_ehci_exynos_init();
extern "C" void module_dwc3_driver_init();
extern "C" void module_xhci_plat_init();
void ehci_setup(Services *services)
{
/* register EHCI controller */
module_ehci_exynos_init();
/* setup controller */
arndale_ehci_init(services->env);
/* setup EHCI-controller platform device */
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
pdev->name = (char *)"exynos-ehci";
pdev->id = 0;
pdev->num_resources = 2;
pdev->resource = _ehci;
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
static u64 dma_mask = ~(u64)0;
pdev->dev.dma_mask = &dma_mask;
pdev->dev.coherent_dma_mask = ~0;
platform_device_register(pdev);
}
void xhci_setup(Services *services)
{
module_dwc3_driver_init();
module_xhci_plat_init();
arndale_xhci_init(services->env);
/* setup DWC3-controller platform device */
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
pdev->name = (char *)"dwc3";
pdev->id = 0;
pdev->num_resources = 2;
pdev->resource = _dwc3;
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
static u64 dma_mask = ~(u64)0;
pdev->dev.dma_mask = &dma_mask;
pdev->dev.coherent_dma_mask = ~0;
platform_device_register(pdev);
}
void platform_hcd_init(Genode::Env &, Services *services)
{
ehci_setup(services);
xhci_setup(services);
}

1
repos/dde_linux/src/drivers/usb_host/spec/arndale/regulator/consts.h
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@ -1 +0,0 @@
#include <spec/exynos5/regulator/consts.h>

22
repos/dde_linux/src/drivers/usb_host/spec/arndale/target.mk
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@ -1,22 +0,0 @@
include $(REP_DIR)/src/drivers/usb_host/target.inc
TARGET = arndale_usb_host_drv
REQUIRES = arm_v7
INC_DIR += $(REP_DIR)/src/drivers/usb_host/spec/arm
INC_DIR += $(REP_DIR)/src/include/spec/arm
SRC_CC += spec/arm/platform.cc
SRC_CC += spec/arndale/platform.cc
SRC_C += usb/dwc3/core.c
SRC_C += usb/dwc3/dwc3-exynos.c
SRC_C += usb/dwc3/host.c
SRC_C += usb/host/ehci-exynos.c
SRC_C += usb/host/xhci-plat.c
CC_OPT += -DCONFIG_USB_EHCI_TT_NEWSCHED=1
CC_OPT += -DCONFIG_USB_DWC3_HOST=1
CC_OPT += -DCONFIG_USB_OTG_UTILS=1
CC_OPT += -DCONFIG_USB_XHCI_PLATFORM=1
CC_OPT += -DDWC3_QUIRK

207
repos/dde_linux/src/drivers/usb_host/spec/odroid_x2/platform.cc
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@ -1,207 +0,0 @@
/*
* \brief EHCI for Odroid-x2 initializaion code
* \author Sebastian Sumpf
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopez Leon <humberto@uclv.cu>
* \author Reinir Millo Sanchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is distributed under the terms of the GNU General Public License
* version 2.
*/
/* Genode */
#include <drivers/defs/odroid_x2.h>
#include <base/attached_io_mem_dataspace.h>
#include <io_mem_session/connection.h>
#include <regulator/consts.h>
#include <regulator_session/connection.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
#include <gpio_session/connection.h>
/* Emulation */
#include <lx_emul.h>
#include <platform.h>
using namespace Genode;
enum Usb_masks {
PHY0_NORMAL_MASK = 0x39 << 0,
PHY0_SWRST_MASK = 0x7 << 0,
PHY1_STD_NORMAL_MASK = 0x7 << 6,
EXYNOS4X12_HSIC0_NORMAL_MASK = 0x7 << 9,
EXYNOS4X12_HSIC1_NORMAL_MASK = 0x7 << 12,
EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK = 0xf << 7,
EXYNOS4X12_PHY1_SWRST_MASK = 0xf << 3,
};
enum {
/*The EHCI base is taken from linux kernel */
EHCI_BASE = 0x12580000,
GPIO_BASE = 0x11000000,
USBOTG = 0x125B0000,
EHCI_IRQ = Odroid_x2::USB_HOST20_IRQ,
};
static resource _ehci[] =
{
{ EHCI_BASE, EHCI_BASE + 0xfff, "ehci", IORESOURCE_MEM },
{ EHCI_IRQ, EHCI_IRQ, "ehci-irq", IORESOURCE_IRQ },
};
/**
* EHCI controller
*/
struct Ehci : Genode::Mmio
{
Ehci(addr_t const mmio_base) : Mmio(mmio_base)
{
write<Cmd>(0);
/* reset */
write<Cmd::Reset>(1);
while(read<Cmd::Reset>())
msleep(1);
}
struct Cmd : Register<0x10, 32>
{
struct Reset : Bitfield<1, 1> { };
};
};
/**
* USB OTG handling
*/
struct Usb_otg : Genode::Mmio
{
Usb_otg(Genode::Env &env, Genode::addr_t base)
: Genode::Mmio (base)
{
Timer::Connection timer(env);
unsigned int rstcon_mask = 0;
unsigned int phyclk_mask = 5;
unsigned int phypwr_mask = 0;
/*set the clock of device*/
write<Phyclk>(phyclk_mask);
rstcon_mask= read<Phyclk>();
/* set to normal of Device */
phypwr_mask= read<Phypwr>() & ~PHY0_NORMAL_MASK;
write<Phypwr>(phypwr_mask);
/* set to normal of Host */
phypwr_mask=read<Phypwr>();
phypwr_mask &= ~(PHY1_STD_NORMAL_MASK
|EXYNOS4X12_HSIC0_NORMAL_MASK
|EXYNOS4X12_HSIC1_NORMAL_MASK);
write<Phypwr>(phypwr_mask);
/* reset both PHY and Link of Device */
rstcon_mask = read<Rstcon>() | PHY0_SWRST_MASK;
write<Rstcon>(rstcon_mask);
timer.usleep(10);
rstcon_mask &= ~PHY0_SWRST_MASK;
write<Rstcon>(rstcon_mask);
/* reset both PHY and Link of Host */
rstcon_mask = read<Rstcon>()
|EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
|EXYNOS4X12_PHY1_SWRST_MASK;
write<Rstcon>(rstcon_mask);
timer.usleep(10);
rstcon_mask &= ~(EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
|EXYNOS4X12_PHY1_SWRST_MASK);
write<Rstcon>(rstcon_mask);
timer.usleep(10);
}
struct Phypwr : Register <0x0,32>{};
struct Phyclk : Register <0x4,32>{};
struct Rstcon : Register <0x8,32>{};
};
static void clock_pwr_init(Genode::Env &env)
{
/* enable USB2 clock and power up */
static Regulator::Connection reg_clk(env, Regulator::CLK_USB20);
reg_clk.state(true);
static Regulator::Connection reg_pwr(env, Regulator::PWR_USB20);
reg_pwr.state(true);
}
static void usb_phy_init(Genode::Env &env)
{
Io_mem_connection io_usbotg(env, USBOTG, 0x1000);
addr_t usbotg_base = (addr_t)env.rm().attach(io_usbotg.dataspace());
Usb_otg usbotg(env, usbotg_base);
env.rm().detach(usbotg_base);
}
static void odroidx2_ehci_init(Genode::Env &env)
{
clock_pwr_init(env);
usb_phy_init(env);
/* reset hub via GPIO */
enum { X30 = 294, X34 = 298, X35 = 299 };
Gpio::Connection gpio_x30(env, X30);
Gpio::Connection gpio_x34(env, X34);
Gpio::Connection gpio_x35(env, X35);
/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
gpio_x30.write(true);
/* Disconnect, Reset, Connect */
gpio_x34.write(false);
gpio_x35.write(false);
gpio_x35.write(true);
gpio_x34.write(true);
/* reset ehci controller */
Io_mem_connection io_ehci(env, EHCI_BASE, 0x1000);
addr_t ehci_base = (addr_t)env.rm().attach(io_ehci.dataspace());
Ehci ehci(ehci_base);
env.rm().detach(ehci_base);
}
extern "C" void module_ehci_exynos_init();
extern "C" int module_usbnet_init();
extern "C" int module_smsc95xx_driver_init();
void platform_hcd_init(Genode::Env &, Services *services)
{
/* register EHCI controller */
module_ehci_exynos_init();
/* setup controller */
odroidx2_ehci_init(services->env);
/* setup EHCI-controller platform device */
platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
pdev->name = (char *)"exynos-ehci";
pdev->id = 0;
pdev->num_resources = 2;
pdev->resource = _ehci;
/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
static u64 dma_mask = ~(u64)0;
pdev->dev.dma_mask = &dma_mask;
pdev->dev.coherent_dma_mask = ~0;
platform_device_register(pdev);
}

1
repos/dde_linux/src/drivers/usb_host/spec/odroid_x2/regulator/consts.h
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@ -1 +0,0 @@
#include <spec/exynos4/regulator/consts.h>

14
repos/dde_linux/src/drivers/usb_host/spec/odroid_x2/target.mk
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@ -1,14 +0,0 @@
include $(REP_DIR)/src/drivers/usb_host/target.inc
TARGET = odroid_x2_usb_host_drv
REQUIRES = arm_v7
INC_DIR += $(REP_DIR)/src/drivers/usb_host/spec/arm
INC_DIR += $(REP_DIR)/src/include/spec/arm
SRC_CC += spec/arm/platform.cc
SRC_CC += spec/odroid_x2/platform.cc
SRC_C += usb/host/ehci-exynos.c
CC_OPT += -DCONFIG_USB_OTG_UTILS=1

4
repos/libports/run/qt5_drivers.inc
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@ -23,7 +23,6 @@ proc use_fb_drv { feature_arg } {
}
proc fb_drv_binary { } {
if {[have_spec exynos5]} { return exynos5_fb_drv }
if {[have_spec pbxa9]} { return pbxa9_fb_drv }
if {[have_spec x86]} { return vesa_fb_drv }
if {[have_spec imx53]} { return imx53_fb_drv }
@ -88,8 +87,7 @@ proc use_usb_input { feature_arg } {
proc use_usb_nic { feature_arg } {
upvar $feature_arg feature
return [expr {[info exists feature(Nic)] &&
([have_spec arndale] ||
[have_spec rpi])}]
[have_spec rpi]}]
}
proc use_usb_drv { feature_arg } {

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repos/os/include/regulator/component.h
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@ -1,104 +0,0 @@
/*
* \brief Regulator-session component
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR__COMPONENT_H_
#define _INCLUDE__REGULATOR__COMPONENT_H_
#include <root/component.h>
#include <regulator_session/rpc_object.h>
#include <regulator/driver.h>
namespace Regulator {
class Session_component;
class Root;
}
class Regulator::Session_component : public Regulator::Session_rpc_object
{
private:
Driver_factory & _driver_factory;
Driver & _driver;
public:
Session_component(Regulator_id regulator_id,
Driver_factory & driver_factory)
: Session_rpc_object(regulator_id),
_driver_factory(driver_factory),
_driver(_driver_factory.create(regulator_id)) { }
~Session_component()
{
_driver.state(_id, false);
_driver_factory.destroy(_driver);
}
/***********************************
** Regulator session interface **
***********************************/
void level(unsigned long level) override { _driver.level(_id, level); }
unsigned long level() override { return _driver.level(_id); }
void state(bool enable) override { _driver.state(_id, enable); }
bool state() override { return _driver.state(_id); }
};
class Regulator::Root :
public Genode::Root_component<Regulator::Session_component>
{
private:
Regulator::Driver_factory & _driver_factory;
protected:
Session_component *_create_session(const char *args) override
{
using namespace Genode;
char reg_name[64];
Arg_string::find_arg(args, "regulator").string(reg_name,
sizeof(reg_name), 0);
size_t ram_quota =
Arg_string::find_arg(args, "ram_quota").ulong_value(0);
/* delete ram quota by the memory needed for the session */
size_t session_size = max((size_t)4096,
sizeof(Session_component));
if (ram_quota < session_size)
throw Insufficient_ram_quota();
if (!strlen(reg_name))
throw Service_denied();
return new (md_alloc())
Session_component(regulator_id_by_name(reg_name),
_driver_factory);
}
public:
Root(Genode::Env & env,
Genode::Allocator & md_alloc,
Regulator::Driver_factory & driver_factory)
: Genode::Root_component<Regulator::Session_component>(env.ep(),
md_alloc),
_driver_factory(driver_factory) { }
};
#endif /* _INCLUDE__REGULATOR__COMPONENT_H_ */

54
repos/os/include/regulator/driver.h
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@ -1,54 +0,0 @@
/*
* \brief Regulator-driver interface
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR__DRIVER_H_
#define _INCLUDE__REGULATOR__DRIVER_H_
#include <regulator/consts.h>
namespace Regulator {
struct Driver;
struct Driver_factory;
}
/**
* Interface to be implemented by the device-specific driver code
*/
struct Regulator::Driver : Genode::Interface
{
virtual void level(Regulator_id id, unsigned long level) = 0;
virtual unsigned long level(Regulator_id id) = 0;
virtual void state(Regulator_id id, bool enable) = 0;
virtual bool state(Regulator_id id) = 0;
};
/**
* Interface for constructing the driver object
*/
struct Regulator::Driver_factory : Genode::Interface
{
/**
* Construct new driver
*/
virtual Driver &create(Regulator_id regulator) = 0;
/**
* Destroy driver
*/
virtual void destroy(Driver &driver) = 0;
};
#endif /* _REGULATOR__DRIVER_H_ */

22
repos/os/include/regulator_session/capability.h
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@ -1,22 +0,0 @@
/*
* \brief Regulator session capability type
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR_SESSION__CAPABILITY_H_
#define _INCLUDE__REGULATOR_SESSION__CAPABILITY_H_
#include <base/capability.h>
#include <regulator_session/regulator_session.h>
namespace Regulator { typedef Genode::Capability<Session> Session_capability; }
#endif /* _INCLUDE__REGULATOR_SESSION__CAPABILITY_H_ */

44
repos/os/include/regulator_session/client.h
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@ -1,44 +0,0 @@
/*
* \brief Client-side regulator session interface
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR_SESSION__CLIENT_H_
#define _INCLUDE__REGULATOR_SESSION__CLIENT_H_
#include <base/rpc_client.h>
#include <regulator_session/capability.h>
namespace Regulator { struct Session_client; }
struct Regulator::Session_client : public Genode::Rpc_client<Session>
{
/**
* Constructor
*
* \param session session capability
*/
Session_client(Session_capability session)
: Genode::Rpc_client<Session>(session) { }
/*********************************
** Regulator session interface **
*********************************/
void level(unsigned long level) override { call<Rpc_set_level>(level); }
unsigned long level() override { return call<Rpc_level>(); }
void state(bool enable) override { call<Rpc_set_state>(enable); }
bool state() override { return call<Rpc_state>(); }
};
#endif /* _INCLUDE__REGULATOR_SESSION__CLIENT_H_ */

42
repos/os/include/regulator_session/connection.h
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@ -1,42 +0,0 @@
/*
* \brief Connection to regulator service
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR_SESSION__CONNECTION_H_
#define _INCLUDE__REGULATOR_SESSION__CONNECTION_H_
#include <regulator_session/client.h>
#include <regulator/consts.h>
#include <base/connection.h>
namespace Regulator { struct Connection; }
struct Regulator::Connection : Genode::Connection<Session>, Session_client
{
/**
* Constructor
*
* \param regulator identifier for the specific regulator
* \param label string identifier of the client
*/
Connection(Genode::Env &env, Regulator_id regulator, const char * label = "")
:
Genode::Connection<Session>(env,
session(env.parent(),
"ram_quota=8K, cap_quota=%ld, regulator=\"%s\", label=\"%s\"",
CAP_QUOTA, regulator_name_by_id(regulator), label)),
Session_client(cap())
{ }
};
#endif /* _INCLUDE__REGULATOR_SESSION__CONNECTION_H_ */

65
repos/os/include/regulator_session/regulator_session.h
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@ -1,65 +0,0 @@
/*
* \brief Abstract regulator session interface.
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR_SESSION__REGULATOR_SESSION_H_
#define _INCLUDE__REGULATOR_SESSION__REGULATOR_SESSION_H_
#include <session/session.h>
namespace Regulator { struct Session; }
struct Regulator::Session : public Genode::Session
{
/**
* \noapi
*/
static const char *service_name() { return "Regulator"; }
enum { CAP_QUOTA = 2 };
virtual ~Session() { }
/**
* Set regulator specific level
*/
virtual void level(unsigned long level) = 0;
/**
* Returns current regulator level
*/
virtual unsigned long level() = 0;
/**
* Enable/disable regulator
*/
virtual void state(bool enable) = 0;
/**
* Returns whether regulator is enabled or not
*/
virtual bool state() = 0;
/*******************
** RPC interface **
*******************/
GENODE_RPC(Rpc_set_level, void, level, unsigned long);
GENODE_RPC(Rpc_level, unsigned long, level);
GENODE_RPC(Rpc_set_state, void, state, bool);
GENODE_RPC(Rpc_state, bool, state);
GENODE_RPC_INTERFACE(Rpc_set_level, Rpc_level, Rpc_set_state, Rpc_state);
};
#endif /* _INCLUDE__REGULATOR_SESSION__REGULATOR_SESSION_H_ */

40
repos/os/include/regulator_session/rpc_object.h
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@ -1,40 +0,0 @@
/*
* \brief Server-side block regulator interface
* \author Stefan Kalkowski
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__REGULATOR_SESSION__SERVER_H_
#define _INCLUDE__REGULATOR_SESSION__SERVER_H_
#include <base/rpc_server.h>
#include <regulator/consts.h>
#include <regulator_session/regulator_session.h>
namespace Regulator { class Session_rpc_object; }
class Regulator::Session_rpc_object : public Genode::Rpc_object<Session, Session_rpc_object>
{
protected:
Regulator_id _id; /* regulator identifier */
public:
/**
* Constructor
*
* \param id identifies the specific regulator
*/
Session_rpc_object(Regulator_id id) : _id(id) { }
};
#endif /* _INCLUDE__REGULATOR_SESSION__SERVER_H_ */

73
repos/os/include/spec/exynos4/regulator/consts.h
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@ -1,73 +0,0 @@
/*
* \brief Regulator definitions for Exynos4412
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__SPEC__EXYNOS4__REGULATOR__CONSTS_H_
#define _INCLUDE__SPEC__EXYNOS4__REGULATOR__CONSTS_H_
#include <util/string.h>
namespace Regulator {
enum Regulator_id {
CLK_CPU,
CLK_USB20,
CLK_MMC0,
CLK_HDMI,
PWR_USB20,
PWR_HDMI,
MAX,
INVALID
};
struct Regulator_name {
Regulator_id id;
const char * name;
};
Regulator_name names[] = {
{ CLK_CPU, "clock-cpu" },
{ CLK_USB20, "clock-usb2.0" },
{ CLK_MMC0, "clock-mmc0" },
{ CLK_HDMI, "clock-hdmi" },
{ PWR_USB20, "power-usb2.0" },
{ PWR_HDMI, "power-hdmi"},
};
Regulator_id regulator_id_by_name(const char * name)
{
for (unsigned i = 0; i < sizeof(names)/sizeof(names[0]); i++)
if (Genode::strcmp(names[i].name, name) == 0)
return names[i].id;
return INVALID;
}
const char * regulator_name_by_id(Regulator_id id) {
return (id < sizeof(names)/sizeof(names[0])) ? names[id].name : 0; }
/***************************************
** Device specific level definitions **
***************************************/
enum Cpu_clock_freq {
CPU_FREQ_200 = 200000000,
CPU_FREQ_400 = 400000000,
CPU_FREQ_600 = 600000000,
CPU_FREQ_800 = 800000000,
CPU_FREQ_1000 = 1000000000,
CPU_FREQ_1200 = 1200000000,
CPU_FREQ_1400 = 1400000000,
};
}
#endif /* _INCLUDE__SPEC__EXYNOS4__REGULATOR__CONSTS_H_ */

86
repos/os/include/spec/exynos5/regulator/consts.h
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@ -1,86 +0,0 @@
/*
* \brief Regulator definitions for Exynos5
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2013-06-13
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__SPEC__EXYNOS5__REGULATOR__CONSTS_H_
#define _INCLUDE__SPEC__EXYNOS5__REGULATOR__CONSTS_H_
#include <util/string.h>
namespace Regulator {
enum Regulator_id {
CLK_CPU,
CLK_SATA,
CLK_USB30,
CLK_USB20,
CLK_MMC0,
CLK_HDMI,
PWR_SATA,
PWR_USB30,
PWR_USB20,
PWR_HDMI,
MAX,
INVALID
};
struct Regulator_name {
Regulator_id id;
const char * name;
};
static constexpr Regulator_name names[] = {
{ CLK_CPU, "clock-cpu" },
{ CLK_SATA, "clock-sata" },
{ CLK_USB30, "clock-usb3.0" },
{ CLK_USB20, "clock-usb2.0" },
{ CLK_MMC0, "clock-mmc0" },
{ CLK_HDMI, "clock-hdmi" },
{ PWR_SATA, "power-sata" },
{ PWR_USB30, "power-usb3.0" },
{ PWR_USB20, "power-usb2.0" },
{ PWR_HDMI, "power-hdmi"},
};
inline Regulator_id regulator_id_by_name(const char * name)
{
for (unsigned i = 0; i < sizeof(names)/sizeof(names[0]); i++)
if (Genode::strcmp(names[i].name, name) == 0)
return names[i].id;
return INVALID;
}
inline const char * regulator_name_by_id(Regulator_id id) {
return (id < sizeof(names)/sizeof(names[0])) ? names[id].name : 0; }
/***************************************
** Device specific level definitions **
***************************************/
enum Cpu_clock_freq {
CPU_FREQ_200 = 200000000,
CPU_FREQ_400 = 400000000,
CPU_FREQ_600 = 600000000,
CPU_FREQ_800 = 800000000,
CPU_FREQ_1000 = 1000000000,
CPU_FREQ_1200 = 1200000000,
CPU_FREQ_1400 = 1400000000,
CPU_FREQ_1600 = 1600000000,
CPU_FREQ_1700 = 1700000000,
/* warning: 1700 not recommended by the reference manual
we just insert this for performance measurement against
Linux, which uses this overclocking */
};
}
#endif /* _INCLUDE__SPEC__EXYNOS5__REGULATOR__CONSTS_H_ */

5
repos/os/recipes/api/regulator_session/content.mk
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@ -1,5 +0,0 @@
MIRRORED_FROM_REP_DIR := include/regulator_session \
include/regulator \
include/spec/exynos4/regulator \
include/spec/exynos5/regulator
include $(REP_DIR)/recipes/api/session.inc

1
repos/os/recipes/api/regulator_session/hash
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@ -1 +0,0 @@
2020-03-25 4678452f3145a5469ba2759fde81cfad4a717a71

1
repos/os/recipes/src/platform_drv/used_apis
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@ -1,5 +1,4 @@
base
os
platform_session
regulator_session
report_session

13
repos/os/run/cache.run
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@ -6,8 +6,6 @@
set build_components { core init test/cache }
lappend_if [have_spec arndale] build_components drivers/platform
build $build_components
create_boot_directory
@ -24,15 +22,8 @@ set config {
<default-route>
<any-service> <parent/> </any-service>
</default-route>
<default caps="100"/>}
<default caps="100"/>
append_if [have_spec arndale] config {
<start name="platform_drv">
<resource name="RAM" quantum="1M"/>
<provides><service name="Regulator"/></provides>
</start> }
append config {
<start name="test-cache">
<resource name="RAM" quantum="64M"/>
</start>
@ -42,8 +33,6 @@ install_config $config
set boot_modules { core ld.lib.so init test-cache }
lappend_if [have_spec arndale] boot_modules platform_drv
build_boot_image $boot_modules
run_genode_until "done.*\n" 300

12
repos/os/run/cpu_quota.run
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@ -147,18 +147,6 @@ proc check_counter { name opt cnt total_cnt } {
#
if {[have_include "power_on/qemu"]} { set tol 0.03 }
#
# FIXME: There is no reasonable explanation by now why the test results
# are less stable on these platforms. We have tried several things that
# did not lead to an explanation or improvement:
#
# * changing the timing parameters of the scheduler
# * switching off SMP
# * double-checking the speed of userland and kernel timers
#
if {[have_spec odroid_xu]} { set tol 0.04 }
if {[have_spec arndale]} { set tol 0.04 }
if {[expr $total_cnt != 0]} { set is [expr double($cnt) / $total_cnt ] }
set err [expr $is - $opt]

3
repos/os/run/fb_bench.run
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@ -1,5 +1,4 @@
if {[have_spec odroid_xu] ||
[have_spec imx7d_sabre] ||
if {[have_spec imx7d_sabre] ||
[have_spec imx6q_sabrelite] ||
[have_spec rpi3] ||
[have_spec zynq] ||

3
repos/os/run/nic_dump.run
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@ -1,5 +1,4 @@
if {[have_spec foc] || [have_spec odroid_xu] || [have_spec linux] ||
[have_spec rpi3] ||
if {[have_spec foc] || [have_spec linux] || [have_spec rpi3] ||
[expr [have_spec imx53] && [have_spec trustzone]]} {
puts "Run script is not supported on this platform."
exit 0

3
repos/os/run/ping_nic_router.run
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@ -1,5 +1,4 @@
if {[have_spec foc] || [have_spec odroid_xu] || [have_spec linux] ||
[have_spec rpi3] ||
if {[have_spec foc] || [have_spec linux] || [have_spec rpi3] ||
[expr [have_spec imx53] && [have_spec trustzone]]} {
puts "Run script is not supported on this platform."
exit 0

2
repos/os/run/sd_card_bench.run
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@ -9,7 +9,6 @@ proc buffer_size_kib {} {
if {[have_spec imx53] &&
![have_spec foc]} { return [expr 1024] }
if {[have_spec rpi]} { return [expr 4 * 1024] }
if {[have_spec arndale]} { return [expr 1024] }
puts "\n Run script is not supported on this platform. \n";
exit 0;
}
@ -20,7 +19,6 @@ proc sd_card_drv {} {
if {[have_spec imx6q_sabrelite]} { return imx6q_sabrelite_sd_card_drv }
if {[have_spec imx53]} { return imx53_sd_card_drv }
if {[have_spec rpi]} { return rpi_sd_card_drv }
if {[have_spec arndale]} { return arndale_sd_card_drv }
puts "\n Run script is not supported on this platform. \n";
exit 0;
}

3
repos/os/run/vmm_arm.run
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@ -6,7 +6,8 @@
assert_spec hw
if { ![have_spec imx7d_sabre] && ![have_spec arndale] && ![have_spec imx8q_evk] && ![have_spec virt_qemu]} {
if { ![have_spec imx7d_sabre] && ![have_spec imx8q_evk] &&
![have_spec virt_qemu]} {
puts "Run script is not supported on this platform"
exit 0
}

1101
repos/os/src/drivers/framebuffer/spec/exynos5/driver.cc
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File diff suppressed because it is too large Load Diff

108
repos/os/src/drivers/framebuffer/spec/exynos5/driver.h
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@ -1,108 +0,0 @@
/*
* \brief Framebuffer driver for Exynos5 HDMI
* \author Martin Stein
* \date 2013-08-09
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVER_H_
#define _DRIVER_H_
/* Genode includes */
#include <base/component.h>
#include <base/stdint.h>
#include <base/log.h>
namespace Framebuffer
{
using namespace Genode;
/**
* Framebuffer driver
*/
class Driver;
}
class Framebuffer::Driver
{
public:
enum Format { FORMAT_RGB565 };
enum Output { OUTPUT_LCD, OUTPUT_HDMI };
private:
Genode::Env &_env;
size_t _fb_width;
size_t _fb_height;
Format _fb_format;
public:
/**
* Constructor
*/
Driver(Genode::Env &env)
:
_env(env),
_fb_width(0),
_fb_height(0),
_fb_format(FORMAT_RGB565)
{ }
/**
* Return amount of bytes that is used for one pixel descriptor
*
* \param format pixel format
*
* \retval 0 failed
* \retval >0 succeeded
*/
static size_t bytes_per_pixel(Format format)
{
switch (format) {
case FORMAT_RGB565:
return 2;
default:
error("unknown pixel format");
return 0;
}
}
/**
* Return size of framebuffer in bytes
*
* \param width width of framebuffer in pixel
* \param height height of framebuffer in pixel
* \param format pixel format of framebuffer
*
* \retval 0 failed
* \retval >0 succeeded
*/
size_t buffer_size(size_t width, size_t height, Format format)
{
return bytes_per_pixel(format) * width * height;
}
/**
* Initialize driver for HDMI output
*
* \param width width of screen and framebuffer in pixel
* \param height height of screen and framebuffer in pixel
* \param format pixel format of framebuffer
* \param fb_phys physical base of framebuffer
*
* \retval -1 failed
* \retval 0 succeeded
*/
int init(size_t width, size_t height, Format format, addr_t fb_phys);
};
#endif /* _DRIVER_H_ */

147
repos/os/src/drivers/framebuffer/spec/exynos5/main.cc
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@ -1,147 +0,0 @@
/*
* \brief Framebuffer driver for Exynos5 HDMI
* \author Martin Stein
* \date 2013-08-09
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* Genode includes */
#include <base/attached_rom_dataspace.h>
#include <base/component.h>
#include <framebuffer_session/framebuffer_session.h>
#include <timer_session/connection.h>
#include <dataspace/client.h>
#include <base/log.h>
#include <os/static_root.h>
#include <util/string.h>
/* local includes */
#include <driver.h>
namespace Framebuffer
{
using namespace Genode;
/**
* Framebuffer session backend
*/
class Session_component;
struct Main;
};
class Framebuffer::Session_component
:
public Genode::Rpc_object<Framebuffer::Session>
{
private:
Genode::Env &_env;
unsigned _width;
unsigned _height;
Driver::Format _format;
size_t _size;
Dataspace_capability _ds;
addr_t _phys_base;
Timer::Connection _timer { _env };
/**
* Convert Driver::Format to Framebuffer::Mode::Format
*/
static Mode::Format _convert_format(Driver::Format driver_format)
{
switch (driver_format) {
case Driver::FORMAT_RGB565: return Mode::RGB565;
}
return Mode::INVALID;
}
public:
/**
* Constructor
*
* \param driver driver backend that communicates with hardware
* \param width width of framebuffer in pixel
* \param height height of framebuffer in pixel
* \param output targeted output device
*/
Session_component(Genode::Env &env, Driver &driver,
unsigned width, unsigned height)
:
_env(env),
_width(width),
_height(height),
_format(Driver::FORMAT_RGB565),
_size(driver.buffer_size(width, height, _format)),
_ds(_env.ram().alloc(_size, WRITE_COMBINED)),
_phys_base(Dataspace_client(_ds).phys_addr())
{
if (driver.init(width, height, _format, _phys_base)) {
error("could not initialize display");
struct Could_not_initialize_display : Exception { };
throw Could_not_initialize_display();
}
}
/************************************
** Framebuffer::Session interface **
************************************/
Dataspace_capability dataspace() override { return _ds; }
Mode mode() const override
{
return Mode(_width, _height, _convert_format(_format));
}
void mode_sigh(Genode::Signal_context_capability) override { }
void sync_sigh(Genode::Signal_context_capability sigh) override
{
_timer.sigh(sigh);
_timer.trigger_periodic(10*1000);
}
void refresh(int, int, int, int) override { }
};
static unsigned config_dimension(Genode::Xml_node node, char const *attr,
unsigned default_value)
{
return node.attribute_value(attr, default_value);
}
struct Main
{
Genode::Env &_env;
Genode::Entrypoint &_ep;
Genode::Attached_rom_dataspace _config { _env, "config" };
Framebuffer::Driver _driver { _env };
Framebuffer::Session_component _fb_session { _env, _driver,
config_dimension(_config.xml(), "width", 1920),
config_dimension(_config.xml(), "height", 1080)
};
Genode::Static_root<Framebuffer::Session> _fb_root { _ep.manage(_fb_session) };
Main(Genode::Env &env) : _env(env), _ep(_env.ep())
{
/* announce service and relax */
_env.parent().announce(_ep.manage(_fb_root));
}
};
void Component::construct(Genode::Env &env) { static Main main(env); }

8
repos/os/src/drivers/framebuffer/spec/exynos5/target.mk
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@ -1,8 +0,0 @@
TARGET = exynos5_fb_drv
REQUIRES = arm_v7
SRC_CC += main.cc driver.cc
LIBS += base
INC_DIR += $(PRG_DIR)
INC_DIR += $(call select_from_repositories,include/spec/exynos5)
CC_CXX_WARN_STRICT :=

220
repos/os/src/drivers/gpio/spec/exynos4/driver.h
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@ -1,220 +0,0 @@
/*
* \brief Gpio driver for the Odroid-x2
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopéz Leon <humberto@uclv.cu>
* \author Reinier Millo Sánchez <rmillo@uclv.cu>
* \date 2015-07-03
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVER_H_
#define _DRIVER_H_
/* Genode includes */
#include <gpio/driver.h>
#include <irq_session/connection.h>
#include <timer_session/connection.h>
/* local includes */
#include <gpio.h>
namespace Gpio { class Odroid_x2_driver; }
class Gpio::Odroid_x2_driver : public Driver
{
private:
Reg _reg1;
Reg _reg2;
Reg _reg3;
Reg _reg4;
Genode::Irq_connection _irq;
Genode::Signal_handler<Odroid_x2_driver> _dispatcher;
Genode::Signal_context_capability _sig_cap[MAX_PINS];
bool _irq_enabled[MAX_PINS];
bool _async;
void _handle()
{
handle_irq();
}
void handle_irq() { }
Gpio::Reg *_gpio_reg(int gpio_pin)
{
int pos = gpio_bank_index(gpio_pin, true);
switch(pos) {
case 0 ... 13:
return &_reg1;
case 14 ... 38:
return &_reg2;
case 39:
return &_reg3;
case 40 ... 46:
return &_reg4;
default:
Genode::error("no Gpio_bank for pin ", gpio_pin, " available");
return 0;
}
}
int _gpio_index(int gpio) { return gpio & 0x1f; }
Odroid_x2_driver(Genode::Env &env)
:
_reg1(env, 0x11400000, 1000),
_reg2(env, 0x11000000, 1000),
_reg3(env, 0x03860000, 1000),
_reg4(env, 0x106E0000, 1000),
_irq(env, 104),
_dispatcher(env.ep(), *this, &Odroid_x2_driver::_handle),
_async(false)
{
_irq.sigh(_dispatcher);
_irq.ack_irq();
}
public:
static Odroid_x2_driver& factory(Genode::Env &env);
/******************************
** Gpio::Driver interface **
******************************/
void direction(unsigned gpio_pin, bool input) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _bank_offset[pos_gpio];
int gpio = gpio_pin - sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
reg->set_direction(gpio, input, offset);
}
void write(unsigned gpio_pin, bool level) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _bank_offset[pos_gpio];
int gpio = gpio_pin - sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
reg->write_pin(gpio, level, offset);
}
bool read(unsigned gpio_pin) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _bank_offset[pos_gpio];
int gpio = gpio_pin - sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
return reg->read_pin(gpio, offset) ;
}
void debounce_enable(unsigned /* gpio */, bool /* enable */) override {
Genode::warning("debounce_enable not supported!"); }
void debounce_time(unsigned /* gpio */, unsigned long /* us */) override {
Genode::warning("debounce_time not supported!"); }
void falling_detect(unsigned gpio_pin) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _irq_offset[pos_gpio];
int gpio = gpio_pin - sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
reg->set_enable_triggers(gpio, offset, FALLING);
}
void rising_detect(unsigned gpio_pin) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _irq_offset[pos_gpio];
int gpio = gpio_pin - sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
reg->set_enable_triggers(gpio, offset, RISING);
}
void high_detect(unsigned gpio_pin) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _irq_offset[pos_gpio];
int gpio = gpio_pin-sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
reg->set_enable_triggers(gpio, offset, HIGH);
}
void low_detect(unsigned gpio_pin) override
{
int pos_gpio = gpio_bank_index(gpio_pin, true);
int sum_gpio = gpio_bank_index(gpio_pin, false);
Genode::off_t offset = _irq_offset[pos_gpio];
int gpio = gpio_pin - sum_gpio;
Reg* reg = _gpio_reg(gpio_pin);
reg->set_enable_triggers(gpio, offset, LOW);
}
void irq_enable(unsigned gpio_pin, bool enable) override
{
_irq_enabled[gpio_pin] = enable;
}
void ack_irq(unsigned /* gpio_pin */) override
{
_irq.ack_irq();
}
void register_signal(unsigned gpio_pin,
Genode::Signal_context_capability cap) override
{
_sig_cap[gpio_pin] = cap;
}
void unregister_signal(unsigned gpio_pin) override
{
Genode::Signal_context_capability cap;
_sig_cap[gpio_pin] = cap;
}
int gpio_bank_index(int pin, bool pos)
{
int i = 0 ,sum = 0;
while (i<MAX_BANKS && ((sum + _bank_sizes[i]) <= pin)) {
sum += 1 + _bank_sizes[i++];
}
return pos ? i : sum;
}
bool gpio_valid(unsigned gpio) override { return gpio < (MAX_PINS); }
};
#endif /* _DRIVER_H_ */

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repos/os/src/drivers/gpio/spec/exynos4/gpio.h
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/*
* \brief Odroid-x2 GPIO definitions
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopéz Leon <humberto@uclv.cu>
* \author Reinier Millo Sánchez <rmillo@uclv.cu>
* \date 2015-07-03
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _GPIO_H_
#define _GPIO_H_
/* Genode includes */
#include <base/attached_io_mem_dataspace.h>
#include <util/mmio.h>
namespace Gpio {
class Reg;
using namespace Genode;
}
struct Gpio::Reg : Attached_io_mem_dataspace, Mmio
{
struct Regs : Genode::Mmio
{
struct Con : Register<0x00, 32> {};
struct Dat : Register<0x04, 8> {};
Regs(Genode::addr_t base) : Genode::Mmio(base) {}
void set_con(unsigned int con) { write<Con>(con); }
void set_dat(unsigned int dat) { write<Dat>(dat); }
unsigned int get_con() { return read<Con>();}
unsigned int get_dat() { return read<Dat>();}
};
struct Irq_regs : Genode::Mmio
{
struct Int_con : Register <0x00,32>
{
struct Con0 : Bitfield<0, 3> {};
struct Con1 : Bitfield<4, 3> {};
struct Con2 : Bitfield<8, 3> {};
struct Con3 : Bitfield<12, 3> {};
struct Con4 : Bitfield<16, 3> {};
struct Con5 : Bitfield<20, 3> {};
struct Con6 : Bitfield<24, 3> {};
struct Con7 : Bitfield<28, 3> {};
};
Irq_regs(Genode::addr_t base) : Genode::Mmio(base) {}
void enable_triggers(unsigned gpio, unsigned value)
{
write<Int_con>(0);
switch(gpio) {
case 0: write<Int_con::Con0>(value); break;
case 1: write<Int_con::Con1>(value); break;
case 2: write<Int_con::Con2>(value); break;
case 3: write<Int_con::Con3>(value); break;
case 4: write<Int_con::Con4>(value); break;
case 5: write<Int_con::Con5>(value); break;
case 6: write<Int_con::Con6>(value); break;
case 7: write<Int_con::Con7>(value); break;
default: warning("Not is valid irq con!");
}
}
};
Reg(Genode::Env &env, addr_t base, size_t size)
: Attached_io_mem_dataspace(env, base, size),
Mmio((addr_t)local_addr<Reg>()) { }
void set_direction(int gpio, bool input, Genode::off_t offset)
{
Regs _reg((Genode::addr_t)local_addr<void>() + offset);
unsigned int value;
int id = (input ? 0 : 0x1);
value = _reg.get_con();
value &= ~(0xf << (gpio << 2));
value |= (id << (gpio << 2));
_reg.set_con(value);
}
void write_pin(unsigned gpio, bool level, Genode::off_t offset)
{
Regs _reg((Genode::addr_t)local_addr<void>() + offset);
unsigned int value;
value = _reg.get_dat();
value &= ~(0x1 << gpio);
if (level)
value |= 0x1 << gpio;
_reg.set_dat(value);
}
bool read_pin(unsigned gpio, Genode::off_t offset)
{
Regs _reg((Genode::addr_t)local_addr<void>() + offset);
return (_reg.get_dat() & (1 << gpio)) !=0;
}
void set_enable_triggers(unsigned gpio, Genode::off_t offset,unsigned value)
{
Irq_regs _irq_regs((Genode::addr_t)local_addr<void>() + offset);
_irq_regs.enable_triggers(gpio,value);
}
};
enum {
MAX_BANKS = 48,
MAX_PINS = 361
};
enum Irqs_triggers {
LOW = 0x0,
HIGH = 0x1,
FALLING = 0x2,
RISING = 0x3,
BOTH = 0x4
};
const int _bank_sizes[MAX_PINS] = {
/* TODO check value of registes type ETC. */
/* GPIO Part1 */
/* GPA0 GPA1 GPB GPC0 GPC1 GPD0 GPD1 GPF0 GPF1 GPF2 GPF3 ETC1 GPJ0 GPJ1 */
8, 6, 8, 5, 5, 4, 4, 8, 8, 8, 6, 6, 8, 5,
/* GPIO Part2 */ /* index 14 */
/* GPK0 GPK1 GPK2 GPK3 GPL0 GPL1 GPL2 GPY0 GPY1 GPY2 GPY3 GPY4 GPY5 GPY6 */
7, 7, 7, 7, 7, 2, 8, 6, 4, 6, 8, 8, 8, 8,
/* ETC0 ETC6 GPM0 GPM1 GPM2 GPM3 GPM4 GPX0 GPX1 GPX2 GPX3 */
6, 8, 8, 7, 5, 8, 8, 8, 8, 8, 8, /* index 35,36,37 */
/* GPIO Part3 */
/* GPZ */ /* index 39 */
7,
/* GPIO Part4 */ //index 40
/* GPV0 GPV1 ETC7 GPV2 GPV3 ETC8 GPV4 */
8, 8, 2, 8, 8, 2, 8
};
const Genode::off_t _bank_offset[MAX_BANKS]=
{
/* Part1 */
/* GPA0 GPA1 GPB GPC0 GPC1 GPD0 GPD1 GPF0 GPF1 GPF2 GPF3 ETC1 GPJ0 GPJ1 */
0x0000, 0x0020, 0x0040, 0x0060, 0x0080, 0x00A0, 0x00C0, 0x0180, 0x01A0, 0x01C0, 0x01E0, 0x0228, 0x0240, 0x0260,
/* Part2 */
/* GPK0 GPK1 GPK2 GPK3 GPL0 GPL1 GPL2 GPY0 GPY1 GPY2 GPY3 GPY4 GPY5 GPY6 */
0x0040, 0x0060, 0x0080, 0x00A0, 0x00C0, 0x00E0, 0x0100, 0x0120, 0x0140, 0x0160, 0x0180, 0x01A0, 0x01C0, 0x01E0,
/* ETC0 ETC6 GPM0 GPM1 GPM2 GPM3 GPM4 GPX0 GPX1 GPX2 GPX3 */
0x0208, 0x0228, 0x0260, 0x0280, 0x02A0, 0x02C0, 0x02E0, 0x0C00, 0x0C20, 0x0C40, 0x0C60,
/* Part3 */
0x0000, /*GPZ */
/* Part4 */
/* GPV0 GPV1 ETC7 GPV2 GPV3 ETC8 GPV4 */
0x0000, 0x0020, 0x0048, 0x0060, 0x0080, 0x00A8, 0x00C0,
};
const Genode::off_t _irq_offset[MAX_BANKS]=
{
/* Bank 1 irq */
/* con1 con2 con3 con4 con5 con6 con7 con13 con14 con15 con16 ETC con21 con22 */
0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x0730, 0x0734, 0x0738, 0x073C, -1, 0x0740, 0x0744,
/* Bank 2 irq */
/* con23 con24 con25 con26 con27 con28 con29 */
0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, -1, -1, -1, -1, -1, -1, -1,
/* con8 con9 con10 con11 con12 x0 x1 x2 x3 */
-1, -1, 0x0724, 0x0728, 0x072C, 0x0730, 0x0734, 0x0E00, 0x0E04, 0x0E08, 0x0E0C, //TODO Check values de x0-x3.
/* Bank 3 irq */
/* con50 */
0x0700,
/* Bank 4 irq */
/* con30 con31 con32 con33 con34 */
0x0700, 0x0704, -1, 0x0708, 0x070C, -1, 0x0710,
};
#endif /* _GPIO_H_ */

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repos/os/src/drivers/gpio/spec/exynos4/main.cc
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/*
* \brief Gpio driver for the Odroid-x2
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopéz Leon <humberto@uclv.cu>
* \author Reinier Millo Sánchez <rmillo@uclv.cu>
* \date 2015-07-03
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* Genode includes */
#include <base/attached_rom_dataspace.h>
#include <base/component.h>
#include <base/heap.h>
#include <base/log.h>
#include <gpio/component.h>
#include <gpio/config.h>
/* local includes */
#include <driver.h>
Gpio::Odroid_x2_driver& Gpio::Odroid_x2_driver::factory(Genode::Env &env)
{
static Odroid_x2_driver driver(env);
return driver;
}
struct Main
{
Genode::Env &env;
Genode::Sliced_heap sliced_heap;
Gpio::Odroid_x2_driver &driver;
Gpio::Root root;
Genode::Attached_rom_dataspace config_rom { env, "config" };
Main(Genode::Env &env)
: env(env),
sliced_heap(env.ram(), env.rm()),
driver(Gpio::Odroid_x2_driver::factory(env)),
root(&env.ep().rpc_ep(), &sliced_heap, driver)
{
using namespace Genode;
log("--- Odroid_x2 gpio driver ---");
Gpio::process_config(config_rom.xml(), driver);
/*
* Announce service
*/
env.parent().announce(env.ep().manage(root));
}
};
void Component::construct(Genode::Env &env) { static Main main(env); }

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repos/os/src/drivers/gpio/spec/exynos4/target.mk
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TARGET = exynos4_gpio_drv
REQUIRES = arm_v7
SRC_CC = main.cc
LIBS = base
INC_DIR += $(PRG_DIR)
vpath main.cc $(PRG_DIR)

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repos/os/src/drivers/platform/spec/arndale/cmu.h
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/*
* \brief Regulator driver for clock management unit of Exynos5250 SoC
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2013-06-13
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVERS__PLATFORM__SPEC__ARNDALE__CMU_H_
#define _DRIVERS__PLATFORM__SPEC__ARNDALE__CMU_H_
#include <base/log.h>
#include <regulator/consts.h>
#include <regulator/driver.h>
#include <drivers/defs/arndale.h>
#include <os/attached_mmio.h>
using namespace Regulator;
using Genode::warning;
class Cmu : public Regulator::Driver,
private Genode::Attached_mmio
{
private:
static const Genode::uint16_t m_values[]; /* M values for frequencies */
static const Genode::uint8_t p_values[]; /* P values for frequencies */
static const Genode::uint8_t s_values[]; /* S values for frequencies */
template <unsigned OFF>
struct Pll_lock : Register<OFF, 32>
{
struct Pll_locktime : Register<OFF, 32>::template Bitfield<0, 20> { };
static Genode::uint32_t max_lock_time(Genode::uint8_t pdiv) {
return pdiv * 250; };
};
template <unsigned OFF>
struct Pll_con0 : Register<OFF, 32>
{
struct S : Register<OFF, 32>::template Bitfield < 0, 3> { };
struct P : Register<OFF, 32>::template Bitfield < 8, 6> { };
struct M : Register<OFF, 32>::template Bitfield <16, 10> { };
struct Locked : Register<OFF, 32>::template Bitfield <29, 1> { };
struct Enable : Register<OFF, 32>::template Bitfield <31, 1> { };
};
/***********************
** CMU CPU registers **
***********************/
typedef Pll_lock<0> Apll_lock;
typedef Pll_con0<0x100> Apll_con0;
struct Clk_src_cpu : Register<0x200, 32>
{
struct Mux_cpu_sel : Bitfield<16, 1>
{
enum { MOUT_APLL, SCLK_MPLL};
};
};
struct Clk_mux_stat_cpu : Register<0x400, 32>
{
struct Cpu_sel : Bitfield<16, 3>
{
enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
};
};
struct Clk_div_cpu0 : Register<0x500, 32>
{
/* Cpu0 divider values for frequencies 200 - 1700 */
static const Genode::uint32_t values[];
};
struct Clk_div_cpu1 : Register<0x504, 32>
{
/* Divider for cpu1 doesn't change */
enum { FIX_VALUE = 32 };
};
struct Clk_div_stat_cpu0 : Register<0x600, 32>
{
struct Div_arm : Bitfield< 0, 1> {};
struct Div_cpud : Bitfield< 4, 1> {};
struct Div_acp : Bitfield< 8, 1> {};
struct Div_pheriph : Bitfield<12, 1> {};
struct Div_atb : Bitfield<16, 1> {};
struct Div_pclk_dbg : Bitfield<20, 1> {};
struct Div_apll : Bitfield<24, 1> {};
struct Div_arm2 : Bitfield<28, 1> {};
static bool in_progress(access_t stat_word)
{
return stat_word & (Div_arm::bits(1) |
Div_cpud::bits(1) |
Div_acp::bits(1) |
Div_pheriph::bits(1) |
Div_atb::bits(1) |
Div_pclk_dbg::bits(1) |
Div_apll::bits(1) |
Div_arm2::bits(1));
}
};
struct Clk_div_stat_cpu1 : Register<0x604, 32>
{
struct Div_copy : Bitfield<0, 1> { };
struct Div_hpm : Bitfield<4, 1> { };
static bool in_progress(access_t stat_word)
{
return stat_word & (Div_copy::bits(1) |
Div_hpm::bits(1));
}
};
/************************
** CMU CORE registers **
************************/
typedef Pll_lock<0x4000> Mpll_lock;
typedef Pll_con0<0x4100> Mpll_con0;
struct Clk_src_core1 : Register<0x4204, 32>
{
struct Mux_mpll_sel : Bitfield<8, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
};
struct Clk_gate_ip_acp : Register<0x8800, 32> { };
struct Clk_gate_ip_isp0 : Register<0xc800, 32> { };
struct Clk_gate_ip_isp1 : Register<0xc804, 32> { };
struct Clk_gate_sclk_isp : Register<0xc900, 32> { };
/***********************
** CMU TOP registers **
***********************/
typedef Pll_lock<0x10020> Cpll_lock;
typedef Pll_lock<0x10030> Epll_lock;
typedef Pll_lock<0x10040> Vpll_lock;
typedef Pll_lock<0x10050> Gpll_lock;
typedef Pll_con0<0x10120> Cpll_con0;
typedef Pll_con0<0x10130> Epll_con0;
typedef Pll_con0<0x10140> Vpll_con0;
typedef Pll_con0<0x10150> Gpll_con0;
struct Clk_src_top2 : Register<0x10218, 32>
{
struct Mux_mpll_user_sel : Bitfield<20, 1> { enum { XXTI, MOUT_MPLL}; };
};
struct Clk_src_fsys : Register<0x10244, 32>
{
struct Sata_sel : Bitfield<24, 1> {
enum { SCLK_MPLL_USER, SCLK_BPLL_USER }; };
struct Usbdrd30_sel : Bitfield<28, 1> {
enum { SCLK_MPLL_USER, SCLK_CPLL }; };
};
struct Clk_src_mask_fsys : Register<0x10340, 32>
{
struct Mmc0_mask : Bitfield<0, 1> { enum { MASK, UNMASK }; };
struct Sata_mask : Bitfield<24, 1> { enum { MASK, UNMASK }; };
struct Usbdrd30_mask : Bitfield<28, 1> { enum { MASK, UNMASK }; };
};
struct Clk_div_fsys0 : Register<0x10548, 32>
{
struct Sata_ratio : Bitfield<20, 4> { };
struct Usbdrd30_ratio : Bitfield<24, 4> { };
};
struct Clk_div_stat_fsys0 : Register<0x10648, 32>
{
struct Div_sata : Bitfield<20, 1> {};
struct Div_usbdrd30 : Bitfield<24, 1> {};
};
struct Clk_gate_ip_gscl : Register<0x10920, 32> { };
struct Clk_gate_ip_disp1 : Register<0x10928, 32>
{
struct Clk_mixer : Bitfield<5, 1> { };
struct Clk_hdmi : Bitfield<6, 1> { };
};
struct Clk_gate_ip_mfc : Register<0x1092c, 32> { };
struct Clk_gate_ip_g3d : Register<0x10930, 32> { };
struct Clk_gate_ip_gen : Register<0x10934, 32> { };
struct Clk_gate_ip_fsys : Register<0x10944, 32>
{
struct Pdma0 : Bitfield<1, 1> { };
struct Pdma1 : Bitfield<2, 1> { };
struct Sata : Bitfield<6, 1> { };
struct Sdmmc0 : Bitfield<12, 1> { };
struct Usbhost20 : Bitfield<18, 1> { };
struct Usbdrd30 : Bitfield<19, 1> { };
struct Sata_phy_ctrl : Bitfield<24, 1> { };
struct Sata_phy_i2c : Bitfield<25, 1> { };
};
struct Clk_src_disp1_0 : Register<0x1022c, 32>
{
struct Hdmi_sel : Bitfield<20, 1> { };
};
struct Clk_src_mask_disp1_0 : Register<0x1032c, 32>
{
struct Hdmi_mask : Bitfield<20, 1> { };
};
struct Clk_gate_ip_peric : Register<0x10950, 32>
{
struct Clk_uart2 : Bitfield<2, 1> { };
struct Clk_i2chdmi : Bitfield<14, 1> { };
struct Clk_pwm : Bitfield<24, 1> { };
};
struct Clk_gate_block : Register<0x10980, 32>
{
struct Clk_disp1 : Bitfield<5, 1> { };
struct Clk_gen : Bitfield<2, 1> { };
};
/*************************
** CMU CDREX registers **
*************************/
typedef Pll_lock<0x20010> Bpll_lock;
typedef Pll_con0<0x20110> Bpll_con0;
struct Pll_div2_sel : Register<0x20a24, 32>
{
struct Mpll_fout_sel : Bitfield<4, 1> {
enum { MPLL_FOUT_HALF, MPLL_FOUT }; };
};
/*******************
** CPU functions **
*******************/
Cpu_clock_freq _cpu_freq;
void _cpu_clk_freq(unsigned long level)
{
unsigned freq;
switch (level) {
case CPU_FREQ_200:
freq = 0;
break;
case CPU_FREQ_400:
freq = 1;
break;
case CPU_FREQ_600:
freq = 2;
break;
case CPU_FREQ_800:
freq = 3;
break;
case CPU_FREQ_1000:
freq = 4;
break;
case CPU_FREQ_1200:
freq = 5;
break;
case CPU_FREQ_1400:
freq = 6;
break;
case CPU_FREQ_1600:
freq = 7;
break;
case CPU_FREQ_1700:
freq = 8;
break;
default:
warning("Unsupported CPU frequency level ", level);
warning("Supported values are 200, 400, 600, 800 MHz");
warning("and 1, 1.2, 1.4, 1.6, 1.7 GHz");
return;
};
/**
* change clock divider values
*/
/* cpu0 divider */
write<Clk_div_cpu0>(Clk_div_cpu0::values[freq]);
while (Clk_div_stat_cpu0::in_progress(read<Clk_div_stat_cpu0>())) ;
/* cpu1 divider */
write<Clk_div_cpu1>(Clk_div_cpu1::FIX_VALUE);
while (Clk_div_stat_cpu1::in_progress(read<Clk_div_stat_cpu1>())) ;
/**
* change APLL frequency
*/
/* change reference clock to MPLL */
write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::SCLK_MPLL);
while (read<Clk_mux_stat_cpu::Cpu_sel>()
!= Clk_mux_stat_cpu::Cpu_sel::SCLK_MPLL) ;
/* set lock time */
unsigned pdiv = p_values[freq];
write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
/* change P, M, S values of APLL */
write<Apll_con0::P>(p_values[freq]);
write<Apll_con0::M>(m_values[freq]);
write<Apll_con0::S>(s_values[freq]);
while (!read<Apll_con0::Locked>()) ;
/* change reference clock back to APLL */
write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::MOUT_APLL);
while (read<Clk_mux_stat_cpu::Cpu_sel>()
!= Clk_mux_stat_cpu::Cpu_sel::MOUT_APLL) ;
_cpu_freq = static_cast<Cpu_clock_freq>(level);
}
/**********************
** Device functions **
**********************/
void _hdmi_enable()
{
write<Clk_gate_ip_peric::Clk_i2chdmi>(1);
Clk_gate_ip_disp1::access_t gd1 = read<Clk_gate_ip_disp1>();
Clk_gate_ip_disp1::Clk_mixer::set(gd1, 1);
Clk_gate_ip_disp1::Clk_hdmi::set(gd1, 1);
write<Clk_gate_ip_disp1>(gd1);
write<Clk_gate_block::Clk_disp1>(1);
write<Clk_src_mask_disp1_0::Hdmi_mask>(1);
write<Clk_src_disp1_0::Hdmi_sel>(1);
}
void _sata_enable()
{
/* enable I2C for SATA */
write<Clk_gate_ip_fsys::Sata_phy_i2c>(1);
/**
* set SATA clock to 66 MHz (nothing else supported)
* assuming 800 MHz from sclk_mpll_user, formula: sclk / (divider + 1)
*/
write<Clk_div_fsys0::Sata_ratio>(11); /* */
while (read<Clk_div_stat_fsys0::Div_sata>()) ;
/* enable SATA and SATA Phy */
write<Clk_gate_ip_fsys::Sata>(1);
write<Clk_gate_ip_fsys::Sata_phy_ctrl>(1);
write<Clk_src_mask_fsys::Sata_mask>(1);
}
void _usb30_enable()
{
/**
* set USBDRD30 clock to 66 MHz
* assuming 800 MHz from sclk_mpll_user, formula: sclk / (divider + 1)
*/
write<Clk_div_fsys0::Usbdrd30_ratio>(11);
while (read<Clk_div_stat_fsys0::Div_usbdrd30>()) ;
/* enable USBDRD30 clock */
write<Clk_gate_ip_fsys::Usbdrd30>(1);
write<Clk_src_mask_fsys::Usbdrd30_mask>(1);
}
void _enable(Regulator_id id)
{
switch (id) {
case CLK_SATA:
_sata_enable();
break;
case CLK_HDMI:
_hdmi_enable();
break;
case CLK_USB30:
_usb30_enable();
break;
case CLK_USB20:
return write<Clk_gate_ip_fsys::Usbhost20>(1);
case CLK_MMC0:
write<Clk_gate_ip_fsys::Sdmmc0>(1);
write<Clk_src_mask_fsys::Mmc0_mask>(1);
break;
default:
warning("Unsupported for ", names[id].name);
}
}
void _disable(Regulator_id id)
{
switch (id) {
case CLK_SATA:
write<Clk_gate_ip_fsys::Sata_phy_i2c>(0);
write<Clk_gate_ip_fsys::Sata>(0);
write<Clk_gate_ip_fsys::Sata_phy_ctrl>(0);
write<Clk_src_mask_fsys::Sata_mask>(0);
break;
case CLK_USB30:
write<Clk_gate_ip_fsys::Usbdrd30>(0);
write<Clk_src_mask_fsys::Usbdrd30_mask>(0);
break;
case CLK_USB20:
return write<Clk_gate_ip_fsys::Usbhost20>(0);
case CLK_MMC0:
write<Clk_gate_ip_fsys::Sdmmc0>(0);
write<Clk_src_mask_fsys::Mmc0_mask>(0);
break;
default:
warning("Unsupported for ", names[id].name);
}
}
public:
/**
* Constructor
*/
Cmu(Genode::Env &env)
: Genode::Attached_mmio(env, Arndale::CMU_MMIO_BASE,
Arndale::CMU_MMIO_SIZE),
_cpu_freq(CPU_FREQ_1600)
{
/**
* Close certain clock gates by default (~ 0.7 Watt reduction)
*/
write<Clk_gate_ip_acp>(0);
write<Clk_gate_ip_isp0>(0);
write<Clk_gate_ip_isp1>(0);
write<Clk_gate_sclk_isp>(0);
write<Clk_gate_ip_gscl>(0);
write<Clk_gate_ip_disp1>(0);
write<Clk_gate_ip_mfc>(0);
write<Clk_gate_ip_g3d>(0);
write<Clk_gate_ip_gen>(0);
write<Clk_gate_ip_fsys>(0);
write<Clk_gate_ip_peric>(Clk_gate_ip_peric::Clk_uart2::bits(1) |
Clk_gate_ip_peric::Clk_pwm::bits(1));
write<Clk_gate_block>(Clk_gate_block::Clk_gen::bits(1));
/**
* Set default CPU frequency
*/
_cpu_clk_freq(_cpu_freq);
/**
* Hard wiring of certain reference clocks
*/
write<Pll_div2_sel::Mpll_fout_sel>(Pll_div2_sel::Mpll_fout_sel::MPLL_FOUT_HALF);
write<Clk_src_core1::Mux_mpll_sel>(Clk_src_core1::Mux_mpll_sel::MPLL_FOUT_RGT);
write<Clk_src_top2::Mux_mpll_user_sel>(Clk_src_top2::Mux_mpll_user_sel::MOUT_MPLL);
write<Clk_src_fsys::Sata_sel>(Clk_src_fsys::Sata_sel::SCLK_MPLL_USER);
write<Clk_src_fsys::Usbdrd30_sel>(Clk_src_fsys::Usbdrd30_sel::SCLK_MPLL_USER);
}
/********************************
** Regulator driver interface **
********************************/
void level(Regulator_id id, unsigned long level) override
{
switch (id) {
case CLK_CPU:
_cpu_clk_freq(level);
break;
default:
warning("Unsupported for ", names[id].name);
}
}
unsigned long level(Regulator_id id) override
{
switch (id) {
case CLK_CPU:
return _cpu_freq;
case CLK_USB30:
case CLK_SATA:
return 66666666; /* 66 MHz */
default:
warning("Unsupported for ", names[id].name);
}
return 0;
}
void state(Regulator_id id, bool enable) override
{
if (enable)
_enable(id);
else
_disable(id);
}
bool state(Regulator_id id) override
{
switch (id) {
case CLK_SATA:
return read<Clk_gate_ip_fsys::Sata>() &&
read<Clk_gate_ip_fsys::Sata_phy_ctrl>() &&
read<Clk_src_mask_fsys::Sata_mask>();
case CLK_USB30:
return read<Clk_gate_ip_fsys::Usbdrd30>() &&
read<Clk_src_mask_fsys::Usbdrd30_mask>();
case CLK_USB20:
return read<Clk_gate_ip_fsys::Usbhost20>();
case CLK_MMC0:
return read<Clk_gate_ip_fsys::Sdmmc0>() &&
read<Clk_src_mask_fsys::Mmc0_mask>();
default:
warning("Unsupported for ", names[id].name);
}
return true;
}
};
const Genode::uint8_t Cmu::s_values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
const Genode::uint16_t Cmu::m_values[] = { 100, 100, 200, 100, 125,
150, 175, 200, 425 };
const Genode::uint8_t Cmu::p_values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
0x2147710, 0x2147710, 0x3157720,
0x4167720, 0x4177730, 0x5377730 };
#endif /* _DRIVERS__PLATFORM__SPEC__ARNDALE__CMU_H_ */

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repos/os/src/drivers/platform/spec/arndale/main.cc
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/*
* \brief Driver for Arndale specific platform devices (clocks, power, etc.)
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2013-06-13
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <base/log.h>
#include <base/heap.h>
#include <base/component.h>
#include <regulator/component.h>
#include <regulator/consts.h>
#include <cmu.h>
#include <pmu.h>
struct Driver_factory : Regulator::Driver_factory
{
Cmu _cmu;
Pmu _pmu;
Driver_factory(Genode::Env &env) : _cmu(env), _pmu(env) { }
Regulator::Driver &create(Regulator::Regulator_id id) override
{
switch (id) {
case Regulator::CLK_CPU:
case Regulator::CLK_SATA:
case Regulator::CLK_USB30:
case Regulator::CLK_USB20:
case Regulator::CLK_MMC0:
case Regulator::CLK_HDMI:
return _cmu;
case Regulator::PWR_SATA:
case Regulator::PWR_USB30:
case Regulator::PWR_USB20:
case Regulator::PWR_HDMI:
return _pmu;
default:
throw Genode::Service_denied(); /* invalid regulator */
};
}
void destroy(Regulator::Driver &) override { }
};
struct Main
{
Genode::Env & env;
Genode::Heap heap { env.ram(), env.rm() };
::Driver_factory factory { env };
Regulator::Root root { env, heap, factory };
Main(Genode::Env & env) : env(env) {
env.parent().announce(env.ep().manage(root)); }
};
void Component::construct(Genode::Env &env)
{
Genode::log("--- Arndale platform driver ---");
static Main main(env);
}

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repos/os/src/drivers/platform/spec/arndale/pmu.h
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/*
* \brief Regulator driver for power management unit of Exynos5250 SoC
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2013-06-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVERS__PLATFORM__SPEC__ARNDALE__PMU_H_
#define _DRIVERS__PLATFORM__SPEC__ARNDALE__PMU_H_
#include <base/log.h>
#include <regulator/consts.h>
#include <regulator/driver.h>
#include <drivers/defs/arndale.h>
#include <os/attached_mmio.h>
using namespace Regulator;
using Genode::warning;
class Pmu : public Regulator::Driver,
private Genode::Attached_mmio
{
private:
template <unsigned OFFSET>
struct Control : Register <OFFSET, 32>
{
struct Enable : Register<OFFSET, 32>::template Bitfield<0, 1> { };
};
template <unsigned OFFSET>
struct Configuration : Register <OFFSET, 32>
{
struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 3> { };
};
template <unsigned OFFSET>
struct Status : Register <OFFSET, 32>
{
struct Stat : Register<OFFSET, 32>::template Bitfield<0, 3> { };
};
template <unsigned OFFSET>
struct Sysclk_configuration : Register <OFFSET, 32>
{
struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 1> { };
};
template <unsigned OFFSET>
struct Sysclk_status : Register <OFFSET, 32>
{
struct Stat : Register<OFFSET, 32>::template Bitfield<0, 1> { };
};
struct Hdmi_phy_control : Register<0x700, 32>
{
struct Enable : Bitfield<0, 1> { };
struct Div_ratio : Bitfield<16, 10> { };
};
typedef Control<0x704> Usbdrd_phy_control;
typedef Control<0x708> Usbhost_phy_control;
typedef Control<0x70c> Efnand_phy_control;
typedef Control<0x718> Adc_phy_control;
typedef Control<0x71c> Mtcadc_phy_control;
typedef Control<0x720> Dptx_phy_control;
typedef Control<0x724> Sata_phy_control;
typedef Sysclk_configuration<0x2a40> Vpll_sysclk_configuration;
typedef Sysclk_status<0x2a44> Vpll_sysclk_status;
typedef Sysclk_configuration<0x2a60> Epll_sysclk_configuration;
typedef Sysclk_status<0x2a64> Epll_sysclk_status;
typedef Sysclk_configuration<0x2aa0> Cpll_sysclk_configuration;
typedef Sysclk_status<0x2aa4> Cpll_sysclk_status;
typedef Sysclk_configuration<0x2ac0> Gpll_sysclk_configuration;
typedef Sysclk_status<0x2ac4> Gpll_sysclk_status;
typedef Configuration<0x4000> Gscl_configuration;
typedef Status<0x4004> Gscl_status;
typedef Configuration<0x4020> Isp_configuration;
typedef Status<0x4024> Isp_status;
typedef Configuration<0x4040> Mfc_configuration;
typedef Status<0x4044> Mfc_status;
typedef Configuration<0x4060> G3d_configuration;
typedef Status<0x4064> G3d_status;
typedef Configuration<0x40A0> Disp1_configuration;
typedef Status<0x40A4> Disp1_status;
typedef Configuration<0x40C0> Mau_configuration;
typedef Status<0x40C4> Mau_status;
template <typename C, typename S>
void _disable_domain()
{
if (read<typename S::Stat>() == 0)
return;
write<typename C::Local_pwr_cfg>(0);
while (read<typename S::Stat>() != 0) ;
}
template <typename C, typename S>
void _enable_domain()
{
if (read<typename S::Stat>() == 7)
return;
write<typename C::Local_pwr_cfg>(7);
while (read<typename S::Stat>() != 7) ;
}
void _enable(unsigned long id)
{
switch (id) {
case PWR_USB30:
write<Usbdrd_phy_control::Enable>(1);
break;
case PWR_USB20:
write<Usbhost_phy_control::Enable>(1);
break;
case PWR_SATA :
write<Sata_phy_control::Enable>(1);
break;
case PWR_HDMI: {
_enable_domain<Disp1_configuration, Disp1_status>();
Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
Hdmi_phy_control::Div_ratio::set(hpc, 150);
Hdmi_phy_control::Enable::set(hpc, 1);
write<Hdmi_phy_control>(hpc);
break; }
default:
warning("Unsupported for ", names[id].name);
}
}
void _disable(unsigned long id)
{
switch (id) {
case PWR_USB30:
write<Usbdrd_phy_control::Enable>(0);
break;
case PWR_USB20:
write<Usbhost_phy_control::Enable>(0);
break;
case PWR_SATA :
write<Sata_phy_control::Enable>(0);
break;
default:
warning("Unsupported for ", names[id].name);
}
}
public:
/**
* Constructor
*/
Pmu(Genode::Env &env)
: Genode::Attached_mmio(env, Arndale::PMU_MMIO_BASE,
Arndale::PMU_MMIO_SIZE)
{
write<Hdmi_phy_control ::Enable>(0);
write<Usbdrd_phy_control ::Enable>(0);
write<Usbhost_phy_control::Enable>(0);
write<Efnand_phy_control ::Enable>(0);
write<Adc_phy_control ::Enable>(0);
write<Mtcadc_phy_control ::Enable>(0);
write<Dptx_phy_control ::Enable>(0);
write<Sata_phy_control ::Enable>(0);
_disable_domain<Gscl_configuration, Gscl_status>();
_disable_domain<Isp_configuration, Isp_status>();
_disable_domain<Mfc_configuration, Mfc_status>();
_disable_domain<G3d_configuration, G3d_status>();
_disable_domain<Disp1_configuration, Disp1_status>();
_disable_domain<Mau_configuration, Mau_status>();
_disable_domain<Vpll_sysclk_configuration, Vpll_sysclk_status>();
_disable_domain<Epll_sysclk_configuration, Epll_sysclk_status>();
_disable_domain<Cpll_sysclk_configuration, Cpll_sysclk_status>();
_disable_domain<Gpll_sysclk_configuration, Gpll_sysclk_status>();
}
/********************************
** Regulator driver interface **
********************************/
void level(Regulator_id id, unsigned long /* level */) override
{
switch (id) {
default:
warning("Unsupported for ", names[id].name);
}
}
unsigned long level(Regulator_id id) override
{
switch (id) {
default:
warning("Unsupported for ", names[id].name);
}
return 0;
}
void state(Regulator_id id, bool enable) override
{
if (enable)
_enable(id);
else
_disable(id);
}
bool state(Regulator_id id) override
{
switch (id) {
case PWR_USB30:
return read<Usbdrd_phy_control::Enable>();
case PWR_USB20:
return read<Usbhost_phy_control::Enable>();
case PWR_SATA:
return read<Sata_phy_control::Enable>();
default:
warning("Unsupported for ", names[id].name);
}
return true;
}
};
#endif /* _DRIVERS__PLATFORM__SPEC__ARNDALE__PMU_H_ */

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repos/os/src/drivers/platform/spec/arndale/target.mk
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TARGET = arndale_platform_drv
REQUIRES = arm_v7
SRC_CC = main.cc
INC_DIR += ${PRG_DIR} $(call select_from_repositories,include/spec/exynos5)
LIBS = base

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repos/os/src/drivers/platform/spec/odroid_x2/cmu.h
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/*
* \brief Regulator driver for clock management unit of Exynos4412 SoC
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopez Leon <humberto@uclv.cu>
* \author Reinier Millo Sanchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVERS__PLATFORM__SPEC__ODROID_X2__CMU_H_
#define _DRIVERS__PLATFORM__SPEC__ODROID_X2__CMU_H_
#include <regulator/consts.h>
#include <regulator/driver.h>
#include <drivers/defs/odroid_x2.h>
#include <os/attached_mmio.h>
#include <base/log.h>
using namespace Regulator;
class Cmu : public Regulator::Driver,
private Genode::Attached_mmio
{
private:
static const Genode::uint16_t m_values[]; /* M values for frequencies */
static const Genode::uint8_t p_values[]; /* P values for frequencies */
static const Genode::uint8_t s_values[]; /* S values for frequencies */
template <unsigned OFF>
struct Pll_lock : Register<OFF, 32>
{
struct Pll_locktime : Register<OFF, 32>::template Bitfield<0, 20> { };
static Genode::uint32_t max_lock_time(Genode::uint8_t pdiv) {
return pdiv * 250; };
};
template <unsigned OFF>
struct Pll_con0 : Register<OFF, 32>
{
struct S : Register<OFF, 32>::template Bitfield < 0, 3> { };
struct P : Register<OFF, 32>::template Bitfield < 8, 6> { };
struct M : Register<OFF, 32>::template Bitfield <16, 10> { };
struct Locked : Register<OFF, 32>::template Bitfield <29, 1> { };
struct Enable : Register<OFF, 32>::template Bitfield <31, 1> { };
};
/***********************
** CMU CPU registers **
***********************/
typedef Pll_lock<4000> Apll_lock;
typedef Pll_con0<0x14100> Apll_con0;
struct Clk_src_cpu : Register<0x14200, 32>
{
struct Mux_core_sel : Bitfield<16, 1>
{
enum { MOUT_APLL, SCLK_MPLL};
};
};
struct Clk_mux_stat_cpu : Register<0x14400, 32>
{
struct Core_sel : Bitfield<16, 3>
{
enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
};
};
struct Clk_div_cpu0 : Register<0x14500, 32>
{
/* Cpu0 divider values for frequencies 200 - 1400 */
static const Genode::uint32_t values[];
};
struct Clk_div_cpu1 : Register<0x14504, 32>
{
/* Divider for cpu1 doesn't change */
enum { FIX_VALUE = 32 };
};
struct Clk_div_stat_cpu0 : Register<0x14600, 32>
{
struct Div_core : Bitfield< 0, 1> {};
struct Div_corem0 : Bitfield< 4, 1> {};
struct Div_corem1 : Bitfield< 8, 1> {};
struct Div_pheriph : Bitfield<12, 1> {};
struct Div_atb : Bitfield<16, 1> {};
struct Div_pclk_dbg : Bitfield<20, 1> {};
struct Div_apll : Bitfield<24, 1> {};
struct Div_core2 : Bitfield<28, 1> {};
static bool in_progress(access_t stat_word)
{
return stat_word & (Div_core::bits(1) |
Div_corem0::bits(1) |
Div_corem1::bits(1) |
Div_pheriph::bits(1) |
Div_atb::bits(1) |
Div_pclk_dbg::bits(1) |
Div_apll::bits(1) |
Div_core2::bits(1));
}
};
struct Clk_div_stat_cpu1 : Register<0x14604, 32>
{
struct Div_copy : Bitfield<0, 1> { };
struct Div_hpm : Bitfield<4, 1> { };
static bool in_progress(access_t stat_word)
{
return stat_word & (Div_copy::bits(1) |
Div_hpm::bits(1));
}
};
/************************
** CMU CORE registers **
************************/
typedef Pll_lock<0x0008> Mpll_lock;
typedef Pll_con0<0x0108> Mpll_con0;
/***********************
** CMU TOP registers **
***********************/
struct Clk_gate_ip_tv : Register<0x10928, 32>
{
struct Clk_mixer : Bitfield<1, 1> { };
struct Clk_hdmi : Bitfield<3, 1> { };
};
struct Clk_gate_ip_fsys : Register<0xC940, 32>
{
struct Usbhost20 : Bitfield<12, 1> { };
struct Usbdevice : Bitfield<13, 1> { };
};
struct Clk_src_tv : Register<0xC224, 32> /* old name Clk_src_disp1_0 */
{
struct Hdmi_sel : Bitfield<0, 1> { };
};
struct Clk_src_mask_tv : Register<0xC324, 32>
{
struct Hdmi_mask : Bitfield<0, 1> { };
};
struct Clk_gate_ip_peric : Register<0xC950, 32>
{
struct Clk_uart2 : Bitfield<2, 1> { };
struct Clk_i2chdmi : Bitfield<14, 1> { };
struct Clk_pwm : Bitfield<24, 1> { };
};
struct Clk_gate_block : Register<0xC970, 32>
{
struct Clk_tv : Bitfield<1, 1> { };
};
/*******************
** CPU functions **
*******************/
Cpu_clock_freq _cpu_freq;
void _cpu_clk_freq(unsigned long level)
{
using namespace Genode;
log("Changing CPU frequency to ",level);
unsigned freq;
switch (level) {
case CPU_FREQ_200:
freq = 0;
break;
case CPU_FREQ_400:
freq = 1;
break;
case CPU_FREQ_600:
freq = 2;
break;
case CPU_FREQ_800:
freq = 3;
break;
case CPU_FREQ_1000:
freq = 4;
break;
case CPU_FREQ_1200:
freq = 5;
break;
case CPU_FREQ_1400:
freq = 6;
break;
default:
warning("Unsupported CPU frequency level ", level);
warning("Supported values are 200, 400, 600, 800, 1000, 1200, 14000 MHz");
warning("and 1, 1.2, 1.4, 1.6, 1.7 GHz");
return;
};
/**
* change clock divider values
*/
/* cpu0 divider */
write<Clk_div_cpu0>(Clk_div_cpu0::values[freq]);
while (Clk_div_stat_cpu0::in_progress(read<Clk_div_stat_cpu0>())) ;
/* cpu1 divider */
write<Clk_div_cpu1>(Clk_div_cpu1::FIX_VALUE);
while (Clk_div_stat_cpu1::in_progress(read<Clk_div_stat_cpu1>())) ;
/**
* change APLL frequency
*/
/* change reference clock to MPLL */
write<Clk_src_cpu::Mux_core_sel>(Clk_src_cpu::Mux_core_sel::SCLK_MPLL);
while (read<Clk_mux_stat_cpu::Core_sel>()
!= Clk_mux_stat_cpu::Core_sel::SCLK_MPLL) ;
/* set lock time */
unsigned pdiv = p_values[freq];
write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
/* change P, M, S values of APLL */
write<Apll_con0::P>(p_values[freq]);
write<Apll_con0::M>(m_values[freq]);
write<Apll_con0::S>(s_values[freq]);
while (!read<Apll_con0::Locked>()) ;
/* change reference clock back to APLL */
write<Clk_src_cpu::Mux_core_sel>(Clk_src_cpu::Mux_core_sel::MOUT_APLL);
while (read<Clk_mux_stat_cpu::Core_sel>()
!= Clk_mux_stat_cpu::Core_sel::MOUT_APLL) ;
_cpu_freq = static_cast<Cpu_clock_freq>(level);
Genode::log("changed CPU frequency to ",level);
}
/**********************
** Device functions **
**********************/
void _hdmi_enable()
{
write<Clk_gate_ip_peric::Clk_i2chdmi>(1);
Clk_gate_ip_tv::access_t gd1 = read<Clk_gate_ip_tv>();
Clk_gate_ip_tv::Clk_mixer::set(gd1, 1);
Clk_gate_ip_tv::Clk_hdmi::set(gd1, 1);
write<Clk_gate_ip_tv>(gd1);
write<Clk_gate_block::Clk_tv>(1);
write<Clk_src_mask_tv::Hdmi_mask>(1);
write<Clk_src_tv::Hdmi_sel>(1);
}
void _enable(Regulator_id id)
{
switch (id) {
case CLK_USB20:
{
write<Clk_gate_ip_fsys::Usbdevice>(1);
return write<Clk_gate_ip_fsys::Usbhost20>(1);
}
case CLK_HDMI:
_hdmi_enable();
break;
default:
Genode::warning("enabling regulator unsupported for ", names[id].name);
}
}
void _disable(Regulator_id id)
{
switch (id) {
case CLK_USB20:
{
write<Clk_gate_ip_fsys::Usbdevice>(0);
return write<Clk_gate_ip_fsys::Usbhost20>(0);
}
default:
Genode::warning("disabling regulator unsupported for ", names[id].name);
}
}
public:
/**
* Constructor
*/
Cmu(Genode::Env &env)
: Genode::Attached_mmio(env, Odroid_x2::CMU_MMIO_BASE,
Odroid_x2::CMU_MMIO_SIZE),
_cpu_freq(CPU_FREQ_1400)
{
/**
* Close certain clock gates by default (~ 0.7 Watt reduction)
*/
write<Clk_gate_ip_fsys>(0);
write<Clk_gate_ip_peric::Clk_uart2>(1);
write<Clk_gate_ip_peric::Clk_pwm>(1);
/**
* Set default CPU frequency
*/
_cpu_clk_freq(_cpu_freq);
}
virtual ~Cmu() { }
/********************************
** Regulator driver interface **
********************************/
void level(Regulator_id id, unsigned long level) override
{
switch (id) {
case CLK_CPU:
_cpu_clk_freq(level);
break;
default:
Genode::warning("level setting unsupported for ", names[id].name);
}
}
unsigned long level(Regulator_id id) override
{
switch (id) {
case CLK_CPU:
return _cpu_freq;
default:
Genode::warning("level requesting unsupported for ", names[id].name);
}
return 0;
}
void state(Regulator_id id, bool enable) override
{
if (enable)
_enable(id);
else
_disable(id);
}
bool state(Regulator_id id) override
{
switch (id) {
case CLK_USB20:
return read<Clk_gate_ip_fsys::Usbhost20>();
default:
Genode::warning("state request unsupported for ", names[id].name);
}
return true;
}
};
const Genode::uint8_t Cmu::s_values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
const Genode::uint16_t Cmu::m_values[] = { 100, 100, 200, 100, 125,
150, 175, 200, 425 };
const Genode::uint8_t Cmu::p_values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
0x2147710, 0x2147710, 0x3157720,
0x4167720};
#endif /* _DRIVERS__PLATFORM__SPEC__ODROID_X2__CMU_H_ */

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/*
* \brief Driver for Odroid-x2 specific platform devices (clocks, power, etc.)
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopez Leon <humberto@uclv.cu>
* \author Reinier Millo Sanchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <base/log.h>
#include <base/heap.h>
#include <base/component.h>
#include <regulator/component.h>
#include <regulator/consts.h>
#include <cmu.h>
#include <pmu.h>
struct Driver_factory : Regulator::Driver_factory
{
Cmu _cmu;
Pmu _pmu;
Driver_factory(Genode::Env &env) : _cmu(env), _pmu(env) { }
Regulator::Driver &create(Regulator::Regulator_id id) override
{
switch (id) {
case Regulator::CLK_CPU:
case Regulator::CLK_USB20:
case Regulator::CLK_HDMI:
return _cmu;
case Regulator::PWR_USB20:
case Regulator::PWR_HDMI:
return _pmu;
default:
throw Genode::Service_denied(); /* invalid regulator */
}
}
void destroy(Regulator::Driver &) override { }
};
struct Main
{
Genode::Env & env;
Genode::Heap heap { env.ram(), env.rm() };
::Driver_factory factory { env };
Regulator::Root root { env, heap, factory };
Main(Genode::Env & env) : env(env) {
env.parent().announce(env.ep().manage(root)); }
};
void Component::construct(Genode::Env &env)
{
Genode::log("--- Odroid X2 platform driver ---");
static Main main(env);
}

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repos/os/src/drivers/platform/spec/odroid_x2/pmu.h
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/*
* \brief Regulator driver for power management unit of Exynos4412 SoC
* \author Alexy Gallardo Segura <alexy@uclv.cu>
* \author Humberto Lopez Leon <humberto@uclv.cu>
* \author Reinier Millo Sanchez <rmillo@uclv.cu>
* \date 2015-07-08
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVERS__PLATFORM__SPEC__ODROID_X2__PMU_H_
#define _DRIVERS__PLATFORM__SPEC__ODROID_X2__PMU_H_
#include <base/log.h>
#include <regulator/consts.h>
#include <regulator/driver.h>
#include <drivers/defs/odroid_x2.h>
#include <os/attached_mmio.h>
using Genode::warning;
using namespace Regulator;
class Pmu : public Regulator::Driver,
private Genode::Attached_mmio
{
private:
template <unsigned OFFSET>
struct Control : Register <OFFSET, 32>
{
struct Enable : Register<OFFSET, 32>::template Bitfield<0, 1> { };
};
template <unsigned OFFSET>
struct Configuration : Register <OFFSET, 32>
{
struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 3> { };
};
template <unsigned OFFSET>
struct Status : Register <OFFSET, 32>
{
struct Stat : Register<OFFSET, 32>::template Bitfield<0, 3> { };
};
template <unsigned OFFSET>
struct Sysclk_configuration : Register <OFFSET, 32>
{
struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 1> { };
};
template <unsigned OFFSET>
struct Sysclk_status : Register <OFFSET, 32>
{
struct Stat : Register<OFFSET, 32>::template Bitfield<0, 1> { };
};
struct Hdmi_phy_control : Register<0x700, 32>
{
struct Enable : Bitfield<0, 1> { };
struct Div_ratio : Bitfield<16, 10> { };
};
typedef Control<0x0704> Usbdrd_phy_control;
typedef Control<0x0708> Usbhost_phy1_control;
typedef Control<0x70c> Usbhost_phy2_control;
void _enable(unsigned long id)
{
switch (id) {
case PWR_USB20:
write<Usbdrd_phy_control::Enable>(1);
write<Usbhost_phy1_control::Enable>(1);
write<Usbhost_phy2_control::Enable>(1);
break;
case PWR_HDMI: {
Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
Hdmi_phy_control::Div_ratio::set(hpc, 150);
Hdmi_phy_control::Enable::set(hpc, 1);
write<Hdmi_phy_control>(hpc);
break; }
default:
warning("Unsupported for ", names[id].name);
}
}
void _disable(unsigned long id)
{
switch (id) {
case PWR_USB20:
write<Usbdrd_phy_control::Enable>(0);
write<Usbhost_phy1_control::Enable>(0);
write<Usbhost_phy2_control::Enable>(0);
break;
case PWR_HDMI:
write<Hdmi_phy_control::Enable>(0);
break;
default:
warning("Unsupported for ", names[id].name);
}
}
public:
/**
* Constructor
*/
Pmu(Genode::Env &env)
: Genode::Attached_mmio(env, Odroid_x2::PMU_MMIO_BASE,
Odroid_x2::PMU_MMIO_SIZE)
{
write<Usbdrd_phy_control::Enable>(0);
write<Usbhost_phy1_control::Enable>(0);
write<Usbhost_phy2_control::Enable>(0);
write<Hdmi_phy_control::Enable>(0);
}
/********************************
** Regulator driver interface **
********************************/
void level(Regulator_id id, unsigned long /* level */) override
{
switch (id) {
default:
warning("Unsupported for ", names[id].name);
}
}
unsigned long level(Regulator_id id) override
{
switch (id) {
default:
warning("Unsupported for ", names[id].name);
}
return 0;
}
void state(Regulator_id id, bool enable) override
{
if (enable)
_enable(id);
else
_disable(id);
}
bool state(Regulator_id id) override
{
switch (id) {
case PWR_USB20:
return read<Usbdrd_phy_control::Enable>();
default:
warning("Unsupported for ", names[id].name);
}
return true;
}
};
#endif /* _DRIVERS__PLATFORM__SPEC__ODROID_X2__PMU_H_ */

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repos/os/src/drivers/platform/spec/odroid_x2/target.mk
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TARGET = odroid_x2_platform_drv
REQUIRES = arm_v7
SRC_CC = main.cc
INC_DIR += ${PRG_DIR} $(call select_from_repositories,include/spec/exynos4)
LIBS = base

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/*
* \brief Exynos5-specific implementation of the Block::Driver interface
* \author Sebastian Sumpf
* \author Martin Stein
* \date 2013-03-22
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
/* local includes */
#include <driver.h>
using namespace Genode;
using namespace Sd_card;
Driver::Driver(Env &env)
:
Driver_base(env.ram()),
Attached_mmio(env, MSH_BASE, MSH_SIZE), _env(env)
{
_irq.sigh(_irq_handler);
_irq.ack_irq();
log("SD/MMC card detected");
log("capacity: ", _card_info.capacity_mb(), " MiB");
}
void Driver::read_dma(Block::sector_t block_number,
size_t block_count,
addr_t buf_phys,
Block::Packet_descriptor &pkt)
{
if (_block_transfer.pending) {
throw Request_congestion(); }
if (!_setup_idmac_descriptor_table(block_count, buf_phys))
throw Io_error();
_block_transfer.packet = pkt;
_block_transfer.pending = true;
if (!_issue_command(Read_multiple_block(block_number))) {
error("Read_multiple_block failed");
throw Io_error();
}
}
void Driver::write_dma(Block::sector_t block_number,
size_t block_count,
addr_t buf_phys,
Block::Packet_descriptor &pkt)
{
if (_block_transfer.pending) {
throw Request_congestion(); }
if (!_setup_idmac_descriptor_table(block_count, buf_phys))
throw Io_error();
_block_transfer.packet = pkt;
_block_transfer.pending = true;
if (!_issue_command(Write_multiple_block(block_number))) {
error("Read_multiple_block failed");
throw Io_error();
}
}
bool Driver::_reset()
{
Mmio::write<Ctrl::Reset>(0x7);
try { wait_for(Attempts(100), Microseconds(1000), _delayer,
Ctrl::Reset::Equal(0)); }
catch (Polling_timeout) {
error("Could not reset host contoller");
return false;
}
return true;
}
void Driver::_reset_fifo()
{
Mmio::write<Ctrl::Reset>(0x2);
try { wait_for(Attempts(100), Microseconds(1000), _delayer,
Ctrl::Reset::Equal(0)); }
catch (Polling_timeout) {
error("Could not reset fifo"); }
}
void Driver::_disable_irq()
{
Mmio::write<Rintsts>(~0U);
Mmio::write<Intmask>(0);
}
bool Driver::_update_clock_registers()
{
Cmd::access_t cmd = 0;
Cmd::Wait_prvdata_complete::set(cmd, 1);
Cmd::Update_clock_registers_only::set(cmd, 1);
Cmd::Start_cmd::set(cmd, 1);
Mmio::write<Cmd>(cmd);
try { wait_for(_delayer, Cmd::Start_cmd::Equal(0)); }
catch (Polling_timeout) {
error("Update clock registers failed");
return false;
}
return true;
}
bool Driver::_setup_bus(unsigned clock_div)
{
/* set host clock divider */
Mmio::write<Clkdiv>(clock_div);
if (!_update_clock_registers())
return false;
/* enable clock for card 1 */
Mmio::write<Clkena>(0x1);
if (!_update_clock_registers())
return false;
_delayer.usleep(10 * 1000);
return true;
}
Card_info Driver::_init()
{
Mmio::write<Pwren>(1);
if (!_reset())
throw Detection_failed();
Mmio::write<Emmc_ddr_req>(0x1);
_disable_irq();
Mmio::write<Tmout>(~0U);
Mmio::write<Idinten>(0);
Mmio::write<Bmod>(1);
Mmio::write<Bytcnt>(0);
Mmio::write<Fifoth>(0x203f0040);
/* set to one bit transfer Bit */
if (!_setup_bus(CLK_DIV_400Khz))
throw Detection_failed();
Mmio::write<Ctype>(BUS_WIDTH_1);
if (!issue_command(Go_idle_state())) {
warning("Go_idle_state command failed");
throw Detection_failed();
}
_delayer.usleep(2000);
if (!issue_command(Send_if_cond())) {
warning("Send_if_cond command failed");
throw Detection_failed();
}
/* if this succeeds it is an SD card */
if ((Mmio::read<Rsp0>() & 0xff) == 0xaa)
log("Found SD card");
/*
* We need to issue the same Mmc_send_op_cond command multiple
* times. The first time, we receive the status information. On
* subsequent attempts, the response tells us that the card is
* busy. Usually, the command is issued twice. We give up if the
* card is not reaching busy state after one second.
*/
unsigned i = 1000;
unsigned voltages = 0x300080;
unsigned arg = 0;
for (; i > 0; --i) {
if (!issue_command(Mmc_send_op_cond(arg, true))) {
warning("Sd_send_op_cond command failed");
throw Detection_failed();
}
arg = Mmio::read<Rsp0>();
arg = (voltages & (arg & 0x007FFF80)) | (arg & 0x60000000);
_delayer.usleep(1000);
if (Ocr::Busy::get(Mmio::read<Rsp0>()))
break;
}
if (i == 0) {
error("Send_op_cond timed out, could no power-on SD/MMC card");
throw Detection_failed();
}
Card_info card_info = _detect_mmc();
/* switch frequency to high speed */
enum { EXT_CSD_HS_TIMING = 185 };
if (!issue_command(Mmc_switch(EXT_CSD_HS_TIMING, 1))) {
error("Error setting high speed frequency");
throw Detection_failed();
}
enum { EXT_CSD_BUS_WIDTH = 183 };
/* set card to 8 bit */
if (!issue_command(Mmc_switch(EXT_CSD_BUS_WIDTH, 2))) {
error("Error setting card bus width");
throw Detection_failed();
}
Mmio::write<Ctype>(BUS_WIDTH_8);
/* set to eight bit transfer Bit */
if (!_setup_bus(CLK_DIV_52Mhz)) {
error("Error setting bus to high speed");
throw Detection_failed();
}
/* Enable IRQs data read timeout, data transfer done, resp error */
Mmio::write<Intmask>(0x28a);
Mmio::write<Ctrl::Global_interrupt>(1);
return card_info;
}
bool Driver::_setup_idmac_descriptor_table(size_t block_count,
addr_t phys_addr)
{
size_t const max_idmac_block_count = IDMAC_DESC_MAX_ENTRIES * 8;
if (block_count > max_idmac_block_count) {
error("Block request too large");
return false;
}
_reset_fifo();
Idmac_desc::Flags flags = Idmac_desc::FS;
size_t b = block_count;
int index = 0;
for (index = 0; b; index++, phys_addr += 0x1000, flags = Idmac_desc::NONE) {
b = _idmac_desc[index].set(b, _block_size(), phys_addr, flags);
_idmac_desc[index].next =
_idmac_desc_phys + ((index + 1) * sizeof(Idmac_desc));
}
_idmac_desc[index].next = (unsigned)_idmac_desc;
_idmac_desc[index].flags |= Idmac_desc::ER;
Mmio::write<Dbaddr>(_idmac_desc_phys);
Mmio::write<Ctrl::Dma_enable>(1);
Mmio::write<Ctrl::Use_internal_dmac>(1);
Mmio::write<Bmod::Fixed_burst>(1);
Mmio::write<Bmod::Idmac_enable>(1);
Mmio::write<Blksize>(_block_size());
Mmio::write<Bytcnt>(_block_size() * block_count);
Mmio::write<Pldmnd>(1);
return true;
}
void Driver::_handle_irq()
{
_irq.ack_irq();
if (!_block_transfer.pending) {
return; }
bool success = false;
if (Mmio::read<Rintsts::Response_error>()) {
error("Response error");
}
if (Mmio::read<Rintsts::Data_read_timeout>()) {
error("Data read timeout");
}
if (Mmio::read<Rintsts::Data_crc_error>()) {
error("CRC error");
}
if (Mmio::read<Rintsts::Data_transfer_over>()) {
Mmio::write<Rintsts>(~0U);
if (!_issue_command(Stop_transmission())) {
error("unable to stop transmission");
} else {
success = true;
}
}
_block_transfer.pending = false;
ack_packet(_block_transfer.packet, success);
}
bool Driver::_issue_command(Command_base const &command)
{
try { wait_for(Attempts(10000), Microseconds(100), _delayer,
Status::Data_busy::Equal(0)); }
catch (Polling_timeout) {
error("wait for State::Data_busy timed out ",
Hex(Mmio::read<Status>()));
return false;
}
Mmio::write<Rintsts>(~0UL);
/* write command argument */
Mmio::write<Cmdarg>(command.arg);
Cmd::access_t cmd = 0;
Cmd::Index::set(cmd, command.index);
if (command.transfer != TRANSFER_NONE) {
/* set data-direction bit depending on the command */
bool const write = command.transfer == TRANSFER_WRITE;
Cmd::Data_expected::set(cmd, 1);
Cmd::Write::set(cmd, write ? 1 : 0);
}
Cmd::access_t rsp_type = 0;
switch (command.rsp_type) {
case RESPONSE_NONE: rsp_type = Cmd::Rsp_type::RESPONSE_NONE; break;
case RESPONSE_136_BIT: rsp_type = Cmd::Rsp_type::RESPONSE_136_BIT; break;
case RESPONSE_48_BIT: rsp_type = Cmd::Rsp_type::RESPONSE_48_BIT; break;
case RESPONSE_48_BIT_WITH_BUSY: rsp_type = Cmd::Rsp_type::RESPONSE_48_BIT_WITH_BUSY; break;
}
Cmd::Rsp_type::set(cmd, rsp_type);
Cmd::Start_cmd::set(cmd, 1);
Cmd::Use_hold_reg::set(cmd ,1);
Cmd::Wait_prvdata_complete::set(cmd, 1);
if (command.index == 0)
Cmd::Init_sequence::set(cmd, 1);
/* issue command */
Mmio::write<Cmd>(cmd);
try { wait_for(Attempts(10000), Microseconds(100), _delayer,
Rintsts::Command_done::Equal(1)); }
catch (Polling_timeout) {
error("command failed "
"Rintst: ", Mmio::read<Rintsts>(), " "
"Mintst: ", Mmio::read<Mintsts>(), " "
"Status: ", Mmio::read<Status>());
if (Mmio::read<Rintsts::Response_timeout>())
warning("timeout");
if (Mmio::read<Rintsts::Response_error>())
warning("repsonse error");
return false;
}
/* acknowledge interrupt */
Mmio::write<Rintsts::Command_done>(1);
_delayer.usleep(100);
return true;
}
Cid Driver::_read_cid()
{
Cid cid;
cid.raw_0 = Mmio::read<Rsp0>();
cid.raw_1 = Mmio::read<Rsp1>();
cid.raw_2 = Mmio::read<Rsp2>();
cid.raw_3 = Mmio::read<Rsp3>();
return cid;
}
Csd Driver::_read_csd()
{
Csd csd;
csd.csd0 = Mmio::read<Rsp0>();
csd.csd1 = Mmio::read<Rsp1>();
csd.csd2 = Mmio::read<Rsp2>();
csd.csd3 = Mmio::read<Rsp3>();
return csd;
}
size_t Driver::_read_ext_csd()
{
Attached_ram_dataspace ds(_env.ram(), _env.rm(), 0x1000, UNCACHED);
addr_t phys = Dataspace_client(ds.cap()).phys_addr();
_setup_idmac_descriptor_table(1, phys);
if (!issue_command(Mmc_send_ext_csd()))
throw Detection_failed();
try { wait_for(_delayer, Rintsts::Data_transfer_over::Equal(1)); }
catch (Polling_timeout) {
error("cannot retrieve extented CSD");
throw Detection_failed();
}
/* clear IRQ */
Mmio::write<Rintsts::Data_transfer_over>(1);
/* contruct extented CSD */
Ext_csd csd((addr_t)ds.local_addr<addr_t>());
/* read revision */
if (csd.Mmio::read<Ext_csd::Revision>() < 2) {
error("extented CSD revision is < 2");
throw Detection_failed();
}
/* return sector count */
uint64_t capacity = csd.Mmio::read<Ext_csd::Sector_count>() * _block_size();
/* to MB */
return capacity / (1024 * 1024);
}
size_t Driver::Idmac_desc::set(size_t block_count,
size_t block_size,
addr_t phys_addr,
Flags flag)
{
constexpr size_t MAX_BLOCKS = 8;
flags = OWN | flag |
(block_count <= MAX_BLOCKS ? LD : (CH | DIC));
bytes = ((block_count < MAX_BLOCKS) ? block_count : MAX_BLOCKS) *
block_size;
addr = phys_addr;
return block_count < MAX_BLOCKS ?
0 : block_count - MAX_BLOCKS;
}

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/*
* \brief Exynos5-specific implementation of the Block::Driver interface
* \author Sebastian Sumpf
* \author Martin Stein
* \date 2013-03-22
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _DRIVER_H_
#define _DRIVER_H_
/* Genode includes */
#include <os/attached_mmio.h>
#include <timer_session/connection.h>
#include <drivers/defs/exynos5.h>
#include <regulator_session/connection.h>
#include <irq_session/connection.h>
#include <base/attached_ram_dataspace.h>
/* local includes */
#include <driver_base.h>
namespace Sd_card { class Driver; }
class Sd_card::Driver : public Driver_base,
private Attached_mmio
{
private:
/*
* Noncopyable
*/
Driver(Driver const &);
Driver &operator = (Driver const &);
enum {
HOST_FREQ = 52000000,
CLK_FREQ = 400000000,
CLK_DIV_52Mhz = 4,
CLK_DIV_400Khz = 0xff,
MSH_BASE = 0x12200000,
MSH_SIZE = 0x10000,
IDMAC_DESC_MAX_ENTRIES = 1024
};
enum Bus_width {
BUS_WIDTH_1 = 0,
BUS_WIDTH_4 = 1,
BUS_WIDTH_8 = 1 << 16,
};
template <off_t OFFSET, bool STRICT_WRITE = false>
struct Register : Mmio::Register<OFFSET, 32, STRICT_WRITE> { };
struct Ctrl : Register<0x0>
{
struct Reset : Bitfield<0, 3> { };
struct Global_interrupt : Bitfield<4, 1> { };
struct Dma_enable : Bitfield<5, 1> { };
struct Use_internal_dmac : Bitfield<25, 1> { };
};
struct Pwren : Register<0x4> { };
struct Clkdiv : Register<0x8> { };
struct Clkena : Register<0x10> { };
struct Tmout : Register<0x14> { };
struct Ctype : Register<0x18, true> { };
struct Blksize : Register<0x1c> { };
struct Bytcnt : Register<0x20> { };
struct Intmask : Register<0x24> { };
struct Cmdarg : Register<0x28> { };
struct Cmd : Register<0x2c>
{
struct Index : Bitfield<0, 6> { };
struct Rsp_type : Bitfield<6, 3>
{
enum Response { RESPONSE_NONE = 0,
RESPONSE_48_BIT = 1,
RESPONSE_48_BIT_WITH_BUSY = 5,
RESPONSE_136_BIT = 7,
};
};
struct Data_expected : Bitfield<9, 1> { };
struct Write : Bitfield<10, 1> { };
struct Wait_prvdata_complete : Bitfield<13, 1> { };
struct Init_sequence : Bitfield<15, 1> { };
struct Update_clock_registers_only : Bitfield<21, 1> { };
struct Use_hold_reg : Bitfield<29, 1> { };
struct Start_cmd : Bitfield<31, 1> { };
};
struct Rsp0 : Register<0x30> { };
struct Rsp1 : Register<0x34> { };
struct Rsp2 : Register<0x38> { };
struct Rsp3 : Register<0x3c> { };
struct Mintsts : Register<0x40> { };
struct Rintsts : Register<0x44, true>
{
struct Response_error : Bitfield<1, 1> { };
struct Data_transfer_over : Bitfield<3, 1> { };
struct Command_done : Bitfield<2, 1> { };
struct Data_crc_error : Bitfield<7, 1> { };
struct Response_timeout : Bitfield<8, 1> { };
struct Data_read_timeout : Bitfield<9, 1> { };
};
struct Status : Register<0x48>
{
struct Data_busy : Bitfield<9, 1> { };
};
struct Fifoth : Register<0x4c> { };
struct Bmod : Register<0x80, true>
{
struct Fixed_burst : Bitfield<1, 1> { };
struct Idmac_enable : Bitfield<7, 1> { };
};
struct Pldmnd : Register<0x84> { };
struct Idsts : Register<0x8c> { };
struct Idinten : Register<0x90, true> { };
struct Dbaddr : Register<0x88> { };
struct Clksel : Register<0x9c> { };
struct Emmc_ddr_req : Register<0x10c, true> { };
struct Idmac_desc
{
enum Flags {
NONE = 0,
DIC = 1 << 1,
LD = 1 << 2,
FS = 1 << 3,
CH = 1 << 4,
ER = 1 << 5,
OWN = 1 << 31,
};
unsigned flags;
unsigned bytes;
unsigned addr;
unsigned next;
size_t set(size_t block_count,
size_t block_size,
addr_t phys_addr,
Flags flag);
};
struct Clock_regulator
{
Regulator::Connection regulator;
Clock_regulator(Env &env) : regulator(env, Regulator::CLK_MMC0) {
regulator.state(true); }
};
struct Timer_delayer : Timer::Connection, Mmio::Delayer
{
Timer_delayer(Genode::Env &env) : Timer::Connection(env) { }
void usleep(uint64_t us) override { Timer::Connection::usleep(us); }
};
struct Block_transfer
{
Block::Packet_descriptor packet { };
bool pending = false;
};
Env &_env;
Timer_delayer _delayer { _env };
Block_transfer _block_transfer { };
Clock_regulator _clock_regulator { _env };
Signal_handler<Driver> _irq_handler { _env.ep(), *this, &Driver::_handle_irq };
Irq_connection _irq { _env, Exynos5::SDMMC0_IRQ };
Attached_ram_dataspace _idmac_desc_ds { _env.ram(), _env.rm(),
IDMAC_DESC_MAX_ENTRIES * sizeof(Idmac_desc),
UNCACHED };
Idmac_desc *const _idmac_desc { _idmac_desc_ds.local_addr<Idmac_desc>() };
addr_t const _idmac_desc_phys { Dataspace_client(_idmac_desc_ds.cap())
.phys_addr() };
Card_info _card_info { _init() };
bool _reset();
void _reset_fifo();
void _disable_irq();
bool _update_clock_registers();
bool _setup_bus(unsigned clock_div);
void _handle_irq();
Card_info _init();
bool _setup_idmac_descriptor_table(size_t block_count,
addr_t phys_addr);
/*********************
** Host_controller **
*********************/
bool _issue_command(Command_base const &command) override;
Cid _read_cid() override ;
Csd _read_csd() override ;
size_t _read_ext_csd() override;
unsigned _read_rca() override { return 0; }
Card_info card_info() const override { return _card_info; }
public:
using Block::Driver::read;
using Block::Driver::write;
Driver(Env &env);
/*******************
** Block::Driver **
*******************/
void read_dma(Block::sector_t block_number,
size_t block_count,
addr_t buf_phys,
Block::Packet_descriptor &pkt) override;
void write_dma(Block::sector_t block_number,
size_t block_count,
addr_t buf_phys,
Block::Packet_descriptor &pkt) override;
bool dma_enabled() override { return true; }
Ram_dataspace_capability alloc_dma_buffer(size_t size) override {
return _env.ram().alloc(size, UNCACHED); }
};
#endif /* _DRIVER_H_ */

5
repos/os/src/drivers/sd_card/spec/exynos5/target.mk
View File

@ -1,5 +0,0 @@
TARGET = exynos5_sd_card_drv
REQUIRES = arm_v7
INC_DIR = $(call select_from_repositories,include/spec/exynos5)
include $(REP_DIR)/src/drivers/sd_card/target.inc

4
repos/os/src/drivers/uart/spec/arndale/target.mk
View File

@ -1,4 +0,0 @@
TARGET = arndale_uart_drv
REQUIRES = arm_v7
include $(REP_DIR)/src/drivers/uart/target.inc

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