85 lines
2.5 KiB
C++
85 lines
2.5 KiB
C++
/*
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* \brief Parts of platform that are specific to Arndale
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <spec/arm/cortex_a7_a15_virtualization.h>
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#include <platform.h>
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extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
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static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
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using namespace Board;
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Bootstrap::Platform::Board::Board()
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: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
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core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
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Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
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Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
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static inline void switch_to_supervisor_mode()
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{
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using Cpsr = Hw::Arm_cpu::Psr;
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Cpsr::access_t cpsr = 0;
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Cpsr::M::set(cpsr, Cpsr::M::SVC);
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Cpsr::F::set(cpsr, 1);
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Cpsr::I::set(cpsr, 1);
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asm volatile (
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"msr sp_svc, sp \n" /* copy current mode's sp */
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"msr lr_svc, lr \n" /* copy current mode's lr */
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"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
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"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
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"msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */
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"adr lr, 1f \n" /* load exception return address */
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"eret \n" /* exception return */
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"1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack));
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}
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unsigned Bootstrap::Platform::enable_mmu()
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{
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static volatile bool primary_cpu = true;
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static unsigned long timer_freq = 24000000;
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/* locally initialize interrupt controller */
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::Board::Pic pic { };
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volatile unsigned long * mct_control = (unsigned long*) 0x101C0240;
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*mct_control = 0x100;
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prepare_nonsecure_world(timer_freq);
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prepare_hypervisor((addr_t)core_pd->table_base);
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switch_to_supervisor_mode();
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Cpu::Sctlr::init();
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Cpu::Cpsr::init();
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/* primary cpu wakes up all others */
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if (primary_cpu && NR_OF_CPUS > 1) {
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Cpu::invalidate_data_cache();
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primary_cpu = false;
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Cpu::wake_up_all_cpus(&_start_setup_stack);
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}
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Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
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}
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void Board::Cpu::wake_up_all_cpus(void * const ip)
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{
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*(void * volatile *)Board::IRAM_BASE = ip;
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asm volatile("dsb; sev;");
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}
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