f842c92ee1
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685 |
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arm | ||
arm_v6 | ||
arm_v7 | ||
arm_v8 | ||
arndale | ||
cortex_a8 | ||
cortex_a9 | ||
cortex_a15 | ||
imx6q_sabrelite | ||
imx7d_sabre | ||
imx8q_evk | ||
imx53_qsb | ||
nit6_solox | ||
odroid_xu | ||
panda | ||
pbxa9 | ||
riscv | ||
rpi | ||
rpi3 | ||
usb_armory | ||
wand_quad | ||
x86_64 | ||
zynq_qemu |