f842c92ee1
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685 |
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.. | ||
hw | ||
kernel | ||
spec | ||
capability.cc | ||
core_log_out.cc | ||
core_region_map.cc | ||
cpu_session_support.cc | ||
cpu_thread_allocator.h | ||
env.cc | ||
io_mem_session_support.cc | ||
irq_session_component.cc | ||
irq_session_component.h | ||
kernel_log.cc | ||
map_local.h | ||
native_pd_component.cc | ||
native_pd_component.h | ||
native_utcb.cc | ||
object.h | ||
pager.cc | ||
pager.h | ||
platform_pd.cc | ||
platform_pd.h | ||
platform_thread.cc | ||
platform_thread.h | ||
platform.cc | ||
platform.h | ||
ram_dataspace_support.cc | ||
region_map_support.cc | ||
rpc_cap_factory.h | ||
signal_broker.h | ||
signal_source_component.h | ||
stack_area_addr.cc | ||
thread_start.cc | ||
util.h | ||
vm_session_component.cc | ||
vm_session_component.h |