39 lines
1.3 KiB
C++
39 lines
1.3 KiB
C++
/*
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* \brief Memory barrier
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* \author Martin Stein
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* \date 2014-11-12
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*
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* The memory barrier prevents memory accesses from being reordered in such a
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* way that accesses to the guarded resource get outside the guarded stage. As
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* cmpxchg() defines the start of the guarded stage it also represents an
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* effective memory barrier.
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*
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* On ARM, the architectural memory model allows not only that memory accesses
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* take local effect in another order as their program order but also that
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* different observers (components that can access memory like data-busses,
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* TLBs and branch predictors) observe these effects each in another order.
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* Thus, achieving a correct program order via a compiler memory-barrier isn't
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* sufficient for a correct observation order. An additional architectural
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* preservation of the memory barrier is needed.
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*/
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/*
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* Copyright (C) 2014 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ARM_V6__CPU__MEMORY_BARRIER_H_
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#define _INCLUDE__ARM_V6__CPU__MEMORY_BARRIER_H_
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namespace Genode {
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static inline void memory_barrier()
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{
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asm volatile ("mcr p15, 0, r0, c7, c10, 5" ::: "memory");
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}
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}
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#endif /* _INCLUDE__ARM_V6__CPU__MEMORY_BARRIER_H_ */
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