237 lines
6.1 KiB
ArmAsm
237 lines
6.1 KiB
ArmAsm
/*
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* \brief Transition between kernel and userland
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* \author Martin stein
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* \date 2011-11-15
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* core includes */
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.include "macros.s"
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/***************
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** Constants **
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***************/
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/* size of local variables */
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.set BUFFER_SIZE, 1 * 4
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/************
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** Macros **
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************/
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/**
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* Invalidate all entries of the branch prediction cache
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*
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* FIXME branch prediction shall not be activated for now because we have no
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* support for instruction barriers. The manual says that one should
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* implement this via 'swi 0xf00000', but when we do this in SVC mode it
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* pollutes our SP and this is not acceptable with the current mode
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* transition implementation
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*/
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.macro _flush_branch_predictor
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mcr p15, 0, sp, c7, c5, 6
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/*swi 0xf00000 */
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.endm
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/**
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* Switch from an interrupted user context to a kernel context
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*
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* \param exception_type immediate exception type ID
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* \param pc_adjust immediate value that gets subtracted from the
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* user PC before it gets saved
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*/
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.macro _user_to_kernel_pic exception_type, pc_adjust
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/*
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* We expect that privileged modes are never interrupted by an
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* exception. Thus we can assume that we always come from
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* user mode at this point.
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*/
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/************************************************
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** We're still in the user protection domain, **
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** so we must avoid access to kernel memory **
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************************************************/
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/* load kernel cidr */
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adr sp, _mt_master_context_begin
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ldr sp, [sp, #CIDR_OFFSET]
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mcr p15, 0, sp, c13, c0, 1
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_flush_branch_predictor
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/* load kernel ttbr0 */
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adr sp, _mt_master_context_begin
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ldr sp, [sp, #TTBR0_OFFSET]
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mcr p15, 0, sp, c2, c0, 0
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_flush_branch_predictor
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/*******************************************
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** Now it's save to access kernel memory **
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*******************************************/
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/* get user context pointer */
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ldr sp, _mt_client_context_ptr
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/*
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* Save user r0 ... r12. We explicitely target user registers
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* via '^' because we might be in FIQ exception-mode where
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* some of them are banked. Doesn't affect other modes.
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*/
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stmia sp, {r0-r12}^
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/* save user lr and sp */
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add r0, sp, #SP_OFFSET
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stmia r0, {sp,lr}^
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/* adjust and save user pc */
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.if \pc_adjust != 0
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sub lr, lr, #\pc_adjust
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.endif
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str lr, [sp, #PC_OFFSET]
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/* save user psr */
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mrs r0, spsr
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str r0, [sp, #PSR_OFFSET]
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/* save type of exception that interrupted the user */
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mov r0, #\exception_type
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str r0, [sp, #EXCEPTION_TYPE_OFFSET]
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/*
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* Switch to supervisor mode
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*
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* FIXME This is done due to incorrect behavior when running the kernel
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* high-level-code in FIQ-exception mode. Please debug this behavior
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* and remove this switch.
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*/
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cps #19
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/* apply kernel sp */
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adr r0, _mt_master_context_begin
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_restore_kernel_sp r0, r1, r2
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/* load kernel context */
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add r0, r0, #LR_OFFSET
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ldm r0, {lr, pc}
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.endm
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/**********************************
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** Linked into the text section **
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**********************************/
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.section .text
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/*
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* Page aligned base of mode transition code.
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*
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* This position independent code switches between a kernel context and a
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* user context and thereby between their address spaces. Due to the latter
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* it must be mapped executable to the same region in every address space.
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* To enable such switching, the kernel context must be stored within this
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* region, thus one should map it solely accessable for privileged modes.
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*/
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.p2align MIN_PAGE_SIZE_LOG2
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.global _mt_begin
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_mt_begin:
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/*
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* On user exceptions the CPU has to jump to one of the following
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* seven entry vectors to switch to a kernel context.
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*/
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.global _mt_kernel_entry_pic
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_mt_kernel_entry_pic:
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b _rst_entry /* 0x00: reset */
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b _und_entry /* 0x04: undefined instruction */
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b _swi_entry /* 0x08: software interrupt */
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b _pab_entry /* 0x0c: prefetch abort */
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b _dab_entry /* 0x10: data abort */
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nop /* 0x14: reserved */
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b _irq_entry /* 0x18: interrupt request */
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b _fiq_entry /* 0x1c: fast interrupt request */
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/* PICs that switch from a user exception to the kernel */
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_rst_entry: _user_to_kernel_pic RST_TYPE, RST_PC_ADJUST
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_und_entry: _user_to_kernel_pic UND_TYPE, UND_PC_ADJUST
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_swi_entry:
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/*
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* FIXME fast SWI routines pollute the SVC SP but we have
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* to call them especially in SVC mode
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*/
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/* check if SWI requests a fast service routine */
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/*ldr sp, [r14, #-0x4]*/
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/*and sp, sp, #0xffffff*/
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/* fast "instruction barrier" service routine */
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/*cmp sp, #0xf00000*/
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/*bne _slow_swi_entry*/
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/*movs pc, r14*/
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/* slow high level service routine */
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_slow_swi_entry: _user_to_kernel_pic SVC_TYPE, SVC_PC_ADJUST
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_pab_entry: _user_to_kernel_pic PAB_TYPE, PAB_PC_ADJUST
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_dab_entry: _user_to_kernel_pic DAB_TYPE, DAB_PC_ADJUST
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_irq_entry: _user_to_kernel_pic IRQ_TYPE, IRQ_PC_ADJUST
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_fiq_entry: _user_to_kernel_pic FIQ_TYPE, FIQ_PC_ADJUST
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/* kernel must jump to this point to switch to a user context */
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.p2align 2
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.global _mt_user_entry_pic
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_mt_user_entry_pic:
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/* get user context pointer */
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ldr lr, _mt_client_context_ptr
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/* buffer user pc */
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ldr r0, [lr, #PC_OFFSET]
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adr r1, _mt_buffer
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str r0, [r1]
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/* buffer user psr */
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ldr r0, [lr, #PSR_OFFSET]
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msr spsr_cxsf, r0
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/* load user r0 ... r12 */
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ldm lr, {r0-r12}
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/* load user sp and lr */
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add sp, lr, #SP_OFFSET
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ldm sp, {sp,lr}^
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/* get user cidr and ttbr0 */
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ldr sp, [lr, #CIDR_OFFSET]
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ldr lr, [lr, #TTBR0_OFFSET]
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/********************************************************
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** From now on, until we leave kernel mode, we must **
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** avoid access to memory that is not mapped globally **
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********************************************************/
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/* apply user contextidr and section table */
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mcr p15, 0, sp, c13, c0, 1
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mcr p15, 0, lr, c2, c0, 0
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_flush_branch_predictor
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/* load user pc (implies application of the user psr) */
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adr lr, _mt_buffer
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ldm lr, {pc}^
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_mt_local_variables
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.p2align 2
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.global _mt_end
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_mt_end:
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