60a7fe5586
Previously we did write the SPSR via an MSR instruction without additional flags. Unfortunately, this tells the CPU to write the register only partially. This often isn't a problem as the users PSR reset value normally is conform to our expectations but in some cases (e.g. PSR endianess bit on WandBoard core #4) the reset value is bad. Thus, we have to add the CXSF flags (access Control + eXtension + Status + Flags) so the CPU overwrites the entire register. Fixes #2254
283 lines
7.6 KiB
ArmAsm
283 lines
7.6 KiB
ArmAsm
/*
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* \brief Transition between kernel/userland, and secure/non-secure world
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2011-11-15
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* core includes */
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.include "macros.s"
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/* size of local variables */
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.set BUFFER_SIZE, 3 * 4
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/************
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** Macros **
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************/
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/**
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* Determine the base of the globally mapped buffer of the executing CPU
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*
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* \param target_reg register that shall receive the base pointer
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* \param buf_reg register that can be polluted by the macro
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*/
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.macro _get_buffer_ptr target_reg, buf_reg
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/* get kernel name of CPU */
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_get_cpu_id \buf_reg
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/* multiply CPU name with buffer size to get offset of buffer */
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mov \target_reg, #BUFFER_SIZE
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mul \buf_reg, \buf_reg, \target_reg
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/* get base of the buffer array */
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adr \target_reg, _mt_buffer
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/* add offset and base to get CPU-local buffer */
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add \target_reg, \target_reg, \buf_reg
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.endm
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/**
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* Save an interrupted user context and switch to the kernel context
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*
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* \param exception_type kernel name of exception type
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* \param pc_adjust value that gets subtracted from saved user PC
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*/
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.macro _user_to_kernel_pic exception_type, pc_adjust
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/* disable fast interrupts when not in fast-interrupt mode */
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.if \exception_type != FIQ_TYPE
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cpsid f
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.endif
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/*
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* The sp in svc mode still contains the base of the globally mapped buffer
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* of this CPU. Hence go to svc mode, buffer user r0-r2, and make
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* buffer pointer available to all modes
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*/
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.if \exception_type != RST_TYPE && \exception_type != SVC_TYPE
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cps #SVC_MODE
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.endif
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stm sp, {r0-r2}^
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mov r0, sp
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/* switch back to previous privileged mode */
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.if \exception_type == UND_TYPE
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cps #UND_MODE
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.endif
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.if \exception_type == PAB_TYPE
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cps #ABT_MODE
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.endif
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.if \exception_type == DAB_TYPE
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cps #ABT_MODE
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.endif
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.if \exception_type == IRQ_TYPE
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cps #IRQ_MODE
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.endif
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.if \exception_type == FIQ_TYPE
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cps #FIQ_MODE
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.endif
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/* switch to kernel protection-domain */
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adr sp, _mt_master_context_begin
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add sp, #TRANSIT_TTBR0_OFFSET
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ldm sp, {r1, r2, sp}
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_switch_protection_domain r1, r2, sp
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/* get user context-pointer */
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_get_client_context_ptr sp, r1, _mt_client_context_ptr
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/* adjust and save user pc */
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.if \pc_adjust != 0
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sub lr, lr, #\pc_adjust
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.endif
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str lr, [sp, #PC_OFFSET]
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/* restore user r0-r2 from buffer and save user r0-r12 */
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mov lr, r0
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ldm lr, {r0-r2}
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stm sp, {r0-r12}^
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/* save user sp and user lr */
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add r0, sp, #SP_OFFSET
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stm r0, {sp, lr}^
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/* get user psr and type of exception that interrupted the user */
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mrs r0, spsr
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mov r1, #\exception_type
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b _common_user_to_kernel_pic
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.endm /* _user_to_kernel_pic */
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/**********************************
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** Linked into the text section **
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**********************************/
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.section .text
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/*
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* Page aligned base of mode transition code.
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*
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* This position independent code switches between a kernel context and a
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* user context and thereby between their address spaces. Due to the latter
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* it must be mapped executable to the same region in every address space.
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* To enable such switching, the kernel context must be stored within this
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* region, thus one should map it solely accessable for privileged modes.
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*/
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.p2align MIN_PAGE_SIZE_LOG2
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.global _mt_begin
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_mt_begin:
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/*
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* On user exceptions the CPU has to jump to one of the following
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* seven entry vectors to switch to a kernel context.
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*/
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.global _mt_kernel_entry_pic
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_mt_kernel_entry_pic:
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/***********************
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** Exception entries **
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***********************/
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b _rst_entry /* 0x00: reset */
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b _und_entry /* 0x04: undefined instruction */
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b _svc_entry /* 0x08: supervisor call */
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b _pab_entry /* 0x0c: prefetch abort */
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b _dab_entry /* 0x10: data abort */
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nop /* 0x14: reserved */
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b _irq_entry /* 0x18: interrupt request */
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/******************************************************
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** Entry for fast interrupt requests at offset 0x1c **
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******************************************************/
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/* load the saved PSR of the the previous mode */
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mrs r8, spsr
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/* get the M bitfield from the read PSR value */
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and r9, r8, #0b11111
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/* skip following instructions if previous mode was user mode */
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cmp r9, #USR_MODE
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beq 1f
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/*
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* If we reach this point, the previous mode was not the user
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* mode, meaning an exception entry has been preempted by this
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* fast interrupt before it could disable fast interrupts.
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*/
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/* disable fast interrupts in PSR value of previous mode */
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orr r8, #0b1000000
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/* apply PSR of previous mode */
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msr spsr_cxsf, r8
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/*
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* Resume excecution of previous exception entry leaving the fast
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* interrupt unhandled till fast interrupts get enabled again.
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*/
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subs pc, lr, #4
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/* switch to kernel to handle the fast interrupt */
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1:
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_user_to_kernel_pic FIQ_TYPE, FIQ_PC_ADJUST
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/***************************************************************
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** Code that switches from a non-FIQ exception to the kernel **
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***************************************************************/
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_rst_entry: _user_to_kernel_pic RST_TYPE, RST_PC_ADJUST
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_und_entry: _user_to_kernel_pic UND_TYPE, UND_PC_ADJUST
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_svc_entry: _user_to_kernel_pic SVC_TYPE, SVC_PC_ADJUST
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_pab_entry: _user_to_kernel_pic PAB_TYPE, PAB_PC_ADJUST
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_dab_entry: _user_to_kernel_pic DAB_TYPE, DAB_PC_ADJUST
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_irq_entry: _user_to_kernel_pic IRQ_TYPE, IRQ_PC_ADJUST
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/**************************************************************
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** Kernel-entry code that is common for all user exceptions **
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**************************************************************/
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_common_user_to_kernel_pic:
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/* save user psr and type of exception that interrupted the user */
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add sp, sp, #PSR_OFFSET
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stm sp, {r0, r1}
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/*
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* Clear exclusive access in local monitor,
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* as we use strex/ldrex in our cmpxchg method, we've to do this during
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* a context switch (ARM Reference Manual paragraph 3.4.4.)
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*/
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clrex
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/*
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* Switch to supervisor mode to circumvent incorrect behavior of
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* kernel high-level code in fast interrupt mode and to ensure that
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* we're in svc mode at kernel exit. The latter is because kernel
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* exit stores a buffer pointer into its banked sp that is also
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* needed by the subsequent kernel entry.
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*/
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cps #SVC_MODE
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/* apply kernel sp */
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adr r0, _mt_master_context_begin
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_restore_kernel_sp r0, r1, r2
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/* apply kernel lr and kernel pc */
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add r1, r0, #LR_OFFSET
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ldm r1, {lr, pc}
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_mt_local_variables
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/****************************************************************
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** Code that switches from a kernel context to a user context **
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****************************************************************/
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.p2align 2
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.global _mt_user_entry_pic
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_mt_user_entry_pic:
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/* get user context and globally mapped buffer of this CPU */
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_get_client_context_ptr lr, r0, _mt_client_context_ptr
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_get_buffer_ptr sp, r0
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/* load user psr in spsr */
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ldr r0, [lr, #PSR_OFFSET]
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msr spsr_cxsf, r0
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/* apply banked user sp, banked user lr, and user r0-r12 */
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add r0, lr, #SP_OFFSET
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ldm r0, {sp, lr}^
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ldm lr, {r0-r12}^
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/* buffer user r0-r1, and user pc */
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stm sp, {r0, r1}
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ldr r0, [lr, #PC_OFFSET]
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str r0, [sp, #2*4]
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/* switch to user protection-domain */
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adr r0, _mt_master_context_begin
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ldr r0, [r0, #TRANSIT_TTBR0_OFFSET]
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add lr, lr, #CIDR_OFFSET
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ldm lr, {r1, lr}
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_switch_protection_domain r0, r1, lr
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/* apply user r0-r1 and user pc which implies application of spsr */
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ldm sp, {r0, r1, pc}^
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/* end of the mode transition code */
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.global _mt_end
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_mt_end:
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