hw & arm: write whole SPSR in mode transition

Previously we did write the SPSR via an MSR instruction without
additional flags. Unfortunately, this tells the CPU to write the
register only partially. This often isn't a problem as the users PSR
reset value normally is conform to our expectations but in some cases
(e.g. PSR endianess bit on WandBoard core #4) the reset value is bad.
Thus, we have to add the CXSF flags (access Control + eXtension + Status
+ Flags) so the CPU overwrites the entire register.

Fixes #2254

repos/base-hw/src/core/spec/arm_v6/mode_transition.s

@@ -202,7 +202,7 @@
 
 	/* buffer user psr */
 	ldr r0, [lr, #PSR_OFFSET]
-	msr spsr, r0
+	msr spsr_cxsf, r0
 
 	/* load user r0 ... r12 */
 	ldm lr, {r0-r12}

repos/base-hw/src/core/spec/arm_v7/mode_transition.s

@@ -182,7 +182,7 @@
 	orr r8, #0b1000000
 
 	/* apply PSR of previous mode */
-	msr spsr, r8
+	msr spsr_cxsf, r8
 
 	/*
 	 * Resume excecution of previous exception entry leaving the fast
@@ -255,7 +255,7 @@
 
 	/* load user psr in spsr */
 	ldr r0, [lr, #PSR_OFFSET]
-	msr spsr, r0
+	msr spsr_cxsf, r0
 
 	/* apply banked user sp, banked user lr, and user r0-r12 */
 	add r0, lr, #SP_OFFSET