Mark Vels 1668983efa base-hw: RISC-V Rocket Core on Zynq ... This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880		2016-02-26 11:36:51 +01:00
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arm	hw: make 'smp' property an aspect (Ref #1312)	2016-01-15 16:42:12 +01:00
arm_v6	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
arm_v7
arndale	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
cortex_a8	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
cortex_a9	hw: re-implement lazy FPU context switch	2016-01-26 16:20:38 +01:00
cortex_a15	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
exynos5
imx6
imx53
imx53_qsb
muen
odroid_xu	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
panda
pbxa9	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
perf_counter
riscv	base-hw: RISC-V Rocket Core on Zynq	2016-02-26 11:36:51 +01:00
rpi
smp	hw: enable SMP for ARM Cortex A9	2016-01-26 16:20:18 +01:00
trustzone
usb_armory
x86	hw: re-implement lazy FPU context switch	2016-01-26 16:20:38 +01:00
x86_64	hw_x86_64: do not reference any muen specifics	2016-01-26 16:20:47 +01:00
zynq