41 lines
1.2 KiB
C++
41 lines
1.2 KiB
C++
/*
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* \brief Translation table definitions for core
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2012-02-22
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__CORTEX_A8__TRANSLATION_TABLE_H_
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#define _CORE__SPEC__CORTEX_A8__TRANSLATION_TABLE_H_
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#include <hw/spec/arm/page_table.h>
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#include <kernel/interface.h>
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#include <cpu.h>
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constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() {
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return 2; }
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constexpr bool Hw::Page_table::Descriptor_base::_smp() { return false; }
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void Hw::Page_table::_translation_added(unsigned long addr, unsigned long size)
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{
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/*
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* The Cortex-A8 CPU can't use the L1 cache on page-table
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* walks. Therefore, as the page-tables lie in write-back cacheable
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* memory we've to clean the corresponding cache-lines even when a
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* page table entry is added. We only do this as core as the kernel
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* adds translations solely before MMU and caches are enabled.
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*/
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Genode::Cpu::clean_data_cache_by_virt_region(addr, size);
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}
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#endif /* _CORE__SPEC__CORTEX_A8__TRANSLATION_TABLE_H_ */
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