7 Commits

Author	SHA1	Message	Date
Stefan Kalkowski	f0fae2a5f2	hw: set TTBR0 according to CPU facilities ... Fixes #1195	2014-10-10 13:02:30 +02:00
Martin Stein	14e9a89cba	hw: no superfluous ORing of zeros and clean up ... fix #710	2014-08-15 10:19:49 +02:00
Martin Stein	9da42dde2f	hw & arm_v7: mode transition via transit ttbr0 ... Previously, we did the protection-domain switches without a transitional translation table that contains only global mappings. This was fine as long as the CPU did no speculative memory accesses. However, to enabling branch prediction triggers such accesses. Thus, if we don't want to invalidate predictors on every context switch, we need to switch more carefully. ref #474	2014-08-15 10:19:48 +02:00
Martin Stein	03cd76821c	hw & arm: exceptions to asserts in transl. table ... ref #474	2014-08-15 10:19:48 +02:00
Martin Stein	d48d0e7b43	hw: rename processor CPU ... fix #1217	2014-08-15 10:19:48 +02:00
Martin Stein	1cba71208f	hw: cpu_support to kernel/thread_base ... ref #1217	2014-08-15 10:19:48 +02:00
Martin Stein	a5cf09fa6e	hw: re-organize file structure ... fix #1197	2014-08-15 10:19:48 +02:00