Commit Graph

11 Commits

Author SHA1 Message Date
Martin Stein
909ab8dcd0 hw: communicate page faults via signals
Enable routing of thread events to signal contexts via
Kernel::route_thread_event.

Replace Kernel::set_pager by Kernel::route_thread_event.

In base-hw a pager object is a signal context and a pager activation
is a signal receiver. If a thread wants to start communicating its page
faults via a pager object, the thread calls Kernel::route_thread_event with
its thread ID, event ID "FAULT", and the signal context ID of the pager object.
If a pager activation wants to start handling page faults of a pager object,
the pager activation assigns the corresponding signal context to its signal
receiver. If a pager activation wants to stop handling page faults of a pager
object, the pager activation dissolves the corresponding signal context from
its signal receiver. If a thread wants to start communicating its page faults
via a pager object, the thread calls Kernel::route_thread_event with its
thread ID, event ID "FAULT", and the invalid signal context ID.

Remove Kernel::resume_faulter.

Move all page fault related code from generic kernel sources to CPU
specific cpu_support.h and cpu_support.cc.

fix #935
2013-11-14 19:57:31 +01:00
Martin Stein
da49f86f5b hw: provide placement via dedicated header
ref #935
2013-11-14 19:57:30 +01:00
Martin Stein
de87fa1b5c hw: avoid address overflow in Tlb::remove_region()
ref #589
2013-09-26 15:58:05 +02:00
Norman Feske
65f20262cb base-hw: Enable caches on ARM v6 2013-05-15 20:48:00 +02:00
Norman Feske
d43d9900ab base-hw: Make memory_region_attr CPU-specific
This patch moves the implementation of the 'Arm::memory_region_attr'
function from the generic ARM code to the ARM v6/v7 specific code
to enable the customization of page-table bits depending on the
specific CPU core type. I.e., the ARM1176 apparently does not cope
well with setting the 'Tex::bits(2)' for MMIO mappings.
2013-05-15 20:47:52 +02:00
Norman Feske
71cd7b9d2e base-hw: Avoid early calls of cmpxchg
This patch eliminates calls of 'cmpxchg' prior enabling the MMU. This is
needed because the 'ldrex' and 'strex' instructions do not always work
with MMU and L1 cache disabled, i.e., on Raspberry Pi.
2013-05-15 20:47:46 +02:00
Norman Feske
73ab30c22c Update copyright headers to 2013 2013-01-10 21:44:47 +01:00
Martin Stein
e6ca122fe3 base-hw & arm: write-through cache on uncached RAM
Fix #473
2013-01-08 11:36:52 +01:00
Martin Stein
4fb5c23a3c base-hw: don't use 'long' unnecessarily
Fix #581
2013-01-08 11:36:52 +01:00
Martin Stein
7f2f2d9120 base-hw: ease core build
Merge core only libs into the target make-files.

Use base-hw specific Board drivers that inherit
from generic Board_base.

Use Page_flags::access_t instead of additional
page_flags_t.

Fix #570
2013-01-08 11:36:52 +01:00
Martin Stein
ee6f25a028 base-hw: reorganize core-driver headers
Ref #570
2013-01-08 11:36:51 +01:00