Commit Graph

65 Commits

Author SHA1 Message Date
Stefan Kalkowski
e5b78a6494 hw: disable L2 cache for imx53 platform
Currently the L2 cache for i.MX53 doesn't work correctly in the
hw-kernel, so we temporarily disable it.

Ref #1182
2014-06-26 10:57:27 +02:00
Stefan Kalkowski
786fe805da base: introduce caching attributes (fix #1184)
On ARM it's relevant to not only distinguish between ordinary cached memory
and write-combined one, but also having non-cached memory too. To insert the
appropriated page table entries e.g.: in the base-hw kernel, we need to preserve
the information about the kind of memory from allocation until the pager
resolves a page fault. Therefore, this commit introduces a new Cache_attribute
type, and replaces the write_combined boolean with the new type where necessary.
2014-06-26 10:57:26 +02:00
Stefan Kalkowski
031cabf862 hw: let assembler constants be upper-case (Ref #1180) 2014-06-26 10:57:26 +02:00
Stefan Kalkowski
00ee2b565a hw: define assembler constants in global scope
Don't define assembler constants inside macros, thereby calling the
corresponding macros isn't needed anymore. To prevent having to much
constants included in files where they aren't needed, split macros.s
file into a generic mode_transition.s part, and globally used macros.s.

Fix #1180
2014-06-26 10:57:26 +02:00
Martin Stein
f5fdcc8f1e hw: get a thread cap in Thread_base constructor
Previously this was not done before Thread_base::start(..) in
base-hw as it was not needed to have a valid cap that early. However,
when changing the affinity of a thread we need the cap to be valid
before Thread_base::start(..).

fix #1151
2014-06-26 10:57:26 +02:00
Martin Stein
ccba43574f hw: fix bug in scheduler timing
By now the scheduling timer was only refreshed for a new scheduling timeout
when the choosen scheduling context has changed. But we want it to be refreshed
also when the scheduled context yields without an effect to the schedulers
choice (this is the case e.g. when the idle thread gets a scheduling timeout
or a thread yields without any competitor in its priority band).

ref #1151
2014-06-26 10:57:26 +02:00
Martin Stein
4b7d58fccc hw & cortex_a9: do lazy FPU-context switch
ref #1126
2014-06-26 10:57:25 +02:00
Stefan Kalkowski
05603951b6 hw: enable and maintain outer l2 cache
Fix #1170
2014-06-26 10:57:25 +02:00
Martin Stein
8d145bd80c hw & rpi: provide Pic::MAX_INTERRUPT_ID
fix #1160
2014-06-06 14:54:31 +02:00
Martin Stein
f53e4ff8f5 hw: align kernel stack appropriately
fix #1161
2014-06-06 14:54:31 +02:00
Martin Stein
8d43b67ca6 hw: map binaries of boot modules on demand
fix #1139
2014-06-06 14:54:31 +02:00
Christian Helmuth
06a10b3695 hw: log "Test succeeded" in nested_init.run 2014-06-06 14:54:30 +02:00
Stefan Kalkowski
7138b2740a hw: fix section insertion in translation tables
Fixes an alignment problem introduced by commit "hw: map core on demand"
where physical address alignment wasn't checked anymore, when inserting
a section within the first-level table of ARM's short translation table
format.

Many thanks to Christian Prochaska for helping to debug the problem.
2014-05-28 12:28:11 +02:00
Christian Prochaska
078883fda3 base: interface for D- and I-cache synchronization
On ARM, when machine instructions get written into the data cache
(for example by a JIT compiler), one needs to make sure that the
instructions get written out to memory and read from memory into
the instruction cache before they get executed. This functionality
is usually provided by a kernel syscall and this patch adds a generic
interface for Genode applications to use it.

Fixes #1153.
2014-05-27 11:14:45 +02:00
Norman Feske
ca971bbfd8 Move repositories to 'repos/' subdirectory
This patch changes the top-level directory layout as a preparatory
step for improving the tools for managing 3rd-party source codes.
The rationale is described in the issue referenced below.

Issue #1082
2014-05-14 16:08:00 +02:00