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hw: beautify flush_data_caches_by_virt_region 

ref #1115
This commit is contained in:
Martin Stein 2014-04-04 17:21:44 +02:00 committed by Norman Feske
parent d67a26ea4c
commit f8c2596259
2 changed files with 25 additions and 11 deletions
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4
base-hw/src/core/kernel/thread.cc
View File

@ -544,8 +544,8 @@ void Thread::_call_update_pd()
void Thread::_call_update_region()
{
/* flush hardware caches */
Processor::flush_data_cache_by_virt_region((addr_t)user_arg_1(),
(size_t)user_arg_2());
Processor::flush_data_caches_by_virt_region((addr_t)user_arg_1(),
(size_t)user_arg_2());
}

32
base-hw/src/core/processor_driver/arm.h
View File

@ -280,6 +280,21 @@ namespace Arm
}
};
/**
* Data Cache Clean by MVA to PoC
*/
struct Dccmvac : Register<32>
{
/**
* Write register value
*/
static void write(access_t const v)
{
asm volatile (
"mcr p15, 0, %[v], c7, c10, 1\n" :: [v] "r" (v) : );
}
};
/**
* Context identification register
*/
@ -639,20 +654,19 @@ namespace Arm
flush_caches();
}
/*
* Clean every data-cache entry within a region via MVA
/**
* Clean every data-cache entry within a virtual region
*/
static void flush_data_cache_by_virt_region(addr_t base, size_t const size)
static void
flush_data_caches_by_virt_region(addr_t base, size_t const size)
{
enum {
CACHE_LINE_SIZE = 1 << Board::CACHE_LINE_SIZE_LOG2,
CACHE_LINE_ALIGNM_MASK = ~(CACHE_LINE_SIZE - 1),
LINE_SIZE = 1 << Board::CACHE_LINE_SIZE_LOG2,
LINE_ALIGNM_MASK = ~(LINE_SIZE - 1),
};
addr_t const top = base + size;
base = base & CACHE_LINE_ALIGNM_MASK;
for (; base < top; base += CACHE_LINE_SIZE)
asm volatile ("mcr p15, 0, %[base], c7, c10, 1\n" /* DCCMVAC */
:: [base] "r" (base) : );
base = base & LINE_ALIGNM_MASK;
for (; base < top; base += LINE_SIZE) { Dccmvac::write(base); }
}
};
}