From f8c2596259cb5fbaac9e6045769831ee6c80f3a3 Mon Sep 17 00:00:00 2001
From: Martin Stein <martin.stein@genode-labs.com>
Date: Fri, 4 Apr 2014 17:21:44 +0200
Subject: [PATCH] hw: beautify flush_data_caches_by_virt_region

ref #1115
---
 base-hw/src/core/kernel/thread.cc       |  4 ++--
 base-hw/src/core/processor_driver/arm.h | 32 ++++++++++++++++++-------
 2 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/base-hw/src/core/kernel/thread.cc b/base-hw/src/core/kernel/thread.cc
index b0a12cd11..daf229509 100644
--- a/base-hw/src/core/kernel/thread.cc
+++ b/base-hw/src/core/kernel/thread.cc
@@ -544,8 +544,8 @@ void Thread::_call_update_pd()
 void Thread::_call_update_region()
 {
 	/* flush hardware caches */
-	Processor::flush_data_cache_by_virt_region((addr_t)user_arg_1(),
-	                                           (size_t)user_arg_2());
+	Processor::flush_data_caches_by_virt_region((addr_t)user_arg_1(),
+	                                            (size_t)user_arg_2());
 }
 
 
diff --git a/base-hw/src/core/processor_driver/arm.h b/base-hw/src/core/processor_driver/arm.h
index 69e11707e..6ea596148 100644
--- a/base-hw/src/core/processor_driver/arm.h
+++ b/base-hw/src/core/processor_driver/arm.h
@@ -280,6 +280,21 @@ namespace Arm
 			}
 		};
 
+		/**
+		 * Data Cache Clean by MVA to PoC
+		 */
+		struct Dccmvac : Register<32>
+		{
+			/**
+			 * Write register value
+			 */
+			static void write(access_t const v)
+			{
+				asm volatile (
+					"mcr p15, 0, %[v], c7, c10, 1\n" :: [v] "r" (v) : );
+			}
+		};
+
 		/**
 		 * Context identification register
 		 */
@@ -639,20 +654,19 @@ namespace Arm
 			flush_caches();
 		}
 
-		/*
-		 * Clean every data-cache entry within a region via MVA
+		/**
+		 * Clean every data-cache entry within a virtual region
 		 */
-		static void flush_data_cache_by_virt_region(addr_t base, size_t const size)
+		static void
+		flush_data_caches_by_virt_region(addr_t base, size_t const size)
 		{
 			enum {
-				CACHE_LINE_SIZE        = 1 << Board::CACHE_LINE_SIZE_LOG2,
-				CACHE_LINE_ALIGNM_MASK = ~(CACHE_LINE_SIZE - 1),
+				LINE_SIZE        = 1 << Board::CACHE_LINE_SIZE_LOG2,
+				LINE_ALIGNM_MASK = ~(LINE_SIZE - 1),
 			};
 			addr_t const top = base + size;
-			base = base & CACHE_LINE_ALIGNM_MASK;
-			for (; base < top; base += CACHE_LINE_SIZE)
-				asm volatile ("mcr p15, 0, %[base], c7, c10, 1\n" /* DCCMVAC */
-				              :: [base] "r" (base) : );
+			base = base & LINE_ALIGNM_MASK;
+			for (; base < top; base += LINE_SIZE) { Dccmvac::write(base); }
 		}
 	};
 }