Extend clock and power units in platform driver
* Add clock and power management for SATA and USB3.0 for Arndale Fix #771
This commit is contained in:
Stefan Kalkowski
Norman Feske
parent
1d34589f84
commit
f7034369b2
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@ -32,7 +32,10 @@ namespace Genode
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MMIO_0_SIZE = 0x10000000,
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CMU_MMIO_BASE = 0x10010000,
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CMU_MMIO_SIZE = 0x21000,
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CMU_MMIO_SIZE = 0x24000,
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PMU_MMIO_BASE = 0x10040000,
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PMU_MMIO_SIZE = 0x5000,
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/* interrupt controller */
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GIC_CPU_MMIO_BASE = 0x10480000,
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@ -20,6 +20,10 @@ namespace Regulator {
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enum Regulator_id {
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CLK_CPU,
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CLK_SATA,
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CLK_USB30,
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PWR_SATA,
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PWR_USB30,
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MAX,
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INVALID
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};
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@ -30,7 +34,11 @@ namespace Regulator {
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};
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Regulator_name names[] = {
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{ CLK_CPU, "clock-cpu" },
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{ CLK_CPU, "clock-cpu" },
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{ CLK_SATA, "clock-sata" },
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{ CLK_USB30, "clock-usb3.0" },
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{ PWR_SATA, "power-sata" },
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{ PWR_USB30, "power-usb3.0" },
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};
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Regulator_id regulator_id_by_name(const char * name)
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@ -17,52 +17,45 @@
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#include <regulator/consts.h>
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#include <regulator/driver.h>
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#include <drivers/board_base.h>
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#include <os/attached_io_mem_dataspace.h>
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#include <util/mmio.h>
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#include <os/attached_mmio.h>
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using namespace Regulator;
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class Cmu : public Regulator::Driver,
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public Genode::Attached_io_mem_dataspace,
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public Genode::Mmio
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public Genode::Attached_mmio
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{
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private:
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static const Genode::uint16_t m_values[]; /* M values for frequencies */
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static const Genode::uint8_t p_values[]; /* P values for frequencies */
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static const Genode::uint8_t s_values[]; /* S values for frequencies */
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template <unsigned OFF>
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struct Pll_lock : Register<OFF, 32>
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{
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struct Pll_locktime : Register<OFF, 32>::template Bitfield<0, 20> { };
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static Genode::uint32_t max_lock_time(Genode::uint8_t pdiv) {
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return pdiv * 250; };
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};
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template <unsigned OFF>
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struct Pll_con0 : Register<OFF, 32>
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{
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struct S : Register<OFF, 32>::template Bitfield < 0, 3> { };
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struct P : Register<OFF, 32>::template Bitfield < 8, 6> { };
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struct M : Register<OFF, 32>::template Bitfield <16, 10> { };
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struct Locked : Register<OFF, 32>::template Bitfield <29, 1> { };
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};
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/***********************
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** CMU CPU registers **
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***********************/
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struct Apll_lock : Register<0x000, 32>
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{
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struct Pll_locktime : Bitfield <0, 20> { };
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static access_t max_lock_time(access_t pdiv) { return pdiv * 250; };
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};
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struct Apll_con0 : Register<0x100, 32>
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{
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struct S : Bitfield <0, 3>
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{
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/* S values for frequencies 200 - 1700 */
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static const Genode::uint8_t values[];
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};
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struct P : Bitfield <8, 6>
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{
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/* P values for frequencies 200 - 1700 */
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static const Genode::uint8_t values[];
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};
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struct M : Bitfield <16, 10>
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{
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/* M values for frequencies 200 - 1700 */
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static const Genode::uint16_t values[];
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};
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struct Locked : Bitfield <29, 1> { };
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};
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typedef Pll_lock<0> Apll_lock;
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typedef Pll_con0<0x100> Apll_con0;
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struct Clk_src_cpu : Register<0x200, 32>
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{
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@ -128,10 +121,81 @@ class Cmu : public Regulator::Driver,
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}
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};
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typedef Pll_lock<0x4000> Mpll_lock;
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typedef Pll_con0<0x4100> Mpll_con0;
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struct Clk_src_core1 : Register<0x4204, 32>
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{
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struct Mux_mpll_sel : Bitfield<8, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
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};
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/***********************
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** CMU TOP registers **
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***********************/
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struct Clk_src_top2 : Register<0x10218, 32>
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{
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struct Mux_mpll_user_sel : Bitfield<20, 1> { enum { XXTI, MOUT_MPLL}; };
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};
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struct Clk_src_fsys : Register<0x10244, 32>
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{
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struct Sata_sel : Bitfield<24, 1> {
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enum { SCLK_MPLL_USER, SCLK_BPLL_USER }; };
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struct Usbdrd30_sel : Bitfield<28, 1> {
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enum { SCLK_MPLL_USER, SCLK_CPLL }; };
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};
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struct Clk_src_mask_fsys : Register<0x10340, 32>
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{
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struct Sata_mask : Bitfield<24, 1> { enum { MASK, UNMASK }; };
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struct Usbdrd30_mask : Bitfield<28, 1> { enum { MASK, UNMASK }; };
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};
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struct Clk_div_fsys0 : Register<0x10548, 32>
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{
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struct Sata_ratio : Bitfield<20, 4> { };
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struct Usbdrd30_ratio : Bitfield<24, 4> { };
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};
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struct Clk_div_stat_fsys0 : Register<0x10648, 32>
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{
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struct Div_sata : Bitfield<20, 1> {};
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struct Div_usbdrd30 : Bitfield<24, 1> {};
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};
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struct Clk_gate_ip_fsys : Register<0x10944, 32>
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{
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struct Pdma0 : Bitfield<1, 1> { };
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struct Pdma1 : Bitfield<2, 1> { };
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struct Sata : Bitfield<6, 1> { };
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struct Usbdrd30 : Bitfield<19, 0> { };
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struct Sata_phy_ctrl : Bitfield<24, 1> { };
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struct Sata_phy_i2c : Bitfield<25, 1> { };
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};
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/*************************
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** CMU CDREX registers **
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*************************/
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typedef Pll_lock<0x20010> Bpll_lock;
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typedef Pll_con0<0x20110> Bpll_con0;
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struct Pll_div2_sel : Register<0x20a24, 32>
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{
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struct Mpll_fout_sel : Bitfield<4, 1> {
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enum { MPLL_FOUT_HALF, MPLL_FOUT }; };
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};
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/*******************
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** CPU functions **
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*******************/
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Cpu_clock_freq _cpu_freq;
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/**
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* CPU frequency scaling function
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*/
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void _cpu_clk_freq(Cpu_clock_freq freq)
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{
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/**
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@ -157,13 +221,13 @@ class Cmu : public Regulator::Driver,
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!= Clk_mux_stat_cpu::Cpu_sel::SCLK_MPLL) ;
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/* set lock time */
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unsigned pdiv = Apll_con0::P::values[freq];
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unsigned pdiv = p_values[freq];
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write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
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/* change P, M, S values of APLL */
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write<Apll_con0::P>(Apll_con0::P::values[freq]);
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write<Apll_con0::M>(Apll_con0::M::values[freq]);
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write<Apll_con0::S>(Apll_con0::S::values[freq]);
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write<Apll_con0::P>(p_values[freq]);
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write<Apll_con0::M>(m_values[freq]);
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write<Apll_con0::S>(s_values[freq]);
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while (!read<Apll_con0::Locked>()) ;
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@ -171,6 +235,80 @@ class Cmu : public Regulator::Driver,
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write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::MOUT_APLL);
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while (read<Clk_mux_stat_cpu::Cpu_sel>()
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!= Clk_mux_stat_cpu::Cpu_sel::MOUT_APLL) ;
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_cpu_freq = freq;
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}
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/********************
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** SATA functions **
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********************/
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void _sata_enable()
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{
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/* enable I2C for SATA */
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write<Clk_gate_ip_fsys::Sata_phy_i2c>(1);
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/**
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* set SATA clock to 66 MHz (nothing else supported)
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* assuming 800 MHz from sclk_mpll_user, formula: sclk / (divider + 1)
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*/
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write<Clk_div_fsys0::Sata_ratio>(11); /* */
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while (read<Clk_div_stat_fsys0::Div_sata>()) ;
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/* enable SATA and SATA Phy */
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write<Clk_gate_ip_fsys::Sata>(1);
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write<Clk_gate_ip_fsys::Sata_phy_ctrl>(1);
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write<Clk_src_mask_fsys::Sata_mask>(1);
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}
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void _sata_disable()
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{
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/* disable I2C for SATA */
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write<Clk_gate_ip_fsys::Sata_phy_i2c>(0);
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/* disable SATA and SATA Phy */
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write<Clk_gate_ip_fsys::Sata>(0);
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write<Clk_gate_ip_fsys::Sata_phy_ctrl>(0);
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write<Clk_src_mask_fsys::Sata_mask>(0);
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}
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bool _sata_enabled()
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{
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return read<Clk_gate_ip_fsys::Sata>() &&
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read<Clk_gate_ip_fsys::Sata_phy_ctrl>() &&
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read<Clk_src_mask_fsys::Sata_mask>();
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}
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/***********************
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** USB 3.0 functions **
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***********************/
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void _usb30_enable()
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{
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/**
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* set USBDRD30 clock to 66 MHz
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* assuming 800 MHz from sclk_mpll_user, formula: sclk / (divider + 1)
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*/
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write<Clk_div_fsys0::Usbdrd30_ratio>(11); /* */
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while (read<Clk_div_stat_fsys0::Div_usbdrd30>()) ;
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/* enable USBDRD30 clock */
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write<Clk_gate_ip_fsys::Usbdrd30>(1);
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write<Clk_src_mask_fsys::Usbdrd30_mask>(1);
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}
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void _usb30_disable()
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{
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write<Clk_gate_ip_fsys::Usbdrd30>(0);
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write<Clk_src_mask_fsys::Usbdrd30_mask>(0);
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}
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bool _usb30_enabled()
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{
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return read<Clk_gate_ip_fsys::Usbdrd30>() &&
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read<Clk_src_mask_fsys::Usbdrd30_mask>();
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}
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public:
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@ -179,12 +317,23 @@ class Cmu : public Regulator::Driver,
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* Constructor
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*/
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Cmu()
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: Genode::Attached_io_mem_dataspace(Genode::Board_base::CMU_MMIO_BASE,
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Genode::Board_base::CMU_MMIO_SIZE),
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Mmio((Genode::addr_t)local_addr<void>())
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: Genode::Attached_mmio(Genode::Board_base::CMU_MMIO_BASE,
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Genode::Board_base::CMU_MMIO_SIZE),
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_cpu_freq(CPU_FREQ_1600)
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{
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/* set CPU to full speed */
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_cpu_clk_freq(CPU_FREQ_1600);
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_sata_disable();
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_usb30_disable();
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_cpu_clk_freq(_cpu_freq);
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/**
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* Hard wiring of reference clocks
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*/
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write<Pll_div2_sel::Mpll_fout_sel>(Pll_div2_sel::Mpll_fout_sel::MPLL_FOUT_HALF);
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write<Clk_src_core1::Mux_mpll_sel>(Clk_src_core1::Mux_mpll_sel::MPLL_FOUT_RGT);
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write<Clk_src_top2::Mux_mpll_user_sel>(Clk_src_top2::Mux_mpll_user_sel::MOUT_MPLL);
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write<Clk_src_fsys::Sata_sel>(Clk_src_fsys::Sata_sel::SCLK_MPLL_USER);
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write<Clk_src_fsys::Usbdrd30_sel>(Clk_src_fsys::Usbdrd30_sel::SCLK_MPLL_USER);
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}
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@ -201,6 +350,7 @@ class Cmu : public Regulator::Driver,
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return;
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}
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_cpu_clk_freq(static_cast<Cpu_clock_freq>(level));
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break;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -209,6 +359,11 @@ class Cmu : public Regulator::Driver,
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unsigned long level(Regulator_id id)
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{
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switch (id) {
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case CLK_CPU:
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return _cpu_freq;
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case CLK_USB30:
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case CLK_SATA:
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return 66666666; /* 66 MHz */
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -218,6 +373,18 @@ class Cmu : public Regulator::Driver,
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void set_state(Regulator_id id, bool enable)
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{
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switch (id) {
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case CLK_SATA:
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if (enable)
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_sata_enable();
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else
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_sata_disable();
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break;
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case CLK_USB30:
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if (enable)
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_usb30_enable();
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else
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_usb30_disable();
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break;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -226,6 +393,10 @@ class Cmu : public Regulator::Driver,
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bool state(Regulator_id id)
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{
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switch (id) {
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case CLK_SATA:
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return _sata_enabled();
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case CLK_USB30:
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return _usb30_enabled();
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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@ -234,10 +405,10 @@ class Cmu : public Regulator::Driver,
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};
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const Genode::uint8_t Cmu::Apll_con0::S::values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
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const Genode::uint16_t Cmu::Apll_con0::M::values[] = { 100, 100, 200, 100, 125,
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150, 175, 200, 425 };
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const Genode::uint8_t Cmu::Apll_con0::P::values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
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const Genode::uint8_t Cmu::s_values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
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const Genode::uint16_t Cmu::m_values[] = { 100, 100, 200, 100, 125,
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150, 175, 200, 425 };
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const Genode::uint8_t Cmu::p_values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
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const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
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0x2147710, 0x2147710, 0x3157720,
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0x4167720, 0x4177730, 0x5377730 };
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@ -18,16 +18,23 @@
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#include <regulator/consts.h>
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#include <cmu.h>
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#include <pmu.h>
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struct Driver_factory : Regulator::Driver_factory
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{
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Cmu _cmu;
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Pmu _pmu;
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Regulator::Driver &create(Regulator::Regulator_id id) {
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switch (id) {
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case Regulator::CLK_CPU:
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case Regulator::CLK_SATA:
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case Regulator::CLK_USB30:
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return _cmu;
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case Regulator::PWR_SATA:
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case Regulator::PWR_USB30:
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return _pmu;
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default:
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throw Root::Invalid_args(); /* invalid regulator */
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};
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@ -0,0 +1,128 @@
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/*
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* \brief Regulator driver for power management unit of Exynos5250 SoC
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-06-18
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _PMU_H_
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#define _PMU_H_
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#include <regulator/consts.h>
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#include <regulator/driver.h>
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#include <drivers/board_base.h>
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#include <os/attached_mmio.h>
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using namespace Regulator;
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class Pmu : public Regulator::Driver,
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public Genode::Attached_mmio
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{
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private:
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template <unsigned OFF>
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struct Control : Register <OFF, 32>
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{
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struct Enable : Register<OFF, 32>::template Bitfield<0, 1> { };
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};
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|
||||
typedef Control<0x704> Usbdrd_phy_control;
|
||||
typedef Control<0x708> Usbhost_phy_control;
|
||||
typedef Control<0x724> Sata_phy_control;
|
||||
|
||||
|
||||
/***********************
|
||||
** USB 3.0 functions **
|
||||
***********************/
|
||||
|
||||
void _usb30_enable()
|
||||
{
|
||||
write<Usbdrd_phy_control::Enable>(1);
|
||||
write<Usbhost_phy_control::Enable>(1);
|
||||
}
|
||||
|
||||
void _usb30_disable()
|
||||
{
|
||||
write<Usbdrd_phy_control::Enable>(0);
|
||||
write<Usbhost_phy_control::Enable>(0);
|
||||
}
|
||||
|
||||
bool _usb30_enabled()
|
||||
{
|
||||
return read<Usbdrd_phy_control::Enable>() &&
|
||||
read<Usbhost_phy_control::Enable>();
|
||||
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*/
|
||||
Pmu() : Genode::Attached_mmio(Genode::Board_base::PMU_MMIO_BASE,
|
||||
Genode::Board_base::PMU_MMIO_SIZE) { }
|
||||
|
||||
|
||||
/********************************
|
||||
** Regulator driver interface **
|
||||
********************************/
|
||||
|
||||
void set_level(Regulator_id id, unsigned long level)
|
||||
{
|
||||
switch (id) {
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long level(Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void set_state(Regulator_id id, bool enable)
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB30:
|
||||
if (enable)
|
||||
_usb30_enable();
|
||||
else
|
||||
_usb30_disable();
|
||||
break;
|
||||
case PWR_SATA :
|
||||
if (enable)
|
||||
write<Sata_phy_control::Enable>(1);
|
||||
else
|
||||
write<Sata_phy_control::Enable>(0);
|
||||
break;
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
bool state(Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB30:
|
||||
return _usb30_enabled();
|
||||
case PWR_SATA:
|
||||
return read<Sata_phy_control::Enable>();
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _PMU_H_ */
|
||||
Loading…
Reference in New Issue