Implement cpu frequency scaling for Arndale
* Implements platform driver for Arndale providing Regulator for CPU clock * Implements a cpu frequency scaling test using the affinity test * Fixes #770
This commit is contained in:
Stefan Kalkowski
Norman Feske
parent
8fb8cf1c8b
commit
1d34589f84
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@ -31,6 +31,9 @@ namespace Genode
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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CMU_MMIO_BASE = 0x10010000,
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CMU_MMIO_SIZE = 0x21000,
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/* interrupt controller */
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GIC_CPU_MMIO_BASE = 0x10480000,
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GIC_CPU_MMIO_SIZE = 0x00010000,
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@ -0,0 +1,68 @@
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/*
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* \brief Regulator definitions for Arndale
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__PLATFORM__ARNDALE__REGULATOR__CONSTS_H_
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#define _INCLUDE__PLATFORM__ARNDALE__REGULATOR__CONSTS_H_
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#include <util/string.h>
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namespace Regulator {
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enum Regulator_id {
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CLK_CPU,
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MAX,
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INVALID
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};
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struct Regulator_name {
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Regulator_id id;
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const char * name;
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};
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Regulator_name names[] = {
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{ CLK_CPU, "clock-cpu" },
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};
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Regulator_id regulator_id_by_name(const char * name)
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{
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for (unsigned i = 0; i < MAX; i++)
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if (Genode::strcmp(names[i].name, name) == 0)
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return names[i].id;
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return INVALID;
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}
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const char * regulator_name_by_id(Regulator_id id) {
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return (id < MAX) ? names[id].name : 0; }
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/***************************************
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** Device specific level definitions **
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***************************************/
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enum Cpu_clock_freq {
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CPU_FREQ_200,
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CPU_FREQ_400,
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CPU_FREQ_600,
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CPU_FREQ_800,
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CPU_FREQ_1000,
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CPU_FREQ_1200,
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CPU_FREQ_1400,
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CPU_FREQ_1600,
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CPU_FREQ_1700, /* warning: 1700 not recommended by the reference manual
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we just insert this for performance measurement against
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Linux, which uses this overclocking */
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CPU_FREQ_MAX
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};
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}
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#endif /* _INCLUDE__PLATFORM__ARNDALE__REGULATOR__CONSTS_H_ */
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@ -0,0 +1,78 @@
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#
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# Build
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#
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# generic components
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set build_components {
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core
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init
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drivers/platform
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drivers/timer
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test/affinity
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test/cpufreq
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}
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build $build_components
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create_boot_directory
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#
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# Config
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#
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set config {
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<config>
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<parent-provides>
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<service name="ROM"/>
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<service name="RAM"/>
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<service name="IRQ"/>
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<service name="IO_MEM"/>
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<service name="CAP"/>
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<service name="PD"/>
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<service name="RM"/>
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<service name="CPU"/>
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<service name="LOG"/>
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<service name="SIGNAL"/>
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</parent-provides>
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<default-route>
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<any-service> <any-child/> <parent/> </any-service>
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</default-route>
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<start name="platform_drv">
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<resource name="RAM" quantum="1M"/>
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<provides><service name="Regulator"/></provides>
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</start>
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<start name="timer">
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<resource name="RAM" quantum="1M"/>
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<provides><service name="Timer"/></provides>
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</start>
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<start name="test-affinity">
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<resource name="RAM" quantum="10M"/>
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</start>
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<start name="test-cpufreq">
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<resource name="RAM" quantum="10M"/>
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</start>
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</config>
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</config>
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}
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install_config $config
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#
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# Boot modules
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#
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# generic modules
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set boot_modules {
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core
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init
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platform_drv
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timer
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test-affinity
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test-cpufreq
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}
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build_boot_image $boot_modules
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run_genode_until forever
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@ -0,0 +1,244 @@
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/*
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* \brief Regulator driver for clock management unit of Exynos5250 SoC
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CMU_H_
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#define _CMU_H_
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#include <regulator/consts.h>
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#include <regulator/driver.h>
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#include <drivers/board_base.h>
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#include <os/attached_io_mem_dataspace.h>
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#include <util/mmio.h>
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using namespace Regulator;
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class Cmu : public Regulator::Driver,
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public Genode::Attached_io_mem_dataspace,
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public Genode::Mmio
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{
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private:
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/***********************
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** CMU CPU registers **
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***********************/
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struct Apll_lock : Register<0x000, 32>
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{
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struct Pll_locktime : Bitfield <0, 20> { };
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static access_t max_lock_time(access_t pdiv) { return pdiv * 250; };
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};
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struct Apll_con0 : Register<0x100, 32>
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{
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struct S : Bitfield <0, 3>
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{
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/* S values for frequencies 200 - 1700 */
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static const Genode::uint8_t values[];
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};
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struct P : Bitfield <8, 6>
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{
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/* P values for frequencies 200 - 1700 */
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static const Genode::uint8_t values[];
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};
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struct M : Bitfield <16, 10>
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{
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/* M values for frequencies 200 - 1700 */
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static const Genode::uint16_t values[];
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};
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struct Locked : Bitfield <29, 1> { };
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};
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struct Clk_src_cpu : Register<0x200, 32>
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{
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struct Mux_cpu_sel : Bitfield<16, 1>
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{
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enum { MOUT_APLL, SCLK_MPLL};
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};
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};
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struct Clk_mux_stat_cpu : Register<0x400, 32>
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{
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struct Cpu_sel : Bitfield<16, 3>
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{
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enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
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};
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};
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struct Clk_div_cpu0 : Register<0x500, 32>
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{
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/* Cpu0 divider values for frequencies 200 - 1700 */
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static const Genode::uint32_t values[];
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};
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struct Clk_div_cpu1 : Register<0x504, 32>
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{
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/* Divider for cpu1 doesn't change */
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enum { FIX_VALUE = 32 };
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};
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struct Clk_div_stat_cpu0 : Register<0x600, 32>
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{
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struct Div_arm : Bitfield< 0, 1> {};
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struct Div_cpud : Bitfield< 4, 1> {};
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struct Div_acp : Bitfield< 8, 1> {};
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struct Div_pheriph : Bitfield<12, 1> {};
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struct Div_atb : Bitfield<16, 1> {};
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struct Div_pclk_dbg : Bitfield<20, 1> {};
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struct Div_apll : Bitfield<24, 1> {};
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struct Div_arm2 : Bitfield<28, 1> {};
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static bool in_progress(access_t stat_word)
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{
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return stat_word & (Div_arm::bits(1) |
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Div_cpud::bits(1) |
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Div_acp::bits(1) |
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Div_pheriph::bits(1) |
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Div_atb::bits(1) |
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Div_pclk_dbg::bits(1) |
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Div_apll::bits(1) |
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Div_arm2::bits(1));
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}
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};
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struct Clk_div_stat_cpu1 : Register<0x604, 32>
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{
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struct Div_copy : Bitfield<0, 1> { };
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struct Div_hpm : Bitfield<4, 1> { };
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static bool in_progress(access_t stat_word)
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{
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return stat_word & (Div_copy::bits(1) |
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Div_hpm::bits(1));
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}
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};
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/**
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* CPU frequency scaling function
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*/
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void _cpu_clk_freq(Cpu_clock_freq freq)
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{
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/**
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* change clock divider values
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*/
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/* cpu0 divider */
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write<Clk_div_cpu0>(Clk_div_cpu0::values[freq]);
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while (Clk_div_stat_cpu0::in_progress(read<Clk_div_stat_cpu0>())) ;
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/* cpu1 divider */
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write<Clk_div_cpu1>(Clk_div_cpu1::FIX_VALUE);
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while (Clk_div_stat_cpu1::in_progress(read<Clk_div_stat_cpu1>())) ;
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/**
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* change APLL frequency
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*/
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/* change reference clock to MPLL */
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write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::SCLK_MPLL);
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while (read<Clk_mux_stat_cpu::Cpu_sel>()
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!= Clk_mux_stat_cpu::Cpu_sel::SCLK_MPLL) ;
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/* set lock time */
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unsigned pdiv = Apll_con0::P::values[freq];
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write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
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/* change P, M, S values of APLL */
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write<Apll_con0::P>(Apll_con0::P::values[freq]);
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write<Apll_con0::M>(Apll_con0::M::values[freq]);
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write<Apll_con0::S>(Apll_con0::S::values[freq]);
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while (!read<Apll_con0::Locked>()) ;
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/* change reference clock back to APLL */
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write<Clk_src_cpu::Mux_cpu_sel>(Clk_src_cpu::Mux_cpu_sel::MOUT_APLL);
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while (read<Clk_mux_stat_cpu::Cpu_sel>()
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!= Clk_mux_stat_cpu::Cpu_sel::MOUT_APLL) ;
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}
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public:
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/**
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* Constructor
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*/
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Cmu()
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: Genode::Attached_io_mem_dataspace(Genode::Board_base::CMU_MMIO_BASE,
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Genode::Board_base::CMU_MMIO_SIZE),
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Mmio((Genode::addr_t)local_addr<void>())
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{
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/* set CPU to full speed */
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_cpu_clk_freq(CPU_FREQ_1600);
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}
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/********************************
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** Regulator driver interface **
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********************************/
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void set_level(Regulator_id id, unsigned long level)
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{
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switch (id) {
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case CLK_CPU:
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if (level >= CPU_FREQ_MAX) {
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PWRN("level=%ld not supported", level);
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return;
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}
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_cpu_clk_freq(static_cast<Cpu_clock_freq>(level));
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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}
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unsigned long level(Regulator_id id)
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{
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switch (id) {
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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return 0;
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}
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void set_state(Regulator_id id, bool enable)
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{
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switch (id) {
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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}
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bool state(Regulator_id id)
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{
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switch (id) {
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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return true;
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}
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};
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const Genode::uint8_t Cmu::Apll_con0::S::values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
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const Genode::uint16_t Cmu::Apll_con0::M::values[] = { 100, 100, 200, 100, 125,
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150, 175, 200, 425 };
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const Genode::uint8_t Cmu::Apll_con0::P::values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
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const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
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0x2147710, 0x2147710, 0x3157720,
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0x4167720, 0x4177730, 0x5377730 };
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#endif /* _CMU_H_ */
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@ -0,0 +1,55 @@
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/*
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* \brief Driver for Arndale specific platform devices (clocks, power, etc.)
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-06-13
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <base/printf.h>
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#include <base/sleep.h>
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#include <cap_session/connection.h>
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#include <regulator/component.h>
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#include <regulator/consts.h>
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#include <cmu.h>
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struct Driver_factory : Regulator::Driver_factory
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{
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Cmu _cmu;
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Regulator::Driver &create(Regulator::Regulator_id id) {
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switch (id) {
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case Regulator::CLK_CPU:
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return _cmu;
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default:
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throw Root::Invalid_args(); /* invalid regulator */
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};
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}
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void destroy(Regulator::Driver &driver) { }
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};
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int main(int, char **)
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{
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using namespace Genode;
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PINF("--- Arndale platform driver ---\n");
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static Cap_connection cap;
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static Rpc_entrypoint ep(&cap, 4096, "arndale_plat_ep");
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static ::Driver_factory driver_factory;
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static Regulator::Root reg_root(&ep, env()->heap(), driver_factory);
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env()->parent()->announce(ep.manage(®_root));
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sleep_forever();
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return 0;
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}
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@ -0,0 +1,5 @@
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TARGET = platform_drv
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REQUIRES = platform_arndale
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SRC_CC = main.cc
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INC_DIR += ${PRG_DIR}
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LIBS = base
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@ -0,0 +1,42 @@
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/*
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* \brief Test for changing the CPU frequency
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* \author Stefan Kalkowski
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* \date 2013-06-14
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode includes */
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#include <base/printf.h>
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#include <base/env.h>
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#include <base/sleep.h>
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#include <regulator/consts.h>
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#include <regulator_session/connection.h>
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#include <timer_session/connection.h>
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int main(int argc, char **argv)
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{
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using namespace Genode;
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printf("--- test-cpufreq started ---\n");
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static Timer::Connection timer;
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static Regulator::Connection cpu_regulator(Regulator::CLK_CPU);
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bool high = true;
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while (true) {
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timer.msleep(10000);
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PINF("Setting CPU frequency %s", high ? "low" : "high");
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cpu_regulator.set_level(high ? Regulator::CPU_FREQ_200
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: Regulator::CPU_FREQ_1600);
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high = !high;
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}
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return 1;
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}
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@ -0,0 +1,4 @@
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TARGET = test-cpufreq
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REQUIRES = platform_arndale
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SRC_CC = main.cc
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LIBS = base
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