parent
ac92283db0
commit
f2e462266e
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@ -47,6 +47,7 @@
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/* load kernel section table */
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/* load kernel section table */
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adr sp, _mt_master_context_begin
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adr sp, _mt_master_context_begin
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ldr sp, [sp, #19*4]
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ldr sp, [sp, #19*4]
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orr sp, sp, #0b1000000 /* set TTBR0 flags */
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mcr p15, 0, sp, c2, c0, 0
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mcr p15, 0, sp, c2, c0, 0
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isb
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isb
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dsb
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dsb
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@ -128,6 +129,7 @@
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/* get user contextidr and section table */
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/* get user contextidr and section table */
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ldr sp, [lr, #18*4]
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ldr sp, [lr, #18*4]
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ldr lr, [lr, #19*4]
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ldr lr, [lr, #19*4]
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orr lr, lr, #0b1000000 /* set TTBR0 flags */
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/********************************************************
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/********************************************************
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** From now on, until we leave kernel mode, we must **
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** From now on, until we leave kernel mode, we must **
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@ -170,11 +170,6 @@ namespace Arm
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*/
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*/
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struct Ttbr0 : Register<32>
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struct Ttbr0 : Register<32>
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{
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{
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struct Irgn_1 : Bitfield<0,1> /* inner cachable mode */
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{
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enum { NON_CACHEABLE = 0 };
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};
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struct S : Bitfield<1,1> { }; /* shareable */
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struct S : Bitfield<1,1> { }; /* shareable */
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struct Rgn : Bitfield<3, 2> /* outer cachable attributes */
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struct Rgn : Bitfield<3, 2> /* outer cachable attributes */
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@ -209,7 +204,6 @@ namespace Arm
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static access_t init_virt_kernel(addr_t const sect_table)
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static access_t init_virt_kernel(addr_t const sect_table)
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{
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{
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return S::bits(0) |
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return S::bits(0) |
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Irgn_1::bits(Irgn_1::NON_CACHEABLE) |
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Rgn::bits(Rgn::NON_CACHEABLE) |
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Rgn::bits(Rgn::NON_CACHEABLE) |
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Ba::masked((addr_t)sect_table);
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Ba::masked((addr_t)sect_table);
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}
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}
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@ -111,6 +111,11 @@ namespace Arm_v6
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*/
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*/
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struct Ttbr0 : Arm::Cpu::Ttbr0
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struct Ttbr0 : Arm::Cpu::Ttbr0
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{
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{
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struct C : Bitfield<0,1> /* inner cachable mode */
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{
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enum { NON_CACHEABLE = 0 };
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};
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struct P : Bitfield<2,1> { }; /* memory controller ECC enabled */
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struct P : Bitfield<2,1> { }; /* memory controller ECC enabled */
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/**
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/**
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@ -121,7 +126,8 @@ namespace Arm_v6
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static access_t init_virt_kernel(addr_t const sect_table)
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static access_t init_virt_kernel(addr_t const sect_table)
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{
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{
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return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
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return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
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P::bits(0);
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P::bits(0) |
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C::bits(C::NON_CACHEABLE);
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}
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}
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};
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};
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@ -163,6 +169,11 @@ namespace Arm_v6
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Ttbcr::write(Ttbcr::init_virt_kernel());
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Ttbcr::write(Ttbcr::init_virt_kernel());
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Sctlr::write(Sctlr::init_virt_kernel());
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Sctlr::write(Sctlr::init_virt_kernel());
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}
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}
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/**
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* Ensure that TLB insertions get applied
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*/
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static void tlb_insertions() { flush_tlb(); }
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};
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};
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}
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}
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@ -124,10 +124,8 @@ namespace Arm_v7
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{
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{
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struct Nos : Bitfield<6,1> { }; /* not outer shareable */
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struct Nos : Bitfield<6,1> { }; /* not outer shareable */
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struct Irgn_0 : Bitfield<6,1> /* inner cachable mode */
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struct Irgn_1 : Bitfield<0,1> { }; /* inner cachable mode */
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{
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struct Irgn_0 : Bitfield<6,1> { }; /* inner cachable mode */
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enum { NON_CACHEABLE = 0 };
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};
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/**
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/**
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* Value for the switch to virtual mode in kernel
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* Value for the switch to virtual mode in kernel
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@ -138,7 +136,8 @@ namespace Arm_v7
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{
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{
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return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
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return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
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Nos::bits(0) |
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Nos::bits(0) |
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Irgn_0::bits(Irgn_0::NON_CACHEABLE);
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Irgn_1::bits(0) |
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Irgn_0::bits(1);
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}
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}
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};
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};
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37
base-hw/src/core/cpu/cortex_a8.h
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37
base-hw/src/core/cpu/cortex_a8.h
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@ -0,0 +1,37 @@
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/*
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* \brief CPU driver for core
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CPU__CORTEX_A8_H_
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#define _CPU__CORTEX_A8_H_
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/* core includes */
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#include <cpu/arm_v7.h>
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namespace Cortex_a8
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{
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using namespace Genode;
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/**
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* CPU driver for core
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*/
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struct Cpu : Arm_v7::Cpu
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{
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/**
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* Ensure that TLB insertions get applied
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*/
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static void tlb_insertions() { flush_tlb(); }
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};
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}
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#endif /* _CPU__CORTEX_A8_H_ */
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PRIVATE_TIMER_IRQ = 29,
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PRIVATE_TIMER_IRQ = 29,
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PRIVATE_TIMER_CLK = PERIPH_CLK
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PRIVATE_TIMER_CLK = PERIPH_CLK
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};
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};
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/**
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* Ensure that TLB insertions get applied
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*
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* Nothing to do because MMU uses caches on pagetable walks
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*/
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static void tlb_insertions() { }
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};
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};
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}
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}
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#define _IMX53__CPU_H_
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#define _IMX53__CPU_H_
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/* core includes */
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/* core includes */
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#include <cpu/arm_v7.h>
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#include <cpu/cortex_a8.h>
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namespace Genode
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namespace Genode
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{
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{
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/**
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/**
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* CPU driver for core
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* CPU driver for core
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*/
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*/
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class Cpu : public Arm_v7::Cpu { };
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class Cpu : public Cortex_a8::Cpu { };
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}
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}
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#endif /* _IMX53__CPU_H_ */
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#endif /* _IMX53__CPU_H_ */
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* the memory that holds the TLB data, because the latter
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* the memory that holds the TLB data, because the latter
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* is not feasible in core space.
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* is not feasible in core space.
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*/
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*/
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Cpu::flush_caches();
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Cpu::tlb_insertions();
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/* resume targeted thread */
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/* resume targeted thread */
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t->resume();
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t->resume();
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