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base: rename generic Board drivers Board_base 

To enable a repo to name its specific board driver 'Board'.

Fix #569
This commit is contained in:
Martin Stein 2012-12-11 14:45:18 +01:00 committed by Norman Feske
parent 8b568a6029
commit f1d599ae8a
21 changed files with 103 additions and 106 deletions
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6
base-hw/include/pl011/drivers/serial_log.h
View File

@ -15,7 +15,7 @@
#define _INCLUDE__PL011__DRIVERS__SERIAL_LOG_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
#include <drivers/uart/pl011_base.h>
namespace Genode
@ -33,8 +33,8 @@ namespace Genode
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Pl011_base(Board::PL011_0_MMIO_BASE,
Board::PL011_0_CLOCK, baud_rate)
Pl011_base(Board_base::PL011_0_MMIO_BASE,
Board_base::PL011_0_CLOCK, baud_rate)
{ }
};
}

6
base-hw/include/tl16c750/drivers/serial_log.h
View File

@ -15,7 +15,7 @@
#define _INCLUDE__TL16C750__DRIVERS__SERIAL_LOG_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
#include <drivers/uart/tl16c750_base.h>
namespace Genode
@ -33,8 +33,8 @@ namespace Genode
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Tl16c750_base(Board::TL16C750_MMIO_BASE,
Board::TL16C750_CLOCK, baud_rate)
Tl16c750_base(Board_base::TL16C750_3_MMIO_BASE,
Board_base::TL16C750_CLOCK, baud_rate)
{ }
};
}

4
base-hw/src/core/imx31/tlb.h
View File

@ -49,8 +49,8 @@ class Core_tlb : public Tlb
Core_tlb()
{
map_core_area(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0);
map_core_area(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1);
map_core_area(Genode::Board::RAM_0_BASE, Genode::Board::RAM_0_SIZE, 0);
map_core_area(Genode::Board::MMIO_0_BASE, Genode::Board::MMIO_0_SIZE, 1);
}
};

2
base-hw/src/core/include/arm/v6/cpu.h
View File

@ -135,7 +135,7 @@ namespace Arm_v6
*/
static void init_phys_kernel()
{
::Board::prepare_kernel();
Board::prepare_kernel();
Sctlr::write(Sctlr::init_phys_kernel());
flush_tlb();

4
base-hw/src/core/include/arm/v7/cpu.h
View File

@ -15,7 +15,7 @@
#define _INCLUDE__ARM_V7__CPU_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <arm/cpu.h>
@ -194,7 +194,7 @@ namespace Arm_v7
*/
static bool secure_mode()
{
if (!Board::SECURITY_EXTENSION) return 0;
if (!Board_base::SECURITY_EXTENSION) return 0;
return !Cpu::Scr::Ns::get(Cpu::Scr::read());
}

10
base-hw/src/core/include/cortex_a9/cpu.h
View File

@ -15,7 +15,7 @@
#define _INCLUDE__CORTEX_A9__CPU_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/cpu.h>
@ -32,17 +32,17 @@ namespace Cortex_a9
enum
{
/* common */
CLK = Board::CORTEX_A9_CLOCK, /* CPU interface clock */
CLK = Board_base::CORTEX_A9_CLOCK, /* CPU interface clock */
PERIPH_CLK = CLK, /* clock for CPU internal components */
/* interrupt controller */
PL390_DISTRIBUTOR_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
PL390_DISTRIBUTOR_MMIO_BASE = Board_base::CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
PL390_DISTRIBUTOR_MMIO_SIZE = 0x1000,
PL390_CPU_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x100,
PL390_CPU_MMIO_BASE = Board_base::CORTEX_A9_PRIVATE_MEM_BASE + 0x100,
PL390_CPU_MMIO_SIZE = 0x100,
/* timer */
PRIVATE_TIMER_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
PRIVATE_TIMER_MMIO_BASE = Board_base::CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
PRIVATE_TIMER_MMIO_SIZE = 0x10,
PRIVATE_TIMER_IRQ = 29,
PRIVATE_TIMER_CLK = PERIPH_CLK

11
base-hw/src/core/include/imx31/drivers/board.h
View File

@ -8,12 +8,10 @@
#define _INCLUDE__IMX31__DRIVERS__BOARD_H_
/* Genode includes */
#include <platform/imx31/drivers/board.h>
#include <platform/imx31/drivers/board_base.h>
namespace Imx31
namespace Genode
{
using namespace Genode;
/**
* AHB-lite 2v6 to IP bus interface
*/
@ -71,7 +69,7 @@ namespace Imx31
}
};
struct Board : Genode::Board
struct Board : Board_base
{
/**
* static AIPS 1 instance
@ -94,6 +92,5 @@ namespace Imx31
};
}
typedef Imx31::Board Board;
#endif /* _INCLUDE__IMX31__DRIVERS__BOARD_H_ */

22
base-hw/src/core/panda/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <cortex_a9/cpu.h>
@ -26,7 +26,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
{ Board_base::RAM_0_BASE, Board_base::RAM_0_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -50,7 +50,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::Cpu::PRIVATE_TIMER_IRQ, 1 },
/* core UART */
{ Board::TL16C750_3_IRQ, 1 }
{ Board_base::TL16C750_3_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -60,11 +60,11 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
{ Board::DSS_MMIO_BASE, Board::DSS_MMIO_SIZE },
{ Board::DISPC_MMIO_BASE, Board::DISPC_MMIO_SIZE },
{ Board::HDMI_MMIO_BASE, Board::HDMI_MMIO_SIZE }
{ Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE },
{ Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE },
{ Board_base::DSS_MMIO_BASE, Board_base::DSS_MMIO_SIZE },
{ Board_base::DISPC_MMIO_BASE, Board_base::DISPC_MMIO_SIZE },
{ Board_base::HDMI_MMIO_BASE, Board_base::HDMI_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -75,11 +75,11 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* core timer and PIC */
{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
Board_base::CORTEX_A9_PRIVATE_MEM_SIZE },
/* core UART */
{ Board::TL16C750_3_MMIO_BASE, Board::TL16C750_MMIO_SIZE }
{ Board_base::TL16C750_3_MMIO_BASE, Board_base::TL16C750_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

8
base-hw/src/core/panda/tlb.h
View File

@ -15,7 +15,7 @@
#define _SRC__CORE__PANDA_A2__TLB_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/section_table.h>
@ -52,9 +52,9 @@ class Core_tlb : public Tlb
Core_tlb()
{
using namespace Genode;
map_core_area(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0);
map_core_area(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1);
map_core_area(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1);
map_core_area(Board_base::RAM_0_BASE, Board_base::RAM_0_SIZE, 0);
map_core_area(Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE, 1);
map_core_area(Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE, 1);
}
};

16
base-hw/src/core/pbxa9/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <platform.h>
@ -27,8 +27,8 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
{ Board::RAM_1_BASE, Board::RAM_1_SIZE }
{ Board_base::RAM_0_BASE, Board_base::RAM_0_SIZE },
{ Board_base::RAM_1_BASE, Board_base::RAM_1_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -52,7 +52,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::Cpu::PRIVATE_TIMER_IRQ, 1 },
/* core UART */
{ Board::PL011_0_IRQ, 1 }
{ Board_base::PL011_0_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -62,8 +62,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE }
{ Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE },
{ Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -74,10 +74,10 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* core timer and PIC */
{ Board::CORTEX_A9_PRIVATE_MEM_BASE, Board::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board_base::CORTEX_A9_PRIVATE_MEM_BASE, Board_base::CORTEX_A9_PRIVATE_MEM_SIZE },
/* core UART */
{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
{ Board_base::PL011_0_MMIO_BASE, Board_base::PL011_0_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

10
base-hw/src/core/pbxa9/tlb.h
View File

@ -15,7 +15,7 @@
#define _SRC__CORE__PBXA9__TLB_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/section_table.h>
@ -52,10 +52,10 @@ class Core_tlb : public Tlb
Core_tlb()
{
using namespace Genode;
map_core_area(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0);
map_core_area(Board::RAM_1_BASE, Board::RAM_1_SIZE, 0);
map_core_area(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1);
map_core_area(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1);
map_core_area(Board_base::RAM_0_BASE, Board_base::RAM_0_SIZE, 0);
map_core_area(Board_base::RAM_1_BASE, Board_base::RAM_1_SIZE, 0);
map_core_area(Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE, 1);
map_core_area(Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE, 1);
}
};

22
base-hw/src/core/vea9x4/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* Core includes */
#include <platform.h>
@ -26,10 +26,10 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
{ Board::RAM_1_BASE, Board::RAM_1_SIZE },
{ Board::RAM_2_BASE, Board::RAM_2_SIZE },
{ Board::RAM_3_BASE, Board::RAM_3_SIZE }
{ Board_base::RAM_0_BASE, Board_base::RAM_0_SIZE },
{ Board_base::RAM_1_BASE, Board_base::RAM_1_SIZE },
{ Board_base::RAM_2_BASE, Board_base::RAM_2_SIZE },
{ Board_base::RAM_3_BASE, Board_base::RAM_3_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -53,7 +53,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::Cpu::PRIVATE_TIMER_IRQ, 1 },
/* Core UART */
{ Board::PL011_0_IRQ, 1 }
{ Board_base::PL011_0_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -63,8 +63,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
{ Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE },
{ Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -75,11 +75,11 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* Core timer and PIC */
{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
Board_base::CORTEX_A9_PRIVATE_MEM_SIZE },
/* Core UART */
{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
{ Board_base::PL011_0_MMIO_BASE, Board_base::PL011_0_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

14
base-hw/src/core/vea9x4/tlb.h
View File

@ -15,7 +15,7 @@
#define _SRC__CORE__VEA9X4__TLB_H_
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/section_table.h>
@ -55,12 +55,12 @@ class Core_tlb : public Tlb
Core_tlb()
{
using namespace Genode;
map_core_area(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0);
map_core_area(Board::RAM_1_BASE, Board::RAM_1_SIZE, 0);
map_core_area(Board::RAM_2_BASE, Board::RAM_2_SIZE, 0);
map_core_area(Board::RAM_3_BASE, Board::RAM_3_SIZE, 0);
map_core_area(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1);
map_core_area(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1);
map_core_area(Board_base::RAM_0_BASE, Board_base::RAM_0_SIZE, 0);
map_core_area(Board_base::RAM_1_BASE, Board_base::RAM_1_SIZE, 0);
map_core_area(Board_base::RAM_2_BASE, Board_base::RAM_2_SIZE, 0);
map_core_area(Board_base::RAM_3_BASE, Board_base::RAM_3_SIZE, 0);
map_core_area(Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE, 1);
map_core_area(Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE, 1);
}
};

20
base-hw/src/core/vea9x4/trustzone/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
/* Core includes */
#include <platform.h>
@ -26,7 +26,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::RAM_3_BASE, Board::RAM_3_SIZE }
{ Board_base::RAM_3_BASE, Board_base::RAM_3_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -53,7 +53,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::Cpu::PRIVATE_TIMER_IRQ, 1 },
/* Core UART */
{ Board::PL011_0_IRQ, 1 }
{ Board_base::PL011_0_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -63,11 +63,11 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
{ Board_base::MMIO_0_BASE, Board_base::MMIO_0_SIZE },
{ Board_base::MMIO_1_BASE, Board_base::MMIO_1_SIZE },
{ 0x60000000, 0x40000000 },
{ Board::TZASC_MMIO_BASE, Board::TZASC_MMIO_SIZE },
{ Board::TZPC_MMIO_BASE, Board::TZPC_MMIO_SIZE },
{ Board_base::TZASC_MMIO_BASE, Board_base::TZASC_MMIO_SIZE },
{ Board_base::TZPC_MMIO_BASE, Board_base::TZPC_MMIO_SIZE },
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -78,11 +78,11 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* Core timer and PIC */
{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
Board_base::CORTEX_A9_PRIVATE_MEM_SIZE },
/* Core UART */
{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
{ Board_base::PL011_0_MMIO_BASE, Board_base::PL011_0_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

8
base/include/platform/imx31/drivers/board.h → base/include/platform/imx31/drivers/board_base.h
View File

@ -12,8 +12,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__BOARD_H_
#define _INCLUDE__PLATFORM__BOARD_H_
#ifndef _INCLUDE__PLATFORM__BOARD_BASE_H_
#define _INCLUDE__PLATFORM__BOARD_BASE_H_
/* Genode includes */
#include <util/mmio.h>
@ -23,7 +23,7 @@ namespace Genode
/**
* i.MX31 motherboard
*/
struct Board
struct Board_base
{
enum {
RAM_0_BASE = 0x80000000,
@ -52,5 +52,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__PLATFORM__BOARD_H_ */
#endif /* _INCLUDE__PLATFORM__BOARD_BASE_H_ */

8
base/include/platform/panda/drivers/board.h → base/include/platform/panda/drivers/board_base.h
View File

@ -11,15 +11,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_
namespace Genode
{
/**
* Driver for the OMAP4 PandaBoard revision A2
*/
struct Board
struct Board_base
{
enum
{
@ -70,5 +70,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */
#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */

8
base/include/platform/pbxa9/drivers/board.h → base/include/platform/pbxa9/drivers/board_base.h
View File

@ -11,15 +11,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_
namespace Genode
{
/**
* Driver for the Realview PBXA9 board
*/
struct Board
struct Board_base
{
enum
{
@ -68,5 +68,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */
#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */

8
base/include/platform/vea9x4/drivers/board.h → base/include/platform/vea9x4/drivers/board_base.h
View File

@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_
namespace Genode
{
@ -21,7 +21,7 @@ namespace Genode
*
* Implies the uATX motherboard and the CoreTile Express A9X4 daughterboard
*/
struct Board
struct Board_base
{
enum
{
@ -74,5 +74,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */
#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */

8
os/src/drivers/framebuffer/omap4/driver.h
View File

@ -13,7 +13,7 @@
*/
/* Genode includes */
#include <drivers/board.h>
#include <drivers/board_base.h>
#include <os/attached_io_mem_dataspace.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
@ -109,13 +109,13 @@ class Framebuffer::Driver
Framebuffer::Driver::Driver()
:
_dss_mmio(Board::DSS_MMIO_BASE, Board::DSS_MMIO_SIZE),
_dss_mmio(Board_base::DSS_MMIO_BASE, Board_base::DSS_MMIO_SIZE),
_dss((addr_t)_dss_mmio.local_addr<void>()),
_dispc_mmio(Board::DISPC_MMIO_BASE, Board::DISPC_MMIO_SIZE),
_dispc_mmio(Board_base::DISPC_MMIO_BASE, Board_base::DISPC_MMIO_SIZE),
_dispc((addr_t)_dispc_mmio.local_addr<void>()),
_hdmi_mmio(Board::HDMI_MMIO_BASE, Board::HDMI_MMIO_SIZE),
_hdmi_mmio(Board_base::HDMI_MMIO_BASE, Board_base::HDMI_MMIO_SIZE),
_hdmi((addr_t)_hdmi_mmio.local_addr<void>())
{ }

4
os/src/drivers/timer/hw/omap4/platform_timer_base.h
View File

@ -18,7 +18,7 @@
#include <io_mem_session/connection.h>
#include <util/mmio.h>
#include <irq_session/connection.h>
#include <drivers/board.h>
#include <drivers/board_base.h>
namespace Genode
{
@ -31,7 +31,7 @@ namespace Genode
* Timer tics per microsecond
*/
static float tics_per_us() {
return (float)Board::SYS_CLK / 1000000; }
return (float)Board_base::SYS_CLK / 1000000; }
/**
* Microsecodns per timer tic

10
os/src/drivers/timer/hw/pbxa9/platform_timer_base.h
View File

@ -17,25 +17,25 @@
/* Genode includes */
#include <io_mem_session/connection.h>
#include <drivers/timer/sp804_base.h>
#include <drivers/board.h>
#include <drivers/board_base.h>
/**
* Platform-timer base specific for base-hw and PBXA9
*/
class Platform_timer_base :
public Genode::Io_mem_connection,
public Genode::Sp804_base<Genode::Board::SP804_0_1_CLOCK>
public Genode::Sp804_base<Genode::Board_base::SP804_0_1_CLOCK>
{
public:
enum { IRQ = Genode::Board::SP804_0_1_IRQ };
enum { IRQ = Genode::Board_base::SP804_0_1_IRQ };
/**
* Constructor
*/
Platform_timer_base() :
Io_mem_connection(Genode::Board::SP804_0_1_MMIO_BASE,
Genode::Board::SP804_0_1_MMIO_SIZE),
Io_mem_connection(Genode::Board_base::SP804_0_1_MMIO_BASE,
Genode::Board_base::SP804_0_1_MMIO_SIZE),
Sp804_base((Genode::addr_t)Genode::env()->rm_session()->
attach(dataspace()))