hw & cortex_a9: fix scheduling-timer speed
The estimation of the input clock of the Cortex A9 Private Timer module was pretty miserable at every Cortex A9 board. Fixes #1341
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@ -215,9 +215,6 @@ class Genode::Cpu : public Arm_v7
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enum
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enum
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{
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{
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/* common */
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PERIPH_CLK = Board::CORTEX_A9_CLOCK,
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/* interrupt controller */
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/* interrupt controller */
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PL390_DISTRIBUTOR_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
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PL390_DISTRIBUTOR_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
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PL390_DISTRIBUTOR_MMIO_SIZE = 0x1000,
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PL390_DISTRIBUTOR_MMIO_SIZE = 0x1000,
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@ -228,7 +225,6 @@ class Genode::Cpu : public Arm_v7
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PRIVATE_TIMER_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
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PRIVATE_TIMER_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
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PRIVATE_TIMER_MMIO_SIZE = 0x10,
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PRIVATE_TIMER_MMIO_SIZE = 0x10,
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PRIVATE_TIMER_IRQ = 29,
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PRIVATE_TIMER_IRQ = 29,
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PRIVATE_TIMER_CLK = PERIPH_CLK
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};
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};
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/**
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/**
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@ -27,7 +27,7 @@ namespace Genode
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*/
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*/
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class Timer : public Mmio
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class Timer : public Mmio
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{
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{
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enum { TICS_PER_MS = Cpu::PRIVATE_TIMER_CLK / 1000, };
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enum { TICS_PER_MS = Board::CORTEX_A9_PRIVATE_TIMER_CLK / 1000 };
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/**
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/**
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* Load value register
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* Load value register
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@ -34,8 +34,7 @@ namespace Genode
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RAM_0_SIZE = 0x40000000,
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RAM_0_SIZE = 0x40000000,
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/* clocks */
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/* clocks */
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MPU_DPLL_CLOCK = 200*1000*1000,
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SYS_CLK = 38400000,
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SYS_CLK = 38400000,
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/* UART controllers */
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/* UART controllers */
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TL16C750_1_MMIO_BASE = MMIO_0_BASE + 0x6a000,
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TL16C750_1_MMIO_BASE = MMIO_0_BASE + 0x6a000,
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@ -58,7 +57,7 @@ namespace Genode
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/* CPU */
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x48240000,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x48240000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_CLOCK = MPU_DPLL_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_CLK = 350000000,
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/* L2 cache */
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/* L2 cache */
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PL310_MMIO_BASE = 0x48242000,
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PL310_MMIO_BASE = 0x48242000,
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@ -44,12 +44,11 @@ namespace Genode
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/* clocks */
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/* clocks */
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OSC_6_CLOCK = 24*1000*1000,
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OSC_6_CLOCK = 24*1000*1000,
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OSC_7_CLOCK = 14*1000*1000,
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/* CPU */
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/* CPU */
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CORTEX_A9_CLOCK = OSC_7_CLOCK * 5,
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CORTEX_A9_PRIVATE_TIMER_CLK = 100000000,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
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/* UART */
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/* UART */
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PL011_0_MMIO_BASE = 0x10009000,
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PL011_0_MMIO_BASE = 0x10009000,
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@ -65,9 +65,6 @@ namespace Genode
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PL180_0_IRQ = 9,
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PL180_0_IRQ = 9,
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PL180_1_IRQ = 10,
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PL180_1_IRQ = 10,
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/* clocks */
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TCREF_CLOCK = 66670*1000,
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/* TrustZone Address Space Controller */
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/* TrustZone Address Space Controller */
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TZASC_MMIO_BASE = 0x100ec000,
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TZASC_MMIO_BASE = 0x100ec000,
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TZASC_MMIO_SIZE = 0x1000,
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TZASC_MMIO_SIZE = 0x1000,
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@ -77,9 +74,9 @@ namespace Genode
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TZPC_MMIO_SIZE = 0x1000,
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TZPC_MMIO_SIZE = 0x1000,
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/* CPU */
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_CLOCK = TCREF_CLOCK,
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CORTEX_A9_PRIVATE_TIMER_CLK = 200010000,
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/* wether board provides security extension */
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/* wether board provides security extension */
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SECURITY_EXTENSION = 1,
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SECURITY_EXTENSION = 1,
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