ehmry/genode
ehmry
/
genode
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

enable i.MX6 Quad Sabrelite board for hw and foc

This commit is contained in:
Stefan Kalkowski 2019-01-14 15:39:46 +01:00 committed by Norman Feske
parent 2f9da1c7c8
commit c65860ee53
18 changed files with 692 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

112
repos/base-foc/config/imx6q_sabrelite.kernel Normal file
View File

@ -0,0 +1,112 @@
#
# Automatically generated file; DO NOT EDIT.
# Fiasco configuration
#
CONFIG_HAS_FPU_OPTION=y
CONFIG_HAS_VIRT_OBJ_SPACE_OPTION=y
CONFIG_HAS_SERIAL_OPTION=y
CONFIG_HAS_JDB_GZIP_OPTION=y
CONFIG_HAS_MP_OPTION=y
#
# Target configuration
#
# CONFIG_IA32 is not set
# CONFIG_AMD64 is not set
CONFIG_ARM=y
# CONFIG_MIPS is not set
# CONFIG_PF_INTEGRATOR is not set
# CONFIG_PF_REALVIEW is not set
# CONFIG_PF_SUNXI is not set
# CONFIG_PF_BCM283X is not set
# CONFIG_PF_SA1100 is not set
# CONFIG_PF_XSCALE is not set
# CONFIG_PF_ARMADA38X is not set
# CONFIG_PF_KIRKWOOD is not set
# CONFIG_PF_TEGRA is not set
# CONFIG_PF_LAYERSCAPE is not set
CONFIG_PF_IMX=y
# CONFIG_PF_ARM_VIRT is not set
# CONFIG_PF_RCAR3 is not set
# CONFIG_PF_EXYNOS is not set
# CONFIG_PF_S3C2410 is not set
# CONFIG_PF_OMAP is not set
# CONFIG_PF_ZYNQ is not set
# CONFIG_PF_ZYNQMP is not set
CONFIG_BSP_NAME="imx"
CONFIG_CAN_ARM_CPU_CORTEX_A9=y
CONFIG_CAN_ARM_CACHE_L2CXX0=y
CONFIG_ARM_V7=y
CONFIG_ARM_V6PLUS=y
CONFIG_ARM_V7PLUS=y
# CONFIG_PF_IMX_21 is not set
# CONFIG_PF_IMX_28 is not set
# CONFIG_PF_IMX_35 is not set
# CONFIG_PF_IMX_51 is not set
CONFIG_PF_IMX_6=y
# CONFIG_PF_IMX_6UL is not set
# CONFIG_PF_IMX_7 is not set
CONFIG_PF_IMX_RAM_PHYS_BASE=0x10000000
CONFIG_PF_IMX_6_TIMER_MPTIMER=y
# CONFIG_PF_IMX_6_TIMER_EPIT is not set
CONFIG_ABI_VF=y
CONFIG_ARM_CORTEX_A9=y
CONFIG_FPU=y
# CONFIG_ARM_ALIGNMENT_CHECK is not set
CONFIG_ARM_EM_STD=y
# CONFIG_ARM_EM_NS is not set
# CONFIG_ARM_EM_TZ is not set
# CONFIG_ARM_SMC_USER is not set
CONFIG_ARM_CACHE_L2CXX0=y
# CONFIG_ARM_ENABLE_SWP is not set
CONFIG_HAS_ARM_PSCI=y
# CONFIG_ARM_PSCI is not set
CONFIG_ARM_CPU_ERRATA=y
#
# Kernel options
#
# CONFIG_MP is not set
CONFIG_CONTEXT_4K=y
# CONFIG_FINE_GRAINED_CPUTIME is not set
CONFIG_SCHED_FIXED_PRIO=y
CONFIG_VIRT_OBJ_SPACE=y
#
# Debugging
#
CONFIG_INLINE=y
# CONFIG_NDEBUG is not set
CONFIG_NO_FRAME_PTR=y
# CONFIG_STACK_DEPTH is not set
# CONFIG_LIST_ALLOC_SANITY is not set
CONFIG_SERIAL=y
CONFIG_JDB=y
CONFIG_JDB_LOGGING=y
CONFIG_JDB_GZIP=y
# CONFIG_JDB_ACCOUNTING is not set
# CONFIG_WARN_NONE is not set
CONFIG_WARN_WARNING=y
# CONFIG_WARN_ANY is not set
#
# ARM debugging options
#
# CONFIG_VMEM_ALLOC_TEST is not set
# CONFIG_DEBUG_KERNEL_PAGE_FAULTS is not set
#
# Compiling
#
CONFIG_CC="gcc"
CONFIG_CXX="g++"
CONFIG_HOST_CC="gcc"
CONFIG_HOST_CXX="g++"
# CONFIG_MAINTAINER_MODE is not set
CONFIG_LABEL=""
# CONFIG_EXPERIMENTAL is not set
CONFIG_PERF_CNT=y
CONFIG_BIT32=y
CONFIG_WARN_LEVEL=1
CONFIG_XARCH="arm"
CONFIG_ABI="vf"

84
repos/base-foc/config/imx6q_sabrelite.user Normal file
View File

@ -0,0 +1,84 @@
#
# Automatically generated file; DO NOT EDIT.
# L4Re Configuration
#
CONFIG_ARCH_ENABLE_STACK_PROTECTOR=y
# CONFIG_BUILD_ARCH_amd64 is not set
CONFIG_BUILD_ARCH_arm=y
# CONFIG_BUILD_ARCH_arm64 is not set
# CONFIG_BUILD_ARCH_mips is not set
# CONFIG_BUILD_ARCH_ppc32 is not set
# CONFIG_BUILD_ARCH_sparc is not set
# CONFIG_BUILD_ARCH_x86 is not set
CONFIG_BUILD_ARCH="arm"
CONFIG_BUILD_ABI_l4f=y
CONFIG_BUILD_ABI="l4f"
# CONFIG_CPU_ARM_ARMV4 is not set
# CONFIG_CPU_ARM_ARMV4T is not set
# CONFIG_CPU_ARM_ARMV5 is not set
# CONFIG_CPU_ARM_ARMV5T is not set
# CONFIG_CPU_ARM_ARMV5TE is not set
# CONFIG_CPU_ARM_ARMV6 is not set
# CONFIG_CPU_ARM_ARMV6T2 is not set
# CONFIG_CPU_ARM_ARMV6ZK is not set
CONFIG_CPU_ARM_ARMV7A=y
CONFIG_CPU="armv7a"
CONFIG_CPU_ARMV6KPLUS=y
CONFIG_CPU_ARMV6PLUS=y
# CONFIG_PLATFORM_TYPE_exynos4 is not set
# CONFIG_PLATFORM_TYPE_imx35 is not set
# CONFIG_PLATFORM_TYPE_zedboard is not set
# CONFIG_PLATFORM_TYPE_beagleboard is not set
# CONFIG_PLATFORM_TYPE_rv_pbx is not set
# CONFIG_PLATFORM_TYPE_exynos5 is not set
# CONFIG_PLATFORM_TYPE_kirkwood is not set
# CONFIG_PLATFORM_TYPE_ls1012afrdm is not set
# CONFIG_PLATFORM_TYPE_pandaboard is not set
# CONFIG_PLATFORM_TYPE_arm_virt is not set
# CONFIG_PLATFORM_TYPE_tegra2 is not set
# CONFIG_PLATFORM_TYPE_rv is not set
# CONFIG_PLATFORM_TYPE_rv_vexpress_a15 is not set
# CONFIG_PLATFORM_TYPE_cubieboard2 is not set
# CONFIG_PLATFORM_TYPE_omap3_am33xx is not set
# CONFIG_PLATFORM_TYPE_parallella is not set
# CONFIG_PLATFORM_TYPE_rpi_b is not set
# CONFIG_PLATFORM_TYPE_imx21 is not set
# CONFIG_PLATFORM_TYPE_imx51 is not set
# CONFIG_PLATFORM_TYPE_ls1021atwr is not set
# CONFIG_PLATFORM_TYPE_tegra3 is not set
# CONFIG_PLATFORM_TYPE_imx7 is not set
# CONFIG_PLATFORM_TYPE_imx28 is not set
# CONFIG_PLATFORM_TYPE_omap3evm is not set
# CONFIG_PLATFORM_TYPE_rcar3_m3 is not set
# CONFIG_PLATFORM_TYPE_zynqmp is not set
CONFIG_PLATFORM_TYPE_imx6=y
# CONFIG_PLATFORM_TYPE_imx6ul is not set
# CONFIG_PLATFORM_TYPE_armada38x is not set
# CONFIG_PLATFORM_TYPE_omap5 is not set
# CONFIG_PLATFORM_TYPE_rv_vexpress is not set
# CONFIG_PLATFORM_TYPE_rpi_a is not set
# CONFIG_PLATFORM_TYPE_integrator is not set
# CONFIG_PLATFORM_TYPE_custom is not set
CONFIG_PLATFORM_TYPE="imx6"
# CONFIG_USE_DROPS_STDDIR is not set
# CONFIG_USE_DICE is not set
CONFIG_DROPS_STDDIR="/path/to/l4re"
CONFIG_DROPS_INSTDIR="/path/to/l4re"
CONFIG_BID_COLORED_PHASES=y
#
# Building
#
CONFIG_YACC="yacc"
CONFIG_LEX="flex"
CONFIG_CTAGS="ctags"
CONFIG_ETAGS="etags"
CONFIG_HAVE_LDSO=y
CONFIG_INT_CPP_NAME_SWITCH=y
CONFIG_INT_LD_NAME_SWITCH=y
# CONFIG_BID_STRIP_PROGS is not set
# CONFIG_BID_GCC_OMIT_FP is not set
# CONFIG_BID_GCC_ENABLE_STACK_PROTECTOR is not set
# CONFIG_BID_BUILD_DOC is not set
# CONFIG_RELEASE_MODE is not set
CONFIG_MAKECONFS_ADD=""

3
repos/base-foc/lib/mk/spec/imx6q_sabrelite/kernel-foc.mk Normal file
View File

@ -0,0 +1,3 @@
KERNEL_CONFIG := $(REP_DIR)/config/imx6q_sabrelite.kernel
include $(REP_DIR)/lib/mk/kernel-foc.inc

5
repos/base-foc/lib/mk/spec/imx6q_sabrelite/syscall-foc.mk Normal file
View File

@ -0,0 +1,5 @@
L4_CONFIG := $(call select_from_repositories,config/imx6q_sabrelite.user)
L4_BIN_DIR := $(LIB_CACHE_DIR)/syscall-foc/build/bin/arm_armv7a
include $(REP_DIR)/lib/mk/spec/arm/syscall-foc.inc

14
repos/base-hw/lib/mk/spec/imx6q_sabrelite/bootstrap-hw.mk Normal file
View File

@ -0,0 +1,14 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/imx6q_sabrelite
SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/imx6q_sabrelite/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 4
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc

18
repos/base-hw/lib/mk/spec/imx6q_sabrelite/core-hw.mk Normal file
View File

@ -0,0 +1,18 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Josef Söntgen
# \author Martin Stein
# \date 2014-02-25
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/imx6q_sabrelite
# add C++ sources
SRC_CC += platform_services.cc
NR_OF_CPUS = 4
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/cortex_a9/core-hw.inc

0
repos/base-hw/lib/mk/spec/imx6/core-hw.mk → repos/base-hw/lib/mk/spec/wand_quad/core-hw.mk
View File

88
repos/base-hw/src/bootstrap/spec/imx6q_sabrelite/board.h Normal file
View File

@ -0,0 +1,88 @@
/*
* \brief i.MX6Quad Sabrelite specific board definitions
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_
#include <drivers/defs/imx6q_sabrelite.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Imx6q_sabrelite;
struct L2_cache;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
}
struct Board::L2_cache : Hw::Pl310
{
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio)
{
Aux::access_t aux = 0;
Aux::Full_line_of_zero::set(aux, true);
Aux::Associativity::set(aux, Aux::Associativity::WAY_16);
Aux::Way_size::set(aux, Aux::Way_size::KB_64);
Aux::Share_override::set(aux, true);
Aux::Replacement_policy::set(aux, Aux::Replacement_policy::PRAND);
Aux::Ns_lockdown::set(aux, true);
Aux::Data_prefetch::set(aux, true);
Aux::Inst_prefetch::set(aux, true);
Aux::Early_bresp::set(aux, true);
write<Aux>(aux);
Tag_ram::access_t tag_ram = 0;
Tag_ram::Setup_latency::set(tag_ram, 2);
Tag_ram::Read_latency::set(tag_ram, 3);
Tag_ram::Write_latency::set(tag_ram, 1);
write<Tag_ram>(tag_ram);
Data_ram::access_t data_ram = 0;
Data_ram::Setup_latency::set(data_ram, 2);
Data_ram::Read_latency::set(data_ram, 3);
Data_ram::Write_latency::set(data_ram, 1);
write<Data_ram>(data_ram);
Prefetch_ctrl::access_t prefetch = 0;
Prefetch_ctrl::Data_prefetch::set(prefetch, 1);
Prefetch_ctrl::Inst_prefetch::set(prefetch, 1);
write<Prefetch_ctrl>(prefetch | 0xF);
}
using Hw::Pl310::invalidate;
void enable()
{
Pl310::mask_interrupts();
write<Control::Enable>(1);
}
void disable() {
write<Control::Enable>(0);
}
};
#endif /* _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_ */

218
repos/base-hw/src/bootstrap/spec/imx6q_sabrelite/platform.cc Normal file
View File

@ -0,0 +1,218 @@
/*
* \brief Specific bootstrap implementations
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
#include <spec/arm/imx_aipstz.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_BASE, RAM_SIZE }),
core_mmio(Memory_region { UART_2_MMIO_BASE,
UART_2_MMIO_SIZE },
Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE })
{
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)
{ 0x20e0004, 0x48613005 },
{ 0x20e0008, 0x0 },
{ 0x20e000c, 0x1e00040 },
{ 0x20e0020, 0xfffd4000 },
{ 0x20e0030, 0xf004490 },
{ 0x20e0034, 0x593e4a4 },
{ 0x20e004c, 0x3 },
{ 0x20e0050, 0x3 },
{ 0x20e0054, 0x3 },
{ 0x20e015c, 0x0 },
{ 0x20e0160, 0x0 },
{ 0x20e0164, 0x0 },
{ 0x20e0168, 0x0 },
{ 0x20e0170, 0x0 },
{ 0x20e0174, 0x0 },
{ 0x20e0178, 0x0 },
{ 0x20e017c, 0x0 },
{ 0x20e0180, 0x0 },
{ 0x20e0184, 0x0 },
{ 0x20e0188, 0x0 },
{ 0x20e018c, 0x0 },
{ 0x20e0190, 0x0 },
{ 0x20e0194, 0x0 },
{ 0x20e0198, 0x0 },
{ 0x20e019c, 0x0 },
{ 0x20e01a0, 0x0 },
{ 0x20e01a4, 0x0 },
{ 0x20e01a8, 0x0 },
{ 0x20e01ac, 0x0 },
{ 0x20e01b0, 0x0 },
{ 0x20e01b4, 0x0 },
{ 0x20e01b8, 0x0 },
{ 0x20e01bc, 0x0 },
{ 0x20e01c0, 0x0 },
{ 0x20e01c4, 0x0 },
{ 0x20e01c8, 0x0 },
{ 0x20e01cc, 0x0 },
{ 0x20e0208, 0x2 },
{ 0x20e020c, 0x2 },
{ 0x20e0218, 0x2 },
{ 0x20e0220, 0x0 },
{ 0x20e0224, 0x3 },
{ 0x20e0230, 0x11 },
{ 0x20e02b8, 0x0 },
{ 0x20e02f4, 0x0 },
{ 0x20e033c, 0x2 },
{ 0x20e0344, 0x3 },
{ 0x20e0348, 0x2 },
{ 0x20e035c, 0x3 },
{ 0x20e0360, 0x130b0 },
{ 0x20e0364, 0x110b0 },
{ 0x20e0368, 0x130b0 },
{ 0x20e036c, 0x10030 },
{ 0x20e0370, 0x10030 },
{ 0x20e0374, 0x10030 },
{ 0x20e0378, 0x10030 },
{ 0x20e037c, 0x10030 },
{ 0x20e0388, 0x10030 },
{ 0x20e03b0, 0xb1 },
{ 0x20e03bc, 0xb0 },
{ 0x20e03c0, 0xb0 },
{ 0x20e0470, 0x10 },
{ 0x20e0474, 0x10 },
{ 0x20e0478, 0x10 },
{ 0x20e047c, 0x10 },
{ 0x20e0484, 0x10 },
{ 0x20e0488, 0x10 },
{ 0x20e048c, 0x10 },
{ 0x20e0490, 0x10 },
{ 0x20e0494, 0x10 },
{ 0x20e0498, 0x10 },
{ 0x20e049c, 0x10 },
{ 0x20e04a0, 0x10 },
{ 0x20e04a4, 0x10 },
{ 0x20e04a8, 0x10 },
{ 0x20e04ac, 0x10 },
{ 0x20e04b0, 0x10 },
{ 0x20e04b4, 0x10 },
{ 0x20e04b8, 0x10 },
{ 0x20e04bc, 0x10 },
{ 0x20e04c0, 0x10 },
{ 0x20e04c4, 0x10 },
{ 0x20e04c8, 0x10 },
{ 0x20e04cc, 0x10 },
{ 0x20e04d0, 0x10 },
{ 0x20e04d4, 0x10 },
{ 0x20e04d8, 0x10 },
{ 0x20e04dc, 0x10 },
{ 0x20e04e0, 0x10 },
{ 0x20e04e4, 0x100b0 },
{ 0x20e04e8, 0x100b0 },
{ 0x20e0508, 0x100b0 },
{ 0x20e05f0, 0x30b0 },
{ 0x20e05f4, 0x17059 },
{ 0x20e0600, 0xb1 },
{ 0x20e061c, 0x30b0 },
{ 0x20e069c, 0x1f0b0 },
{ 0x20e06a4, 0x10059 },
{ 0x20e06e0, 0x10059 },
{ 0x20e0724, 0x1b0b1 },
{ 0x20e072c, 0x1b0b1 },
{ 0x20e0730, 0x1b0b1 },
{ 0x20e0744, 0x130b0 },
{ 0x20e07c4, 0x1 },
{ 0x20e0944, 0x1 },
// (Global Power Controller)
{ 0x20dc008, 0x70f7f01b },
{ 0x20dc00c, 0xff79b60f },
{ 0x20dc010, 0xfffe0003 },
{ 0x20dc014, 0xfef7f9ff },
// (Power Management Unit)
{ 0x20c8140, 0x4c0013 },
{ 0x20c8150, 0x4010088 },
{ 0x20c8160, 0x8000040b },
{ 0x20c8170, 0xff672f67 },
// (Clock Controller Module)
{ 0x20c4018, 0x10204 },
{ 0x20c402c, 0x7348c1 },
{ 0x20c4030, 0x33e71f92 },
{ 0x20c4034, 0x12088 },
{ 0x20c4038, 0x12090 },
{ 0x20c4054, 0x78 },
{ 0x20c4060, 0x10e0101 },
{ 0x20c4064, 0x2fe62 },
{ 0x20c4068, 0xc03f0f },
{ 0x20c406c, 0x30fc00 },
{ 0x20c4070, 0x3ff0033 },
{ 0x20c4074, 0x3f3300c3 },
{ 0x20c4078, 0xc303 },
{ 0x20c4080, 0xf03 },
{ 0x20c8010, 0x80003040 },
{ 0x20c8070, 0x1006 },
{ 0x20c80a0, 0x1028 },
{ 0x20c80b0, 0x0 },
{ 0x20c80c0, 0xf4240 },
{ 0x20c80e0, 0x80182001 },
{ 0x20c80f0, 0xd3d150cc },
{ 0x20c8100, 0x5018d0db }
};
unsigned num_values = sizeof(initial_values) / (2*sizeof(unsigned long));
for (unsigned i = 0; i < num_values; i++)
*((volatile unsigned long*)initial_values[i][0]) = initial_values[i][1];
}
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
return (err == ARM_764369) ? true : false; }
void Bootstrap::Cpu::wake_up_all_cpus(void * const entry)
{
struct Src : Genode::Mmio
{
struct Scr : Register<0x0, 32>
{
struct Core_1_reset : Bitfield<14,1> {};
struct Core_2_reset : Bitfield<15,1> {};
struct Core_3_reset : Bitfield<16,1> {};
struct Core_1_enable : Bitfield<22,1> {};
struct Core_2_enable : Bitfield<23,1> {};
struct Core_3_enable : Bitfield<24,1> {};
};
struct Gpr1 : Register<0x20, 32> {}; /* ep core 0 */
struct Gpr3 : Register<0x28, 32> {}; /* ep core 1 */
struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE)
{
write<Gpr3>((Gpr3::access_t)entry);
write<Gpr5>((Gpr5::access_t)entry);
write<Gpr7>((Gpr7::access_t)entry);
Scr::access_t v = read<Scr>();
Scr::Core_1_enable::set(v,1);
Scr::Core_1_reset::set(v,1);
Scr::Core_2_enable::set(v,1);
Scr::Core_2_reset::set(v,1);
Scr::Core_3_enable::set(v,1);
Scr::Core_3_reset::set(v,1);
write<Scr>(v);
}
};
Src src(entry);
}

40
repos/base-hw/src/core/spec/imx6q_sabrelite/board.h Normal file
View File

@ -0,0 +1,40 @@
/*
* \brief Board driver
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
/* base includes */
#include <drivers/defs/imx6q_sabrelite.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Imx6q_sabrelite;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
static constexpr bool SMP = true;
L2_cache & l2_cache();
}
#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */

39
repos/base/include/drivers/defs/imx6.h
View File

@ -18,6 +18,45 @@
namespace Imx6 {
enum {
/* device IO memory */
MMIO_BASE = 0x00000000,
MMIO_SIZE = 0x10000000,
UART_1_IRQ = 58,
UART_1_MMIO_BASE = 0x02020000,
UART_1_MMIO_SIZE = 0x00004000,
UART_2_IRQ = 59,
UART_2_MMIO_BASE = 0x021e8000,
UART_2_MMIO_SIZE = 0x00004000,
/* timer */
EPIT_2_IRQ = 89,
EPIT_2_MMIO_BASE = 0x020d4000,
EPIT_2_MMIO_SIZE = 0x00004000,
/* ARM IP Bus control */
AIPS_1_MMIO_BASE = 0x0207c000,
AIPS_1_MMIO_SIZE = 0x00004000,
AIPS_2_MMIO_BASE = 0x0217c000,
AIPS_2_MMIO_SIZE = 0x00004000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
/* L2 cache controller */
PL310_MMIO_BASE = 0x00a02000,
PL310_MMIO_SIZE = 0x00001000,
/* System reset controller */
SRC_MMIO_BASE = 0x20d8000,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 5,
/* SD host controller */
SDHC_IRQ = 54,
SDHC_MMIO_BASE = 0x02190000,

30
repos/base/include/drivers/defs/imx6q_sabrelite.h Normal file
View File

@ -0,0 +1,30 @@
/*
* \brief MMIO and IRQ definitions of the i.MX6Quad Sabrelite
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__IMX6Q_SABRELITE_H_
#define _INCLUDE__DRIVERS__DEFS__IMX6Q_SABRELITE_H_
/* Genode includes */
#include <drivers/defs/imx6.h>
namespace Imx6q_sabrelite {
using namespace Imx6;
enum {
RAM_BASE = 0x10000000,
RAM_SIZE = 0x40000000,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__IMX6Q_SABRELITE_H_ */

35
repos/base/include/drivers/defs/wand_quad.h
View File

@ -28,41 +28,6 @@ namespace Wand_quad {
/* normal RAM */
RAM0_BASE = 0x10000000,
RAM0_SIZE = 0x80000000,
/* device IO memory */
MMIO_BASE = 0x00000000,
MMIO_SIZE = 0x10000000,
UART_1_IRQ = 58,
UART_1_MMIO_BASE = 0x02020000,
UART_1_MMIO_SIZE = 0x00004000,
/* timer */
EPIT_2_IRQ = 89,
EPIT_2_MMIO_BASE = 0x020d4000,
EPIT_2_MMIO_SIZE = 0x00004000,
/* ARM IP Bus control */
AIPS_1_MMIO_BASE = 0x0207c000,
AIPS_1_MMIO_SIZE = 0x00004000,
AIPS_2_MMIO_BASE = 0x0217c000,
AIPS_2_MMIO_SIZE = 0x00004000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
/* L2 cache controller */
PL310_MMIO_BASE = 0x00a02000,
PL310_MMIO_SIZE = 0x00001000,
/* System reset controller */
SRC_MMIO_BASE = 0x20d8000,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 5,
};
};

5
repos/base/mk/spec/imx6q_sabrelite.mk Normal file
View File

@ -0,0 +1,5 @@
SPECS += imx6
REP_INC_DIR += include/spec/imx6q_sabrelite
include $(BASE_DIR)/mk/spec/imx6.mk

3
tool/builddir/build.conf/run_kernel_imx6q_sabrelite Normal file
View File

@ -0,0 +1,3 @@
# kernel to use (foc, hw)
KERNEL ?= hw

36
tool/create_builddir
View File

@ -12,7 +12,7 @@ PLATFORM = $(MAKECMDGOALS)
PLATFORMS = x86_32 x86_64 panda pbxa9 rpi arndale imx53_qsb imx53_qsb_tz \
usb_armory wand_quad odroid_xu odroid_x2 zynq_qemu muen \
riscv_spike linux
imx6q_sabrelite riscv_spike linux
PLATFORMS_DEPR = linux_x86 linux_arm fiasco_x86 okl4_x86 pistachio_x86 \
nova_x86_32 nova_x86_64 hw_x86_64 foc_x86_32 foc_x86_64 \
@ -143,6 +143,7 @@ BUILD_CONF(imx53_qsb) := run_kernel_hw run_boot_dir repos
BUILD_CONF(imx53_qsb_tz) := run_kernel_hw run_boot_dir repos
BUILD_CONF(usb_armory) := run_kernel_hw run_boot_dir repos
BUILD_CONF(wand_quad) := run_kernel_wand_quad run_boot_dir repos
BUILD_CONF(imx6q_sabrelite) := run_kernel_imx6q_sabrelite run_boot_dir repos
BUILD_CONF(odroid_xu) := run_kernel_hw run_boot_dir repos
BUILD_CONF(odroid_x2) := run_kernel_foc run_boot_dir repos
BUILD_CONF(zynq_qemu) := run_kernel_hw run_qemu run_opt_hw run_boot_dir qemu_opt_arm repos
@ -216,22 +217,23 @@ HOST_SPEC_ARCH := ${SPEC_ARCH(${UNAME_MACHINE})}
# SPECS definitions
#
SPECS(x86_32) := x86_32
SPECS(x86_64) := x86_64
SPECS(pbxa9) := pbxa9
SPECS(panda) := panda
SPECS(rpi) := rpi
SPECS(arndale) := arndale
SPECS(imx53_qsb) := imx53_qsb
SPECS(imx53_qsb_tz) := imx53_qsb trustzone
SPECS(usb_armory) := usb_armory trustzone
SPECS(wand_quad) := wand_quad
SPECS(odroid_xu) := odroid_xu
SPECS(odroid_x2) := odroid_x2
SPECS(zynq_qemu) := zynq_qemu
SPECS(muen) := muen x86_64
SPECS(riscv_spike) := riscv
SPECS(linux) := $(HOST_SPEC_ARCH)
SPECS(x86_32) := x86_32
SPECS(x86_64) := x86_64
SPECS(pbxa9) := pbxa9
SPECS(panda) := panda
SPECS(rpi) := rpi
SPECS(arndale) := arndale
SPECS(imx53_qsb) := imx53_qsb
SPECS(imx53_qsb_tz) := imx53_qsb trustzone
SPECS(usb_armory) := usb_armory trustzone
SPECS(wand_quad) := wand_quad
SPECS(imx6q_sabrelite) := imx6q_sabrelite
SPECS(odroid_xu) := odroid_xu
SPECS(odroid_x2) := odroid_x2
SPECS(zynq_qemu) := zynq_qemu
SPECS(muen) := muen x86_64
SPECS(riscv_spike) := riscv
SPECS(linux) := $(HOST_SPEC_ARCH)
# deprecated platforms
SPECS(linux_x86) := $(HOST_SPEC_ARCH)

1
tool/run/boot_dir/foc
View File

@ -16,6 +16,7 @@ proc core_link_address { } {
if {[have_spec pbxa9 ]} { return "0x76000000" }
if {[have_spec odroid_x2]} { return "0x80100000" }
if {[have_spec imx53 ]} { return "0x70140000" }
if {[have_spec imx6q_sabrelite ]} { return "0x10140000" }
puts stderr "Error: platform not supported, core link address unknown"
exit 1

24
tool/run/boot_dir/hw
View File

@ -6,17 +6,18 @@ proc binary_name_timer { } { return "hw_timer_drv" }
proc run_boot_string { } { return "\nkernel initialized" }
proc bootstrap_link_address { } {
if {[have_spec "odroid_xu"]} { return "0x88000000" }
if {[have_spec "pbxa9"]} { return "0x70000000" }
if {[have_spec "usb_armory"]} { return "0x72000000" }
if {[have_spec "x86_64"]} { return "0x00200000" }
if {[have_spec "wand_quad"]} { return "0x10001000" }
if {[have_spec "imx53_qsb"]} { return "0x70010000" }
if {[have_spec "arndale"]} { return "0x88000000" }
if {[have_spec "panda"]} { return "0x88000000" }
if {[have_spec "zynq"]} { return "0x00100000" }
if {[have_spec "riscv"]} { return "0x81000000" }
if {[have_spec "rpi"]} { return "0x00800000" }
if {[have_spec "odroid_xu"]} { return "0x88000000" }
if {[have_spec "pbxa9"]} { return "0x70000000" }
if {[have_spec "usb_armory"]} { return "0x72000000" }
if {[have_spec "x86_64"]} { return "0x00200000" }
if {[have_spec "wand_quad"]} { return "0x10001000" }
if {[have_spec "imx6q_sabrelite"]} { return "0x10001000" }
if {[have_spec "imx53_qsb"]} { return "0x70010000" }
if {[have_spec "arndale"]} { return "0x88000000" }
if {[have_spec "panda"]} { return "0x88000000" }
if {[have_spec "zynq"]} { return "0x00100000" }
if {[have_spec "riscv"]} { return "0x81000000" }
if {[have_spec "rpi"]} { return "0x00800000" }
puts "unknown platform no linker address known"
exit -1
@ -210,6 +211,7 @@ proc base_src { } {
if {[have_spec pbxa9]} { return base-hw-pbxa9 }
if {[have_spec rpi]} { return base-hw-rpi }
if {[have_spec wand_quad]} { return base-hw-wand_quad }
if {[have_spec imx6q_sabrelite]} { return base-hw-imx6q_sabrelite }
if {[have_spec odroid_xu]} { return base-hw-odroid_xu }
if {[have_spec imx53_qsb] && ![have_spec trustzone]} { return base-hw-imx53_qsb }
if {[have_spec imx53_qsb] && [have_spec trustzone]} { return base-hw-imx53_qsb_tz }