219 lines
5.5 KiB
C++
219 lines
5.5 KiB
C++
/*
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* \brief Specific bootstrap implementations
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* \author Stefan Kalkowski
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* \date 2019-01-05
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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#include <spec/arm/imx_aipstz.h>
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using namespace Board;
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Bootstrap::Platform::Board::Board()
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: early_ram_regions(Memory_region { RAM_BASE, RAM_SIZE }),
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core_mmio(Memory_region { UART_2_MMIO_BASE,
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UART_2_MMIO_SIZE },
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Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
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CORTEX_A9_PRIVATE_MEM_SIZE },
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Memory_region { PL310_MMIO_BASE,
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PL310_MMIO_SIZE })
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{
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Aipstz aipstz_1(AIPS_1_MMIO_BASE);
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Aipstz aipstz_2(AIPS_2_MMIO_BASE);
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static volatile unsigned long initial_values[][2] {
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// (IOMUX Controller)
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{ 0x20e0004, 0x48613005 },
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{ 0x20e0008, 0x0 },
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{ 0x20e000c, 0x1e00040 },
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{ 0x20e0020, 0xfffd4000 },
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{ 0x20e0030, 0xf004490 },
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{ 0x20e0034, 0x593e4a4 },
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{ 0x20e004c, 0x3 },
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{ 0x20e0050, 0x3 },
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{ 0x20e0054, 0x3 },
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{ 0x20e015c, 0x0 },
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{ 0x20e0160, 0x0 },
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{ 0x20e0164, 0x0 },
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{ 0x20e0168, 0x0 },
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{ 0x20e0170, 0x0 },
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{ 0x20e0174, 0x0 },
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{ 0x20e0178, 0x0 },
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{ 0x20e017c, 0x0 },
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{ 0x20e0180, 0x0 },
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{ 0x20e0184, 0x0 },
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{ 0x20e0188, 0x0 },
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{ 0x20e018c, 0x0 },
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{ 0x20e0190, 0x0 },
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{ 0x20e0194, 0x0 },
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{ 0x20e0198, 0x0 },
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{ 0x20e019c, 0x0 },
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{ 0x20e01a0, 0x0 },
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{ 0x20e01a4, 0x0 },
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{ 0x20e01a8, 0x0 },
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{ 0x20e01ac, 0x0 },
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{ 0x20e01b0, 0x0 },
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{ 0x20e01b4, 0x0 },
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{ 0x20e01b8, 0x0 },
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{ 0x20e01bc, 0x0 },
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{ 0x20e01c0, 0x0 },
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{ 0x20e01c4, 0x0 },
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{ 0x20e01c8, 0x0 },
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{ 0x20e01cc, 0x0 },
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{ 0x20e0208, 0x2 },
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{ 0x20e020c, 0x2 },
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{ 0x20e0218, 0x2 },
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{ 0x20e0220, 0x0 },
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{ 0x20e0224, 0x3 },
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{ 0x20e0230, 0x11 },
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{ 0x20e02b8, 0x0 },
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{ 0x20e02f4, 0x0 },
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{ 0x20e033c, 0x2 },
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{ 0x20e0344, 0x3 },
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{ 0x20e0348, 0x2 },
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{ 0x20e035c, 0x3 },
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{ 0x20e0360, 0x130b0 },
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{ 0x20e0364, 0x110b0 },
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{ 0x20e0368, 0x130b0 },
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{ 0x20e036c, 0x10030 },
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{ 0x20e0370, 0x10030 },
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{ 0x20e0374, 0x10030 },
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{ 0x20e0378, 0x10030 },
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{ 0x20e037c, 0x10030 },
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{ 0x20e0388, 0x10030 },
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{ 0x20e03b0, 0xb1 },
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{ 0x20e03bc, 0xb0 },
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{ 0x20e03c0, 0xb0 },
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{ 0x20e0470, 0x10 },
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{ 0x20e0474, 0x10 },
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{ 0x20e0478, 0x10 },
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{ 0x20e047c, 0x10 },
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{ 0x20e0484, 0x10 },
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{ 0x20e0488, 0x10 },
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{ 0x20e048c, 0x10 },
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{ 0x20e0490, 0x10 },
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{ 0x20e0494, 0x10 },
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{ 0x20e0498, 0x10 },
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{ 0x20e049c, 0x10 },
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{ 0x20e04a0, 0x10 },
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{ 0x20e04a4, 0x10 },
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{ 0x20e04a8, 0x10 },
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{ 0x20e04ac, 0x10 },
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{ 0x20e04b0, 0x10 },
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{ 0x20e04b4, 0x10 },
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{ 0x20e04b8, 0x10 },
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{ 0x20e04bc, 0x10 },
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{ 0x20e04c0, 0x10 },
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{ 0x20e04c4, 0x10 },
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{ 0x20e04c8, 0x10 },
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{ 0x20e04cc, 0x10 },
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{ 0x20e04d0, 0x10 },
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{ 0x20e04d4, 0x10 },
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{ 0x20e04d8, 0x10 },
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{ 0x20e04dc, 0x10 },
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{ 0x20e04e0, 0x10 },
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{ 0x20e04e4, 0x100b0 },
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{ 0x20e04e8, 0x100b0 },
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{ 0x20e0508, 0x100b0 },
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{ 0x20e05f0, 0x30b0 },
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{ 0x20e05f4, 0x17059 },
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{ 0x20e0600, 0xb1 },
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{ 0x20e061c, 0x30b0 },
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{ 0x20e069c, 0x1f0b0 },
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{ 0x20e06a4, 0x10059 },
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{ 0x20e06e0, 0x10059 },
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{ 0x20e0724, 0x1b0b1 },
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{ 0x20e072c, 0x1b0b1 },
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{ 0x20e0730, 0x1b0b1 },
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{ 0x20e0744, 0x130b0 },
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{ 0x20e07c4, 0x1 },
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{ 0x20e0944, 0x1 },
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// (Global Power Controller)
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{ 0x20dc008, 0x70f7f01b },
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{ 0x20dc00c, 0xff79b60f },
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{ 0x20dc010, 0xfffe0003 },
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{ 0x20dc014, 0xfef7f9ff },
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// (Power Management Unit)
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{ 0x20c8140, 0x4c0013 },
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{ 0x20c8150, 0x4010088 },
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{ 0x20c8160, 0x8000040b },
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{ 0x20c8170, 0xff672f67 },
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// (Clock Controller Module)
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{ 0x20c4018, 0x10204 },
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{ 0x20c402c, 0x7348c1 },
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{ 0x20c4030, 0x33e71f92 },
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{ 0x20c4034, 0x12088 },
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{ 0x20c4038, 0x12090 },
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{ 0x20c4054, 0x78 },
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{ 0x20c4060, 0x10e0101 },
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{ 0x20c4064, 0x2fe62 },
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{ 0x20c4068, 0xc03f0f },
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{ 0x20c406c, 0x30fc00 },
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{ 0x20c4070, 0x3ff0033 },
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{ 0x20c4074, 0x3f3300c3 },
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{ 0x20c4078, 0xc303 },
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{ 0x20c4080, 0xf03 },
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{ 0x20c8010, 0x80003040 },
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{ 0x20c8070, 0x1006 },
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{ 0x20c80a0, 0x1028 },
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{ 0x20c80b0, 0x0 },
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{ 0x20c80c0, 0xf4240 },
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{ 0x20c80e0, 0x80182001 },
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{ 0x20c80f0, 0xd3d150cc },
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{ 0x20c8100, 0x5018d0db }
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};
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unsigned num_values = sizeof(initial_values) / (2*sizeof(unsigned long));
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for (unsigned i = 0; i < num_values; i++)
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*((volatile unsigned long*)initial_values[i][0]) = initial_values[i][1];
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}
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bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
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return (err == ARM_764369) ? true : false; }
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void Bootstrap::Cpu::wake_up_all_cpus(void * const entry)
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{
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struct Src : Genode::Mmio
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{
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struct Scr : Register<0x0, 32>
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{
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struct Core_1_reset : Bitfield<14,1> {};
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struct Core_2_reset : Bitfield<15,1> {};
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struct Core_3_reset : Bitfield<16,1> {};
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struct Core_1_enable : Bitfield<22,1> {};
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struct Core_2_enable : Bitfield<23,1> {};
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struct Core_3_enable : Bitfield<24,1> {};
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};
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struct Gpr1 : Register<0x20, 32> {}; /* ep core 0 */
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struct Gpr3 : Register<0x28, 32> {}; /* ep core 1 */
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struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
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struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
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Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE)
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{
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write<Gpr3>((Gpr3::access_t)entry);
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write<Gpr5>((Gpr5::access_t)entry);
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write<Gpr7>((Gpr7::access_t)entry);
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Scr::access_t v = read<Scr>();
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Scr::Core_1_enable::set(v,1);
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Scr::Core_1_reset::set(v,1);
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Scr::Core_2_enable::set(v,1);
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Scr::Core_2_reset::set(v,1);
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Scr::Core_3_enable::set(v,1);
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Scr::Core_3_reset::set(v,1);
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write<Scr>(v);
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}
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};
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Src src(entry);
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}
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