doc: minor fixes for the release notes 16.02
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@ -8,7 +8,7 @@
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With version 16.02, we add RISC-V to the Genode's supported CPU architectures,
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With version 16.02, we add RISC-V to Genode's supported CPU architectures,
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enable the secure pass-through of individual USB devices to virtual machines,
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enable the secure pass-through of individual USB devices to virtual machines,
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and update the support for the Muen and seL4 kernels.
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and update the support for the Muen and seL4 kernels.
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@ -97,9 +97,9 @@ implement inheritance. This object model is used throughout QEMU. We took the
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easy way out and just used a C++ wrapper class that contains all QEMU objects
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easy way out and just used a C++ wrapper class that contains all QEMU objects
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that are used in the USB subsystem.
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that are used in the USB subsystem.
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The next step was to develop an USB host device model. This model connects a
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The next step was to develop a USB host device model. This model connects a
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USB device attached to Genode's USB host-controller driver to the xHCI device
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USB device attached to Genode's USB host-controller driver to the xHCI device
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model. Lucky for us, QEMU already contains an USB host device model that uses
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model. Lucky for us, QEMU already contains a USB host device model that uses
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libusb, which we could use as blueprint. We implemented a USB host device that
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libusb, which we could use as blueprint. We implemented a USB host device that
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leverages Genode's custom USB session interface. This host device reacts to a
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leverages Genode's custom USB session interface. This host device reacts to a
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USB device report coming from another component such as the host-controller
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USB device report coming from another component such as the host-controller
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@ -107,7 +107,7 @@ driver. It tries to claim all devices it finds in that report and then creates
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a QEMU USB device for each of them that is attached to the xHCI device model.
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a QEMU USB device for each of them that is attached to the xHCI device model.
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The xHCI device model needs infrastructure that normally is provided by QEMU
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The xHCI device model needs infrastructure that normally is provided by QEMU
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itself such as a timer queue and PCI device handling. We introduced an QEMU
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itself such as a timer queue and PCI device handling. We introduced a QEMU
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USB controller interface _repos/libports/include/qemu/usb.h_ whose back-end
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USB controller interface _repos/libports/include/qemu/usb.h_ whose back-end
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library interface has to be implemented by a component, i.e. the VMM, that
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library interface has to be implemented by a component, i.e. the VMM, that
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wants to use the library.
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wants to use the library.
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@ -475,7 +475,7 @@ Execution on bare hardware (base-hw)
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Within the last months, the initialization code of our custom kernel got
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Within the last months, the initialization code of our custom kernel got
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re-arranged to simplify the addition of new architectures, e.g., the RISC-V
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re-arranged to simplify the addition of new architectures, e.g., the RISC-V
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port (Section [New support for the RISC-V CPU architecture]) while also make
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port (Section [New support for the RISC-V CPU architecture]) while also making
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its implementation leaner. A positive side effect of this work was the
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its implementation leaner. A positive side effect of this work was the
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generalization of multi-processor and L2-cache support for ARM's Cortex-A9
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generalization of multi-processor and L2-cache support for ARM's Cortex-A9
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CPUs. For instance, the Wandboard (Freescale i.MX6 SoC) is now driven with all
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CPUs. For instance, the Wandboard (Freescale i.MX6 SoC) is now driven with all
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