parent
f6c494497b
commit
a5c70244bf
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@ -1 +1 @@
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b925f6284e93e4865b1ee6a4b1e8c63e4e9611e0
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8b8762f34e586d96ec89085422452342c6908f80
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@ -1 +1 @@
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cc217111ff4444b66fb90dd688c09cefce6e4110
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720a329b2f1eb7b71e8b3c7542b9f744224d370a
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@ -0,0 +1,34 @@
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--- a/src/app/virtualbox/src/recompiler/VBoxRecompiler.c
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--- b/src/app/virtualbox/src/recompiler/VBoxRecompiler.c
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@@ -2664,13 +2664,14 @@
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#endif
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}
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+ bool busy_set = ((pCtx->tr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT) & DESC_TSS_BUSY_MASK;
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if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
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|| pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
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|| pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
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|| pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
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/* Qemu and AMD/Intel have different ideas about the busy flag ... */ /** @todo just fix qemu! */
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|| pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
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- ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
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+ ? (pVM->rem.s.Env.tr.flags | (busy_set ? DESC_TSS_BUSY_MASK : 0)) >> SEL_FLAGS_SHIFT
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: 0)
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|| !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
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)
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@@ -2905,13 +2906,14 @@
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#endif
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}
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+ bool busy_set = ((pCtx->tr.Attr.u & SEL_FLAGS_SMASK) << SEL_FLAGS_SHIFT) & DESC_TSS_BUSY_MASK;
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if ( pCtx->tr.Sel != pVM->rem.s.Env.tr.selector
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|| pCtx->tr.ValidSel != pVM->rem.s.Env.tr.selector
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|| pCtx->tr.u64Base != pVM->rem.s.Env.tr.base
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|| pCtx->tr.u32Limit != pVM->rem.s.Env.tr.limit
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/* Qemu and AMD/Intel have different ideas about the busy flag ... */
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|| pCtx->tr.Attr.u != ( (pVM->rem.s.Env.tr.flags >> SEL_FLAGS_SHIFT) & (SEL_FLAGS_SMASK & ~DESC_INTEL_UNUSABLE)
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- ? (pVM->rem.s.Env.tr.flags | DESC_TSS_BUSY_MASK) >> SEL_FLAGS_SHIFT
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+ ? (pVM->rem.s.Env.tr.flags | (busy_set ? DESC_TSS_BUSY_MASK : 0)) >> SEL_FLAGS_SHIFT
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: 0)
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|| !(pCtx->tr.fFlags & CPUMSELREG_FLAGS_VALID)
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)
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@ -15,3 +15,4 @@ tm_retries.patch
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vmdk.patch
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vmdk.patch
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tm_tpr.patch
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tm_tpr.patch
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tm_4s.patch
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tm_4s.patch
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rem_tss.patch
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@ -320,7 +320,6 @@ inline void check_vm_state(PVMCPU pVCpu, struct Subject_state *cur_state)
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Assert(cur_state->ldtr.base == pCtx->ldtr.u64Base);
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Assert(cur_state->ldtr.base == pCtx->ldtr.u64Base);
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if(cur_state->ldtr.sel != 0)
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if(cur_state->ldtr.sel != 0)
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Assert(cur_state->ldtr.access == pCtx->ldtr.Attr.u);
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Assert(cur_state->ldtr.access == pCtx->ldtr.Attr.u);
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Assert(pCtx->tr.Attr.u & X86_SEL_TYPE_SYS_TSS_BUSY_MASK);
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{
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{
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Assert(cur_state->tr.sel == pCtx->tr.Sel);
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Assert(cur_state->tr.sel == pCtx->tr.Sel);
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Assert(cur_state->tr.limit == pCtx->tr.u32Limit);
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Assert(cur_state->tr.limit == pCtx->tr.u32Limit);
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@ -455,7 +454,6 @@ int SUPR3CallVMMR0Fast(PVMR0 pVMR0, unsigned uOperation, VMCPUID idCpu)
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cur_state->ldtr.base = pCtx->ldtr.u64Base;
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cur_state->ldtr.base = pCtx->ldtr.u64Base;
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cur_state->ldtr.access = pCtx->ldtr.Attr.u;
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cur_state->ldtr.access = pCtx->ldtr.Attr.u;
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}
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}
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Assert(pCtx->tr.Attr.u & X86_SEL_TYPE_SYS_TSS_BUSY_MASK);
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{
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{
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cur_state->tr.sel = pCtx->tr.Sel;
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cur_state->tr.sel = pCtx->tr.Sel;
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cur_state->tr.limit = pCtx->tr.u32Limit;
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cur_state->tr.limit = pCtx->tr.u32Limit;
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@ -111,7 +111,6 @@ static inline bool vmx_load_state(Nova::Utcb * utcb, VM * pVM, PVMCPU pVCpu)
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}
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}
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/* tr */
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/* tr */
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Assert(pCtx->tr.Attr.u & X86_SEL_TYPE_SYS_TSS_BUSY_MASK);
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{
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{
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utcb->mtd |= Nova::Mtd::TR;
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utcb->mtd |= Nova::Mtd::TR;
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@ -111,7 +111,6 @@ static inline bool vmx_load_state(Nova::Utcb * utcb, VM * pVM, PVMCPU pVCpu)
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}
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}
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/* tr */
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/* tr */
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Assert(pCtx->tr.Attr.u & X86_SEL_TYPE_SYS_TSS_BUSY_MASK);
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{
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{
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utcb->mtd |= Nova::Mtd::TR;
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utcb->mtd |= Nova::Mtd::TR;
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Loading…
Reference in New Issue