hw: separate bootstrap and core strictly
* Introduce Hw namespace and library files under src/lib/hw * Introduce Bootstrap namespace * Move all initialization logic into Bootstrap namespace Ref #2388
This commit is contained in:
Stefan Kalkowski
Christian Helmuth
parent
52411c9017
commit
67ba7b89a7
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@ -1,2 +0,0 @@
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REQUIRES = x86_64
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LIBS = bootstrap-hw-muen_off
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@ -1,4 +0,0 @@
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REQUIRES = imx53
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# add library dependencies
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LIBS += bootstrap-hw-trustzone_off
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@ -5,13 +5,10 @@ LIBS = cxx
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SRC_CC += bootstrap/env.cc
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SRC_CC += bootstrap/init.cc
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SRC_CC += bootstrap/lock.cc
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SRC_CC += bootstrap/log.cc
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SRC_CC += bootstrap/platform.cc
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SRC_CC += bootstrap/thread.cc
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SRC_CC += core/capability.cc
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SRC_CC += core/core_log.cc
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SRC_CC += core/default_log.cc
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SRC_CC += core/dump_alloc.cc
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SRC_CC += core/kernel_log.cc
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SRC_CC += hw/capability.cc
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SRC_CC += lib/base/allocator_avl.cc
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SRC_CC += lib/base/avl_tree.cc
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SRC_CC += lib/base/console.cc
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@ -25,21 +22,20 @@ SRC_CC += lib/base/sleep.cc
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SRC_CC += lib/base/sliced_heap.cc
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SRC_CC += lib/startup/_main.cc
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INC_DIR += $(HW_DIR)/src/bootstrap/include
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INC_DIR += $(HW_DIR)/src/core/include
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INC_DIR += $(BASE_DIR)/src/core/include
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INC_DIR += $(HW_DIR)/src/bootstrap
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INC_DIR += $(HW_DIR)/src/lib
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INC_DIR += $(HW_DIR)/src/include
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INC_DIR += $(BASE_DIR)/src/include
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INC_DIR += $(BASE_DIR)/src/core/include # for boot_modules.h only
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# configure multiprocessor mode
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NR_OF_CPUS ?= 1
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CC_OPT += -Wa,--defsym -Wa,NR_OF_CPUS=$(NR_OF_CPUS) -DNR_OF_CPUS=$(NR_OF_CPUS)
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vpath base/% $(HW_DIR)/src
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vpath bootstrap/% $(HW_DIR)/src
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vpath hw/% $(HW_DIR)/src/lib
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vpath lib/base/% $(HW_DIR)/src
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vpath lib/muen/% $(HW_DIR)/src
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vpath lib/base/% $(BASE_DIR)/src
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vpath lib/startup/% $(BASE_DIR)/src
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vpath base/% $(HW_DIR)/src
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vpath core/% $(HW_DIR)/src
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vpath core/% $(BASE_DIR)/src
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vpath bootstrap/% $(HW_DIR)/src
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@ -11,6 +11,7 @@ INC_DIR += $(BASE_DIR)/../base-hw/src/core/include
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INC_DIR += $(BASE_DIR)/src/core/include
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INC_DIR += $(BASE_DIR)/../base-hw/src/include
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INC_DIR += $(BASE_DIR)/src/include
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INC_DIR += $(BASE_DIR)/../base-hw/src/lib
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# add C++ sources
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SRC_CC += cpu_session_component.cc
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@ -1,4 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/arm
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SRC_S += bootstrap/spec/arm/crt0.s
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -14,7 +14,6 @@ SRC_CC += spec/arm/kernel/pd.cc
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SRC_CC += spec/arm/platform_support.cc
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# add assembly sources
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SRC_S += spec/arm/kernel/crt0.s
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SRC_S += spec/arm/crt0.s
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# include less specific configuration
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@ -1,4 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/arm_v7
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SRC_CC += core/spec/arm_v7/cpu.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/arm/bootstrap-hw.inc
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@ -1,6 +1,11 @@
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SRC_CC += bootstrap/spec/arndale/cpu.cc
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SRC_CC += core/spec/arndale/pic.cc
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/arndale
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SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
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SRC_CC += bootstrap/spec/arndale/pic.cc
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SRC_CC += bootstrap/spec/arndale/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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SRC_S += bootstrap/spec/arm/crt0.s
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NR_OF_CPUS = 2
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include $(REP_DIR)/lib/mk/spec/exynos5/bootstrap-hw.inc
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include $(REP_DIR)/lib/mk/bootstrap-hw.inc
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@ -8,7 +8,7 @@
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INC_DIR += $(REP_DIR)/src/core/include/spec/arm_v7/virtualization
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# add C++ sources
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SRC_CC += spec/arndale/pic.cc
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SRC_CC += spec/arm_gic/pic.cc
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SRC_CC += spec/arndale/platform_services.cc
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SRC_CC += kernel/vm_thread_on.cc
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SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc
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@ -1,4 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/cortex_a15
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/arm_gic
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include $(BASE_DIR)/../base-hw/lib/mk/spec/arm_v7/bootstrap-hw.inc
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@ -1,9 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/smp
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/arm_gic
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/cortex_a9
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SRC_CC += core/spec/arm_gic/pic.cc
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SRC_CC += core/spec/cortex_a9/board.cc
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SRC_CC += bootstrap/spec/cortex_a9/platform.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/arm_v7/bootstrap-hw.inc
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@ -1,5 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/exynos5
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SRC_CC += bootstrap/spec/exynos5/platform.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a15/bootstrap-hw.inc
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@ -1,3 +0,0 @@
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SRC_CC += bootstrap/spec/imx53/board.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/imx53/bootstrap-hw.inc
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@ -1,3 +0,0 @@
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SRC_CC += bootstrap/spec/imx53/board_trustzone.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/imx53/bootstrap-hw.inc
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@ -1,8 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/cortex_a8
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/imx53
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/imx
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SRC_CC += core/spec/imx53/pic.cc
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SRC_CC += bootstrap/spec/imx53/platform.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/arm_v7/bootstrap-hw.inc
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@ -1 +0,0 @@
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LIBS += bootstrap-hw-trustzone
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@ -8,7 +8,6 @@
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# add C++ sources
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SRC_CC += kernel/vm_thread_off.cc
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SRC_CC += spec/imx53/platform_support.cc
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SRC_CC += spec/imx53/pic.cc
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SRC_CC += platform_services.cc
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# include less specific configuration
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@ -12,7 +12,6 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/imx53/trustzone
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# add C++ sources
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SRC_CC += spec/imx53/trustzone/platform_support.cc
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SRC_CC += spec/imx53/trustzone/platform_services.cc
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SRC_CC += spec/imx53/trustzone/pic.cc
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SRC_CC += kernel/vm_thread_on.cc
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SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc
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SRC_CC += spec/arm_v7/vm_session_component.cc
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@ -9,5 +9,7 @@
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INC_DIR += $(REP_DIR)/src/core/include/spec/imx53
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INC_DIR += $(REP_DIR)/src/core/include/spec/imx
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SRC_CC += spec/imx53/pic.cc
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# include less specific configuration
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include $(REP_DIR)/lib/mk/spec/cortex_a8/core-hw.inc
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@ -0,0 +1,16 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/imx53_qsb
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SRC_S += bootstrap/spec/arm/crt0.s
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SRC_CC += bootstrap/spec/arm/cortex_a8_mmu.cc
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/imx_tzic.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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ifneq ($(filter-out $(SPECS),trustzone),)
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SRC_CC += bootstrap/spec/imx53_qsb/platform.cc
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else
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SRC_CC += bootstrap/spec/imx53_qsb/platform_trustzone.cc
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endif
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -1,8 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/imx6
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/imx
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SRC_CC += bootstrap/spec/imx6/platform.cc
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NR_OF_CPUS = 4
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include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a9/bootstrap-hw.inc
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@ -1 +0,0 @@
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LIBS += bootstrap-hw-muen_on
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@ -1,4 +1,9 @@
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SRC_CC += bootstrap/spec/odroid_xu/cpu.cc
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SRC_CC += core/spec/arm_gic/pic.cc
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/odroid_xu
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include $(REP_DIR)/lib/mk/spec/exynos5/bootstrap-hw.inc
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SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
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SRC_CC += bootstrap/spec/arm/pic.cc
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SRC_CC += bootstrap/spec/odroid_xu/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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SRC_S += bootstrap/spec/arm/crt0.s
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include $(REP_DIR)/lib/mk/bootstrap-hw.inc
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@ -1,8 +1,11 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/panda
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/tl16c750
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SRC_CC += bootstrap/spec/panda/platform.cc
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NR_OF_CPUS = 2
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include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a9/bootstrap-hw.inc
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/panda
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
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SRC_CC += bootstrap/spec/arm/pic.cc
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SRC_CC += bootstrap/spec/panda/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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SRC_S += bootstrap/spec/arm/crt0.s
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -1,6 +1,11 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/pbxa9
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/pl011
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/pbxa9
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SRC_S += bootstrap/spec/arm/crt0.s
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
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SRC_CC += bootstrap/spec/arm/pic.cc
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SRC_CC += bootstrap/spec/pbxa9/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a9/bootstrap-hw.inc
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -1,11 +1,8 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/riscv
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/riscv
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SRC_CC += bootstrap/spec/riscv/cpu.cc
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SRC_CC += bootstrap/spec/riscv/exception_vector.cc
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SRC_CC += bootstrap/spec/riscv/platform.cc
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SRC_CC += lib/base/riscv/kernel/interface.cc
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SRC_S += bootstrap/spec/riscv/crt0.s
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SRC_S += core/spec/riscv/mode_transition.s
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SRC_S += bootstrap/spec/riscv/exception_vector.s
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -10,11 +10,9 @@ SRC_CC += spec/riscv/kernel/thread.cc
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SRC_CC += spec/riscv/kernel/pd.cc
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SRC_CC += spec/riscv/kernel/cpu.cc
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SRC_CC += spec/riscv/platform_support.cc
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SRC_CC += spec/riscv/cpu.cc
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#add assembly sources
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SRC_S += spec/riscv/mode_transition.s
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SRC_S += spec/riscv/kernel/crt0.s
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SRC_S += spec/riscv/crt0.s
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# include less specific configuration
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@ -1,10 +1,7 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/rpi
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/arm_v6
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/pl011
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/rpi
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SRC_CC += bootstrap/spec/arm_v6/cpu.cc
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SRC_CC += bootstrap/spec/rpi/platform.cc
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SRC_CC += core/spec/rpi/pic.cc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/arm/bootstrap-hw.inc
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SRC_CC += hw/spec/arm/arm_v6_cpu.cc
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SRC_S += bootstrap/spec/arm/crt0.s
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -1 +0,0 @@
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LIBS += bootstrap-hw-trustzone_on
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@ -1,9 +1,11 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/cortex_a8
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/imx53
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/imx
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/usb_armory
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SRC_CC += core/spec/imx53/pic.cc
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SRC_CC += bootstrap/spec/imx53/platform.cc
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SRC_CC += bootstrap/spec/imx53/board_trustzone.cc
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SRC_S += bootstrap/spec/arm/crt0.s
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include $(BASE_DIR)/../base-hw/lib/mk/spec/arm_v7/bootstrap-hw.inc
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SRC_CC += bootstrap/spec/arm/cortex_a8_mmu.cc
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/imx_tzic.cc
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SRC_CC += bootstrap/spec/usb_armory/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -0,0 +1,13 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/wand_quad
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SRC_S += bootstrap/spec/arm/crt0.s
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
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SRC_CC += bootstrap/spec/arm/pic.cc
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SRC_CC += bootstrap/spec/wand_quad/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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NR_OF_CPUS = 4
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -1,5 +0,0 @@
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SRC_CC += core/spec/x86_64/pic.cc
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SRC_CC += bootstrap/spec/x86_64/platform.cc
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SRC_S += bootstrap/spec/x86_64/crt0_translation_table.s
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include $(BASE_DIR)/../base-hw/lib/mk/spec/x86_64/bootstrap-hw.inc
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@ -1,9 +0,0 @@
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REQUIRES = muen
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INC_DIR += $(REP_DIR)/src/core/include/spec/x86_64/muen
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SRC_CC += lib/muen/sinfo.cc
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SRC_CC += bootstrap/spec/x86_64/platform_muen.cc
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SRC_S += bootstrap/spec/x86_64/crt0_translation_table_muen.s
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include $(BASE_DIR)/../base-hw/lib/mk/spec/x86_64/bootstrap-hw.inc
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@ -1,5 +0,0 @@
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INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/x86_64
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SRC_S += bootstrap/spec/x86_64/crt0.s
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -1 +1,14 @@
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LIBS = bootstrap-hw-muen
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
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SRC_S += bootstrap/spec/x86_64/crt0.s
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ifneq ($(filter-out $(SPECS),muen),)
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SRC_CC += bootstrap/spec/x86_64/platform.cc
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SRC_S += bootstrap/spec/x86_64/crt0_translation_table.s
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else
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SRC_CC += lib/muen/sinfo.cc
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SRC_CC += bootstrap/spec/x86_64/platform_muen.cc
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SRC_S += bootstrap/spec/x86_64/crt0_translation_table_muen.s
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endif
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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|
|
@ -10,7 +10,6 @@ INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/x86_64
|
|||
|
||||
# add assembly sources
|
||||
SRC_S += spec/x86_64/mode_transition.s
|
||||
SRC_S += spec/x86_64/kernel/crt0.s
|
||||
SRC_S += spec/x86_64/crt0.s
|
||||
|
||||
# add C++ sources
|
||||
|
|
|
|||
|
|
@ -1,5 +0,0 @@
|
|||
INC_DIR += $(BASE_DIR)/../base-hw/src/core/include/spec/zynq
|
||||
|
||||
SRC_CC += bootstrap/spec/zynq/platform.cc
|
||||
|
||||
include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a9/bootstrap-hw.inc
|
||||
|
|
@ -1,4 +1,11 @@
|
|||
INC_DIR += $(REP_DIR)/src/core/include/spec/xilinx_uartps_0
|
||||
INC_DIR += $(REP_DIR)/src/core/include/spec/zynq_qemu
|
||||
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/zynq
|
||||
|
||||
include $(BASE_DIR)/../base-hw/lib/mk/spec/zynq/bootstrap-hw.inc
|
||||
SRC_S += bootstrap/spec/arm/crt0.s
|
||||
|
||||
SRC_CC += bootstrap/spec/arm/cpu.cc
|
||||
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
|
||||
SRC_CC += bootstrap/spec/arm/pic.cc
|
||||
SRC_CC += bootstrap/spec/zynq/platform.cc
|
||||
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
|
||||
|
||||
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
|
||||
|
|
|
|||
|
|
@ -11,11 +11,8 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* base includes */
|
||||
#include <base/env.h>
|
||||
|
||||
/* core includes */
|
||||
#include <assert.h>
|
||||
#include <hw/assert.h>
|
||||
|
||||
Genode::Env_deprecated * Genode::env_deprecated()
|
||||
{
|
||||
|
|
|
|||
|
|
@ -18,13 +18,14 @@
|
|||
#include <base/internal/globals.h>
|
||||
#include <base/internal/unmanaged_singleton.h>
|
||||
|
||||
Platform & platform() { return *unmanaged_singleton<Platform>(); }
|
||||
Bootstrap::Platform & Bootstrap::platform() {
|
||||
return *unmanaged_singleton<Bootstrap::Platform>(); }
|
||||
|
||||
extern "C" void init() __attribute__ ((noreturn));
|
||||
|
||||
extern "C" void init()
|
||||
{
|
||||
Genode::init_log();
|
||||
platform().enable_mmu();
|
||||
platform().start_core();
|
||||
Bootstrap::platform().enable_mmu();
|
||||
Bootstrap::platform().start_core();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
*/
|
||||
|
||||
#include <base/lock.h>
|
||||
#include <assert.h>
|
||||
#include <hw/assert.h>
|
||||
|
||||
Genode::Cancelable_lock::Cancelable_lock(Genode::Cancelable_lock::State state)
|
||||
: _state(state), _owner(nullptr) { }
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* \brief Access to the log facility
|
||||
* \author Norman Feske
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2016-05-03
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2016 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* Genode includes */
|
||||
#include <base/log.h>
|
||||
|
||||
/* base-internal includes */
|
||||
#include <base/internal/globals.h>
|
||||
#include <base/internal/output.h>
|
||||
#include <base/internal/unmanaged_singleton.h>
|
||||
|
||||
#include <board.h>
|
||||
|
||||
using namespace Bootstrap;
|
||||
using namespace Genode;
|
||||
|
||||
struct Buffer
|
||||
{
|
||||
struct Write_fn
|
||||
{
|
||||
Serial & serial;
|
||||
|
||||
Write_fn(Serial & serial) : serial(serial) {}
|
||||
|
||||
void operator () (char const *s)
|
||||
{
|
||||
enum { LINE_FEED = 10, CARRIAGE_RETURN = 13 };
|
||||
|
||||
for (unsigned i = 0; i < Genode::strlen(s); i++) {
|
||||
if (s[i] == LINE_FEED) serial.put_char(CARRIAGE_RETURN);
|
||||
serial.put_char(s[i]);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
enum { BAUD_RATE = 115200 };
|
||||
|
||||
Serial serial { UART_BASE, UART_CLOCK, BAUD_RATE };
|
||||
Write_fn function { serial };
|
||||
Buffered_output<512, Write_fn> buffer { function };
|
||||
Log log { buffer };
|
||||
};
|
||||
|
||||
|
||||
Genode::Log &Genode::Log::log() {
|
||||
return unmanaged_singleton<Buffer>()->log; }
|
||||
|
||||
|
||||
void Genode::init_log() { };
|
||||
|
|
@ -11,14 +11,14 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* base-internal includes */
|
||||
#include <base/internal/crt0.h>
|
||||
#include <hw/assert.h>
|
||||
|
||||
/* core includes */
|
||||
#include <assert.h>
|
||||
#include <boot_modules.h>
|
||||
#include <platform.h>
|
||||
|
||||
using namespace Bootstrap;
|
||||
|
||||
|
||||
/*****************************
|
||||
** Platform::Ram_allocator **
|
||||
|
|
@ -27,6 +27,7 @@
|
|||
void * Platform::Ram_allocator::alloc_aligned(size_t size, unsigned align)
|
||||
{
|
||||
using namespace Genode;
|
||||
using namespace Hw;
|
||||
|
||||
void * ret;
|
||||
assert(Base::alloc_aligned(round_page(size), &ret,
|
||||
|
|
@ -55,18 +56,16 @@ void Platform::Ram_allocator::remove(Memory_region const & region) {
|
|||
******************/
|
||||
|
||||
Platform::Pd::Pd(Platform::Ram_allocator & alloc)
|
||||
: table_base(alloc.alloc_aligned(sizeof(Bootinfo::Table),
|
||||
Bootinfo::Table::ALIGNM_LOG2)),
|
||||
allocator_base(alloc.alloc_aligned(sizeof(Bootinfo::Table_allocator),
|
||||
Bootinfo::Table::ALIGNM_LOG2)),
|
||||
table(*Genode::construct_at<Bootinfo::Table>(table_base)),
|
||||
allocator(*Genode::construct_at<Bootinfo::Table_allocator>(allocator_base))
|
||||
: table_base(alloc.alloc_aligned(sizeof(Table), Table::ALIGNM_LOG2)),
|
||||
array_base(alloc.alloc_aligned(sizeof(Table_array), Table::ALIGNM_LOG2)),
|
||||
table(*Genode::construct_at<Table>(table_base)),
|
||||
array(*Genode::construct_at<Table_array>(array_base))
|
||||
{
|
||||
using namespace Genode;
|
||||
map_insert(Mapping((addr_t)table_base, (addr_t)table_base,
|
||||
sizeof(Bootinfo::Table), PAGE_FLAGS_KERN_DATA));
|
||||
map_insert(Mapping((addr_t)allocator_base, (addr_t)allocator_base,
|
||||
sizeof(Bootinfo::Table_allocator), PAGE_FLAGS_KERN_DATA));
|
||||
sizeof(Table), Hw::PAGE_FLAGS_KERN_DATA));
|
||||
map_insert(Mapping((addr_t)array_base, (addr_t)array_base,
|
||||
sizeof(Table_array), Hw::PAGE_FLAGS_KERN_DATA));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -74,8 +73,8 @@ void Platform::Pd::map(Mapping m)
|
|||
{
|
||||
try {
|
||||
table.insert_translation(m.virt(), m.phys(), m.size(), m.flags(),
|
||||
allocator.alloc());
|
||||
} catch(Genode::Allocator::Out_of_memory) {
|
||||
array.alloc());
|
||||
} catch (Hw::Out_of_tables &) {
|
||||
Genode::error("translation table needs to much RAM");
|
||||
} catch (...) {
|
||||
Genode::error("invalid mapping ", m);
|
||||
|
|
@ -97,6 +96,7 @@ void Platform::Pd::map_insert(Mapping m)
|
|||
addr_t Platform::_load_elf()
|
||||
{
|
||||
using namespace Genode;
|
||||
using namespace Hw;
|
||||
|
||||
addr_t start = ~0UL;
|
||||
addr_t end = 0;
|
||||
|
|
@ -166,7 +166,7 @@ Platform::Platform()
|
|||
/* temporarily map all bootstrap memory 1:1 for transition to core */
|
||||
// FIXME do not insert as mapping for core
|
||||
core_pd->map_insert(Mapping(bootstrap_region.base, bootstrap_region.base,
|
||||
bootstrap_region.size, PAGE_FLAGS_KERN_TEXT));
|
||||
bootstrap_region.size, Hw::PAGE_FLAGS_KERN_TEXT));
|
||||
|
||||
/* map memory-mapped I/O for core */
|
||||
board.core_mmio.for_each_mapping([&] (Mapping const & m) {
|
||||
|
|
@ -176,11 +176,12 @@ Platform::Platform()
|
|||
addr_t const elf_end = _load_elf();
|
||||
|
||||
/* setup boot info page */
|
||||
void * bi_base = ram_alloc.alloc(sizeof(Bootinfo));
|
||||
core_pd->map_insert(Mapping((addr_t)bi_base, elf_end, sizeof(Bootinfo),
|
||||
PAGE_FLAGS_KERN_TEXT));
|
||||
Bootinfo & bootinfo =
|
||||
*construct_at<Bootinfo>(bi_base, &core_pd->table, &core_pd->allocator,
|
||||
void * bi_base = ram_alloc.alloc(sizeof(Boot_info));
|
||||
core_pd->map_insert(Mapping((addr_t)bi_base, elf_end, sizeof(Boot_info),
|
||||
Hw::PAGE_FLAGS_KERN_TEXT));
|
||||
Boot_info & bootinfo =
|
||||
*construct_at<Boot_info>(bi_base, (addr_t)&core_pd->table,
|
||||
(addr_t)&core_pd->array,
|
||||
core_pd->mappings, board.core_mmio);
|
||||
|
||||
/* add all left RAM to bootinfo */
|
||||
|
|
|
|||
|
|
@ -11,40 +11,40 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_H_
|
||||
#define _PLATFORM_H_
|
||||
#ifndef _SRC__BOOTSTRAP__PLATFORM_H_
|
||||
#define _SRC__BOOTSTRAP__PLATFORM_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <base/allocator_avl.h>
|
||||
#include <base/internal/elf.h>
|
||||
#include <hw/boot_info.h>
|
||||
#include <util/reconstructible.h>
|
||||
|
||||
/* core includes */
|
||||
#include <bootinfo.h>
|
||||
#include <board.h>
|
||||
#include <cpu.h>
|
||||
#include <pic.h>
|
||||
#include <rom_fs.h>
|
||||
|
||||
using Genode::addr_t;
|
||||
using Genode::size_t;
|
||||
using Genode::Bootinfo;
|
||||
using Genode::Core_mmio;
|
||||
using Genode::Mapping;
|
||||
using Genode::Memory_region;
|
||||
using Genode::Memory_region_array;
|
||||
using Genode::Rom_module;
|
||||
namespace Bootstrap {
|
||||
|
||||
struct Platform;
|
||||
|
||||
class Platform
|
||||
using Genode::addr_t;
|
||||
using Genode::size_t;
|
||||
using Hw::Boot_info;
|
||||
using Hw::Mmio_space;
|
||||
using Hw::Mapping;
|
||||
using Hw::Memory_region;
|
||||
using Hw::Memory_region_array;
|
||||
|
||||
extern Platform & platform();
|
||||
}
|
||||
|
||||
class Bootstrap::Platform
|
||||
{
|
||||
private:
|
||||
|
||||
struct Board : Genode::Board
|
||||
struct Board : Genode::Board_base
|
||||
{
|
||||
Memory_region_array early_ram_regions;
|
||||
Memory_region_array late_ram_regions;
|
||||
Core_mmio const core_mmio;
|
||||
Mmio_space const core_mmio;
|
||||
|
||||
Board();
|
||||
};
|
||||
|
|
@ -80,7 +80,7 @@ class Platform
|
|||
_block_tree().for_each([&] (Block const & b)
|
||||
{
|
||||
if (!b.used())
|
||||
functor(Genode::Memory_region(b.addr(), b.size()));
|
||||
functor(Memory_region(b.addr(), b.size()));
|
||||
});
|
||||
}
|
||||
};
|
||||
|
|
@ -88,11 +88,14 @@ class Platform
|
|||
|
||||
struct Pd
|
||||
{
|
||||
void * const table_base;
|
||||
void * const allocator_base;
|
||||
Bootinfo::Table & table;
|
||||
Bootinfo::Table_allocator & allocator;
|
||||
Bootinfo::Mapping_pool mappings;
|
||||
using Table = Hw::Page_table;
|
||||
using Table_array = Table::Allocator::Array<Table::CORE_TRANS_TABLE_COUNT>;
|
||||
|
||||
void * const table_base;
|
||||
void * const array_base;
|
||||
Table & table;
|
||||
Table_array & array;
|
||||
Boot_info::Mapping_pool mappings;
|
||||
|
||||
Pd(Ram_allocator & alloc);
|
||||
|
||||
|
|
@ -117,8 +120,8 @@ class Platform
|
|||
};
|
||||
|
||||
Board board;
|
||||
Genode::Cpu cpu;
|
||||
Genode::Pic pic;
|
||||
Bootstrap::Cpu cpu;
|
||||
Bootstrap::Pic pic;
|
||||
Ram_allocator ram_alloc;
|
||||
Memory_region const bootstrap_region;
|
||||
Genode::Constructible<Pd> core_pd;
|
||||
|
|
@ -131,12 +134,8 @@ class Platform
|
|||
|
||||
Platform();
|
||||
|
||||
static addr_t mmio_to_virt(addr_t mmio) { return mmio; }
|
||||
|
||||
void enable_mmu();
|
||||
void start_core() __attribute__((noreturn));
|
||||
};
|
||||
|
||||
extern Platform & platform();
|
||||
|
||||
#endif /* _PLATFORM_H_ */
|
||||
#endif /* _SRC__BOOTSTRAP__PLATFORM_H_ */
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* \brief MMU initialization for Cortex A15
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
|
||||
{
|
||||
/* invalidate TLB */
|
||||
Tlbiall::write(0);
|
||||
|
||||
enum Memory_attributes {
|
||||
DEVICE_MEMORY = 0x04,
|
||||
NORMAL_MEMORY_UNCACHED = 0x44,
|
||||
NORMAL_MEMORY_CACHED = 0xff,
|
||||
};
|
||||
|
||||
/* set memory attributes in indirection register */
|
||||
Mair0::access_t mair0 = 0;
|
||||
Mair0::Attr0::set(mair0, NORMAL_MEMORY_UNCACHED);
|
||||
Mair0::Attr1::set(mair0, DEVICE_MEMORY);
|
||||
Mair0::Attr2::set(mair0, NORMAL_MEMORY_CACHED);
|
||||
Mair0::Attr3::set(mair0, DEVICE_MEMORY);
|
||||
Mair0::write(mair0);
|
||||
|
||||
/* do not use domains, but permission bits in table */
|
||||
Dacr::write(Dacr::D0::bits(1));
|
||||
|
||||
Ttbr_64bit::access_t ttbr0 = Ttbr_64bit::Ba::masked(table);
|
||||
Ttbr_64bit::Asid::set(ttbr0, 0);
|
||||
Ttbr0_64bit::write(ttbr0);
|
||||
|
||||
Ttbcr::access_t ttbcr = 0;
|
||||
Ttbcr::Irgn0::set(ttbcr, 1);
|
||||
Ttbcr::Orgn0::set(ttbcr, 1);
|
||||
Ttbcr::Sh0::set(ttbcr, 0b10);
|
||||
Ttbcr::Eae::set(ttbcr, 1);
|
||||
Ttbcr::write(ttbcr);
|
||||
|
||||
Sctlr::access_t sctlr = Sctlr::read();
|
||||
Sctlr::C::set(sctlr, 1);
|
||||
Sctlr::I::set(sctlr, 1);
|
||||
Sctlr::V::set(sctlr, 1);
|
||||
Sctlr::A::set(sctlr, 0);
|
||||
Sctlr::M::set(sctlr, 1);
|
||||
Sctlr::Z::set(sctlr, 1);
|
||||
Sctlr::write(sctlr);
|
||||
|
||||
/* invalidate branch predictor */
|
||||
Bpiall::write(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* \brief MMU initialization for Cortex A8
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2015-12-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
void Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::enable_mmu_and_caches((addr_t)core_pd->table_base);
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* \brief Cortex A9 specific page table format
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A8_PAGE_TABLE_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A8_PAGE_TABLE_H_
|
||||
|
||||
#include <hw/spec/arm/page_table.h>
|
||||
|
||||
constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() {
|
||||
return 2; }
|
||||
|
||||
constexpr bool Hw::Page_table::Descriptor_base::_smp() { return false; }
|
||||
|
||||
void Hw::Page_table::_translation_added(unsigned long, unsigned long) { }
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A8_PAGE_TABLE_H_ */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* \brief Cortex A9 specific ACTLR register settings
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_ACTLR_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_ACTLR_H_
|
||||
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
namespace Bootstrap { struct Actlr; }
|
||||
|
||||
struct Bootstrap::Actlr : Bootstrap::Cpu::Actlr
|
||||
{
|
||||
struct Smp : Bitfield<6, 1> { };
|
||||
|
||||
static void enable_smp()
|
||||
{
|
||||
auto v = read();
|
||||
Smp::set(v, 1);
|
||||
write(v);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_ACTLR_H_ */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* \brief Cpu class implementation specific to Cortex A9 SMP
|
||||
* \brief MMU initialization for Cortex A9 SMP
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2015-12-09
|
||||
*/
|
||||
|
|
@ -12,13 +12,12 @@
|
|||
*/
|
||||
|
||||
#include <base/log.h>
|
||||
#include <hw/spec/arm/cortex_a9.h>
|
||||
#include <hw/spin_lock.h>
|
||||
#include <util/mmio.h>
|
||||
|
||||
/* core includes */
|
||||
#include <kernel/lock.h>
|
||||
#include <platform.h>
|
||||
|
||||
//using namespace Kernel;
|
||||
|
||||
/* entrypoint for non-boot CPUs */
|
||||
extern "C" void * _start_setup_stack;
|
||||
|
||||
|
|
@ -30,14 +29,14 @@ class Cpu_counter
|
|||
{
|
||||
private:
|
||||
|
||||
Kernel::Lock _lock;
|
||||
Hw::Spin_lock _lock;
|
||||
volatile int _value = 0;
|
||||
|
||||
public:
|
||||
|
||||
void inc()
|
||||
{
|
||||
Kernel::Lock::Guard guard(_lock);
|
||||
Hw::Spin_lock::Guard guard(_lock);
|
||||
Genode::memory_barrier();
|
||||
_value++;
|
||||
}
|
||||
|
|
@ -67,7 +66,9 @@ struct Scu : Genode::Mmio
|
|||
struct Cpu3_way : Bitfield<12, 4> { };
|
||||
};
|
||||
|
||||
Scu(Genode::addr_t mmio) : Genode::Mmio(mmio) { }
|
||||
using Memory_map = Hw::Cpu_memory_map<Bootstrap::CPU_MMIO_BASE>;
|
||||
|
||||
Scu() : Genode::Mmio(Memory_map::SCU_MMIO_BASE) { }
|
||||
|
||||
void invalidate()
|
||||
{
|
||||
|
|
@ -96,9 +97,10 @@ struct Scu : Genode::Mmio
|
|||
*
|
||||
* See ARM's Cortex-A9 MPCore TRM r2p0 in section 5.3.5 for more details
|
||||
*/
|
||||
void Platform::enable_mmu()
|
||||
void Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
using Genode::Cpu;
|
||||
using namespace Bootstrap;
|
||||
|
||||
static volatile bool primary_cpu = true;
|
||||
static Cpu_counter data_cache_invalidated;
|
||||
static Cpu_counter data_cache_enabled;
|
||||
|
|
@ -108,61 +110,57 @@ void Platform::enable_mmu()
|
|||
if (primary) primary_cpu = false;
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::Psr::write(Cpu::Psr::init_kernel());
|
||||
Cpu::Cpsr::init();
|
||||
|
||||
/* locally initialize interrupt controller */
|
||||
pic.init_cpu_local();
|
||||
|
||||
cpu.invalidate_inner_data_cache();
|
||||
Cpu::invalidate_data_cache();
|
||||
data_cache_invalidated.inc();
|
||||
|
||||
/* primary cpu wakes up all others */
|
||||
if (primary && NR_OF_CPUS > 1) {
|
||||
board.wake_up_all_cpus(&_start_setup_stack);
|
||||
|
||||
/* send an IPI to all other cpus */
|
||||
pic.send_ipi();
|
||||
}
|
||||
if (primary && NR_OF_CPUS > 1)
|
||||
Cpu::wake_up_all_cpus(&_start_setup_stack);
|
||||
|
||||
/* wait for other cores' data cache invalidation */
|
||||
data_cache_invalidated.wait_for(NR_OF_CPUS);
|
||||
|
||||
if (primary) {
|
||||
Scu scu(Board::SCU_MMIO_BASE);
|
||||
Scu scu;
|
||||
scu.invalidate();
|
||||
Board::L2_cache l2_cache(Board::PL310_MMIO_BASE);
|
||||
Bootstrap::L2_cache l2_cache(Board::PL310_MMIO_BASE);
|
||||
l2_cache.disable();
|
||||
l2_cache.invalidate();
|
||||
scu.enable(board.errata(Platform::Board::ARM_764369));
|
||||
scu.enable(Cpu::errata(Cpu::ARM_764369));
|
||||
}
|
||||
|
||||
/* secondary cpus wait for the primary's cache activation */
|
||||
if (!primary) data_cache_enabled.wait_for(1);
|
||||
|
||||
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
|
||||
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
|
||||
|
||||
data_cache_enabled.inc();
|
||||
cpu.clean_invalidate_inner_data_cache();
|
||||
Cpu::clean_invalidate_data_cache();
|
||||
|
||||
/* wait for other cores' data cache activation */
|
||||
data_cache_enabled.wait_for(NR_OF_CPUS);
|
||||
|
||||
if (primary) {
|
||||
Board::L2_cache l2_cache(board.core_mmio.virt_addr(Board::PL310_MMIO_BASE));
|
||||
Bootstrap::L2_cache l2_cache(board.core_mmio.virt_addr(Board::PL310_MMIO_BASE));
|
||||
l2_cache.enable();
|
||||
}
|
||||
|
||||
/* secondary cpus wait for the primary's coherency activation */
|
||||
if (!primary) smp_coherency_enabled.wait_for(1);
|
||||
|
||||
Cpu::Actlr::enable_smp(board);
|
||||
Actlr::enable_smp();
|
||||
smp_coherency_enabled.inc();
|
||||
|
||||
/*
|
||||
* strangely, some older versions (imx6) seem to not work cache coherent
|
||||
* until SMP bit is set, so write back the variable here.
|
||||
*/
|
||||
cpu.clean_invalidate_inner_data_cache();
|
||||
Cpu::clean_invalidate_data_cache();
|
||||
|
||||
/* wait for other cores' coherency activation */
|
||||
smp_coherency_enabled.wait_for(NR_OF_CPUS);
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* \brief Cortex A9 specific page table format
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_PAGE_TABLE_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_PAGE_TABLE_H_
|
||||
|
||||
#include <hw/spec/arm/page_table.h>
|
||||
|
||||
constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() {
|
||||
return 2; }
|
||||
|
||||
constexpr bool Hw::Page_table::Descriptor_base::_smp() { return true; }
|
||||
|
||||
void Hw::Page_table::_translation_added(unsigned long, unsigned long) { }
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_PAGE_TABLE_H_ */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* \brief Generic MMU initialization for ARM
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
|
||||
{
|
||||
/* invalidate TLB */
|
||||
Tlbiall::write(0);
|
||||
|
||||
/* address space ID to zero */
|
||||
Cidr::write(0);
|
||||
|
||||
/* do not use domains, but permission bits in table */
|
||||
Dacr::write(Dacr::D0::bits(1));
|
||||
|
||||
Ttbcr::write(0);
|
||||
|
||||
Ttbr::access_t ttbr0 = Ttbr::Ba::masked(table);
|
||||
Ttbr::Rgn::set(ttbr0, Ttbr::CACHEABLE);
|
||||
if (Mpidr::read()) { /* check for SMP system */
|
||||
Ttbr::Irgn::set(ttbr0, Ttbr::CACHEABLE);
|
||||
Ttbr::S::set(ttbr0, 1);
|
||||
} else
|
||||
Ttbr::C::set(ttbr0, 1);
|
||||
Ttbr0::write(ttbr0);
|
||||
|
||||
Sctlr::access_t sctlr = Sctlr::read();
|
||||
Sctlr::C::set(sctlr, 1);
|
||||
Sctlr::I::set(sctlr, 1);
|
||||
Sctlr::V::set(sctlr, 1);
|
||||
Sctlr::A::set(sctlr, 0);
|
||||
Sctlr::M::set(sctlr, 1);
|
||||
Sctlr::Z::set(sctlr, 1);
|
||||
Sctlr::write(sctlr);
|
||||
|
||||
/* invalidate branch predictor */
|
||||
Bpiall::write(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* \brief CPU definitions for ARM
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-22
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__CPU_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__CPU_H_
|
||||
|
||||
#include <hw/spec/arm/cpu.h>
|
||||
|
||||
namespace Bootstrap { struct Cpu; }
|
||||
|
||||
struct Bootstrap::Cpu : Hw::Arm_cpu
|
||||
{
|
||||
struct Sctlr : Hw::Arm_cpu::Sctlr
|
||||
{
|
||||
static void init()
|
||||
{
|
||||
/*
|
||||
* disable alignment checks and
|
||||
* set exception vector to 0xffff0000
|
||||
*/
|
||||
access_t v = read();
|
||||
A::set(v, 0);
|
||||
V::set(v, 1);
|
||||
write(v);
|
||||
}
|
||||
};
|
||||
|
||||
struct Cpsr : Hw::Arm_cpu::Cpsr
|
||||
{
|
||||
static void init()
|
||||
{
|
||||
access_t v = read();
|
||||
Psr::F::set(v, 1);
|
||||
Psr::A::set(v, 1);
|
||||
Psr::M::set(v, Psr::M::SVC);
|
||||
Psr::I::set(v, 1);
|
||||
write(v);
|
||||
}
|
||||
};
|
||||
|
||||
enum Errata { ARM_764369 };
|
||||
|
||||
static bool errata(Errata);
|
||||
|
||||
static void wake_up_all_cpus(void * const ip);
|
||||
|
||||
static void enable_mmu_and_caches(Genode::addr_t table);
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__CPU_H_ */
|
||||
|
|
@ -11,8 +11,6 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
.include "macros.s"
|
||||
|
||||
.set STACK_SIZE, 4 * 16 * 1024
|
||||
|
||||
.section ".text.crt0"
|
||||
|
|
@ -20,7 +18,11 @@
|
|||
.global _start
|
||||
_start:
|
||||
|
||||
/* zero-fill BSS segment */
|
||||
|
||||
/***************************
|
||||
** Zero-fill BSS segment **
|
||||
***************************/
|
||||
|
||||
adr r0, _bss_local_start
|
||||
adr r1, _bss_local_end
|
||||
ldr r0, [r0]
|
||||
|
|
@ -34,15 +36,38 @@
|
|||
b 1b
|
||||
2:
|
||||
|
||||
.global _start_setup_stack
|
||||
|
||||
/*****************************************************
|
||||
** Setup multiprocessor-aware kernel stack-pointer **
|
||||
*****************************************************/
|
||||
|
||||
mov sp, #0 /* for boot cpu use id 0 */
|
||||
cps #31 /* change to system mode */
|
||||
|
||||
.global _start_setup_stack /* entrypoint for all cpus */
|
||||
_start_setup_stack:
|
||||
|
||||
/* setup multiprocessor-aware kernel stack-pointer */
|
||||
adr r0, _start_stack
|
||||
adr r1, _start_stack_size
|
||||
mrs r2, cpsr
|
||||
cmp r2, #31 /* check for system mode */
|
||||
mrcne p15, 0, sp, c0, c0, 5 /* read multiprocessor affinity register */
|
||||
andne sp, sp, #0xff /* set cpu id for non-boot cpu */
|
||||
cps #19 /* change to supervisor mode */
|
||||
|
||||
adr r0, _start_stack /* load stack address into r0 */
|
||||
adr r1, _start_stack_size /* load stack size per cpu into r1 */
|
||||
ldr r1, [r1]
|
||||
_init_kernel_sp r0, r1
|
||||
b init
|
||||
|
||||
add sp, #1 /* calculate stack start for CPU */
|
||||
mul r1, r1, sp
|
||||
add sp, r0, r1
|
||||
|
||||
|
||||
/************************************
|
||||
** Jump to high-level entry point **
|
||||
************************************/
|
||||
|
||||
b init
|
||||
|
||||
|
||||
_bss_local_start:
|
||||
.long _bss_start
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* \brief Board driver
|
||||
* \brief Driver for Freescale's AIPSTZ bridge
|
||||
* \author Stefan Kalkowski
|
||||
* \author Martin Stein
|
||||
* \date 2012-10-24
|
||||
|
|
@ -12,14 +12,12 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__INCLUDE__SPEC__IMX__BOARD_SUPPORT_H_
|
||||
#define _CORE__INCLUDE__SPEC__IMX__BOARD_SUPPORT_H_
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <drivers/board_base.h>
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Imx
|
||||
namespace Bootstrap
|
||||
{
|
||||
/**
|
||||
* AHB to IP Bridge
|
||||
|
|
@ -28,14 +26,9 @@ namespace Imx
|
|||
* bus peripherals.
|
||||
*/
|
||||
class Aipstz;
|
||||
|
||||
/**
|
||||
* Board driver
|
||||
*/
|
||||
class Board;
|
||||
}
|
||||
|
||||
class Imx::Aipstz : public Genode::Mmio
|
||||
class Bootstrap::Aipstz : public Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
|
|
@ -69,12 +62,10 @@ class Imx::Aipstz : public Genode::Mmio
|
|||
|
||||
public:
|
||||
|
||||
Aipstz(Genode::addr_t const base) : Genode::Mmio(base) { }
|
||||
|
||||
/**
|
||||
* Configure this module appropriately for the first kernel run
|
||||
*/
|
||||
void init()
|
||||
Aipstz(Genode::addr_t const base) : Genode::Mmio(base)
|
||||
{
|
||||
/* avoid AIPS intervention at any memory access */
|
||||
write<Mpr1>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
|
||||
|
|
@ -91,20 +82,4 @@ class Imx::Aipstz : public Genode::Mmio
|
|||
}
|
||||
};
|
||||
|
||||
class Imx::Board : public Genode::Board_base
|
||||
{
|
||||
public:
|
||||
|
||||
/**
|
||||
* Configure this module appropriately for the first kernel run
|
||||
*/
|
||||
void init()
|
||||
{
|
||||
Aipstz _aipstz_1(AIPS_1_MMIO_BASE);
|
||||
Aipstz _aipstz_2(AIPS_2_MMIO_BASE);
|
||||
_aipstz_1.init();
|
||||
_aipstz_2.init();
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _CORE__INCLUDE__SPEC__IMX__BOARD_SUPPORT_H_ */
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_ */
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
* \brief Driver for the Central Security Unit
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-11-06
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__IMX_CSU_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__IMX_CSU_H_
|
||||
|
||||
#include <util/mmio.h>
|
||||
#include <util/register.h>
|
||||
|
||||
namespace Bootstrap { struct Csu; }
|
||||
|
||||
struct Bootstrap::Csu : Genode::Mmio
|
||||
{
|
||||
template <Genode::off_t OFF>
|
||||
struct Csl : public Register<OFF, 32>
|
||||
{
|
||||
enum {
|
||||
SECURE = 0x33,
|
||||
UNSECURE = 0xff,
|
||||
};
|
||||
|
||||
struct Slave_a : Register<OFF, 32>::template Bitfield<0, 9> { };
|
||||
struct Slave_b : Register<OFF, 32>::template Bitfield<16, 9> { };
|
||||
};
|
||||
|
||||
struct Master : public Register<0x218, 32>
|
||||
{
|
||||
enum {
|
||||
SECURE_UNLOCKED,
|
||||
UNSECURE_UNLOCKED,
|
||||
SECURE_LOCKED,
|
||||
UNSECURE_LOCKED
|
||||
};
|
||||
|
||||
struct Esdhc3 : Bitfield<0,2> { };
|
||||
struct Cortex : Bitfield<2,2> { };
|
||||
struct Sdma : Bitfield<4,2> { };
|
||||
struct Gpu : Bitfield<6,2> { };
|
||||
struct Usb : Bitfield<8,2> { };
|
||||
struct Pata : Bitfield<10,2> { };
|
||||
struct Mlb : Bitfield<14,2> { };
|
||||
struct Rtic : Bitfield<18,2> { };
|
||||
struct Esdhc4 : Bitfield<20,2> { };
|
||||
struct Fec : Bitfield<22,2> { };
|
||||
struct Dap : Bitfield<24,2> { };
|
||||
struct Esdhc1 : Bitfield<26,2> { };
|
||||
struct Esdhc2 : Bitfield<28,2> { };
|
||||
};
|
||||
|
||||
struct Alarm_mask : public Register<0x230, 32> { };
|
||||
struct Irq_ctrl : public Register<0x368, 32> { };
|
||||
|
||||
typedef Csl<0x00> Csl00;
|
||||
typedef Csl<0x04> Csl01;
|
||||
typedef Csl<0x08> Csl02;
|
||||
typedef Csl<0x0c> Csl03;
|
||||
typedef Csl<0x10> Csl04;
|
||||
typedef Csl<0x14> Csl05;
|
||||
typedef Csl<0x18> Csl06;
|
||||
typedef Csl<0x1c> Csl07;
|
||||
typedef Csl<0x20> Csl08;
|
||||
typedef Csl<0x24> Csl09;
|
||||
typedef Csl<0x28> Csl10;
|
||||
typedef Csl<0x2c> Csl11;
|
||||
typedef Csl<0x30> Csl12;
|
||||
typedef Csl<0x34> Csl13;
|
||||
typedef Csl<0x38> Csl14;
|
||||
typedef Csl<0x3c> Csl15;
|
||||
typedef Csl<0x40> Csl16;
|
||||
typedef Csl<0x44> Csl17;
|
||||
typedef Csl<0x48> Csl18;
|
||||
typedef Csl<0x4c> Csl19;
|
||||
typedef Csl<0x50> Csl20;
|
||||
typedef Csl<0x54> Csl21;
|
||||
typedef Csl<0x58> Csl22;
|
||||
typedef Csl<0x5c> Csl23;
|
||||
typedef Csl<0x60> Csl24;
|
||||
typedef Csl<0x64> Csl25;
|
||||
typedef Csl<0x68> Csl26;
|
||||
typedef Csl<0x6c> Csl27;
|
||||
typedef Csl<0x70> Csl28;
|
||||
typedef Csl<0x74> Csl29;
|
||||
typedef Csl<0x78> Csl30;
|
||||
typedef Csl<0x7c> Csl31;
|
||||
|
||||
Csu(Genode::addr_t base,
|
||||
bool secure_uart,
|
||||
bool secure_gpio,
|
||||
bool secure_esdhc,
|
||||
bool secure_i2c) : Genode::Mmio(base)
|
||||
{
|
||||
/* Power (CCM, SRC, DPLLIP1-4, GPC and OWIRE) */
|
||||
write<Csl09::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* AHBMAX S0-S2 */
|
||||
write<Csl09::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl20::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl06::Slave_b>(Csl00::UNSECURE);
|
||||
|
||||
/* AHBMAX M6 */
|
||||
write<Csl10::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* Timer (EPIT, GPT) TODO */
|
||||
write<Csl04::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* UART 1-5 */
|
||||
Csl00::access_t uart_csl =
|
||||
secure_uart ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl07::Slave_b>(uart_csl);
|
||||
write<Csl08::Slave_a>(uart_csl);
|
||||
write<Csl26::Slave_a>(uart_csl);
|
||||
write<Csl30::Slave_b>(uart_csl);
|
||||
write<Csl19::Slave_a>(uart_csl);
|
||||
|
||||
/* GPIO */
|
||||
Csl00::access_t gpio_csl =
|
||||
secure_gpio ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl00::Slave_b>(gpio_csl);
|
||||
write<Csl01::Slave_a>(gpio_csl);
|
||||
write<Csl01::Slave_b>(gpio_csl);
|
||||
write<Csl02::Slave_a>(gpio_csl);
|
||||
|
||||
/* IOMUXC TODO */
|
||||
write<Csl05::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* SDMA TODO */
|
||||
write<Csl15::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* USB */
|
||||
write<Csl00::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* TVE */
|
||||
write<Csl22::Slave_b>(Csl00::SECURE);
|
||||
|
||||
/* I2C */
|
||||
Csl00::access_t i2c_csl =
|
||||
secure_i2c ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl18::Slave_a>(i2c_csl);
|
||||
write<Csl17::Slave_b>(i2c_csl);
|
||||
write<Csl31::Slave_a>(i2c_csl);
|
||||
|
||||
/* IPU */
|
||||
write<Csl24::Slave_a>(Csl00::SECURE);
|
||||
|
||||
/* Audio */
|
||||
write<Csl18::Slave_b>(Csl00::UNSECURE);
|
||||
|
||||
/* SATA */
|
||||
write<Csl07::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* FEC */
|
||||
write<Csl22::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* SDHCI 1-4 */
|
||||
Csl00::access_t esdhc_csl =
|
||||
secure_esdhc ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl25::Slave_a>(esdhc_csl);
|
||||
write<Csl25::Slave_b>(esdhc_csl);
|
||||
write<Csl28::Slave_a>(esdhc_csl);
|
||||
write<Csl28::Slave_b>(esdhc_csl);
|
||||
|
||||
/* SPDIF */
|
||||
write<Csl29::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* GPU 2D */
|
||||
write<Csl24::Slave_b>(Csl00::SECURE);
|
||||
|
||||
/* GPU 3D */
|
||||
write<Csl27::Slave_b>(Csl00::SECURE);
|
||||
|
||||
write<Csl02::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl03::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl03::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl04::Slave_b>(Csl00::UNSECURE); // SRTC
|
||||
write<Csl05::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl06::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl08::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl10::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl11::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl11::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl12::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl12::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl13::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl13::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl14::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl14::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl15::Slave_b>(Csl00::UNSECURE); // SCC
|
||||
write<Csl16::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl16::Slave_b>(Csl00::UNSECURE); // RTIC
|
||||
write<Csl17::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl19::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl20::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl21::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl21::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl23::Slave_a>(Csl00::SECURE); //VPU
|
||||
write<Csl23::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl26::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl27::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl29::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl30::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl31::Slave_b>(Csl00::UNSECURE);
|
||||
|
||||
/* DMA from graphical subsystem is considered to be secure */
|
||||
write<Master::Gpu>(Master::SECURE_UNLOCKED);
|
||||
|
||||
/* all other DMA operations are insecure */
|
||||
write<Master::Sdma>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Usb>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Pata>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Fec>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Dap>(Master::UNSECURE_UNLOCKED);
|
||||
|
||||
Master::access_t esdhc_master =
|
||||
secure_esdhc ? Master::SECURE_UNLOCKED
|
||||
: Master::UNSECURE_UNLOCKED;
|
||||
write<Master::Esdhc1>(esdhc_master);
|
||||
write<Master::Esdhc2>(esdhc_master);
|
||||
write<Master::Esdhc3>(esdhc_master);
|
||||
write<Master::Esdhc4>(esdhc_master);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__IMX_CSU_H_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* \brief Freescale's TrustZone aware interrupt controller
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
|
||||
Hw::Pic::Pic() : Genode::Mmio(Genode::Board_base::IRQ_CONTROLLER_BASE)
|
||||
{
|
||||
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
|
||||
write<Intsec::Nonsecure>(!Bootstrap::secure_irq(i), i);
|
||||
if (!Bootstrap::secure_irq(i)) write<Priority>(0x80, i);
|
||||
write<Enclear::Clear_enable>(1, i);
|
||||
}
|
||||
write<Priomask::Mask>(0xff);
|
||||
Intctrl::access_t v = 0;
|
||||
Intctrl::Enable::set(v, 1);
|
||||
Intctrl::Nsen::set(v, 1);
|
||||
Intctrl::Nsen_mask::set(v, 1);
|
||||
write<Intctrl>(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* \brief Programmable interrupt controller for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <spec/arm/pic.h>
|
||||
#include <platform.h>
|
||||
|
||||
using Memory_map = Hw::Cpu_memory_map<Bootstrap::CPU_MMIO_BASE>;
|
||||
using Bootstrap::Platform;
|
||||
|
||||
void Bootstrap::Pic::init_cpu_local()
|
||||
{
|
||||
/* disable the priority filter */
|
||||
_cpui.write<Cpu_interface::Pmr::Priority>(_distr.min_priority());
|
||||
|
||||
/* disable preemption of IRQ handling by other IRQs */
|
||||
_cpui.write<Cpu_interface::Bpr::Binary_point>(~0);
|
||||
|
||||
/* enable device */
|
||||
_cpui.write<Cpu_interface::Ctlr::Enable>(1);
|
||||
}
|
||||
|
||||
|
||||
Hw::Pic::Pic()
|
||||
: _distr(Memory_map::IRQ_CONTROLLER_DISTR_BASE),
|
||||
_cpui (Memory_map::IRQ_CONTROLLER_CPU_BASE),
|
||||
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
|
||||
_max_irq(_distr.max_irq())
|
||||
{
|
||||
/* disable device */
|
||||
_distr.write<Distributor::Ctlr::Enable>(0);
|
||||
|
||||
/* configure every shared peripheral interrupt */
|
||||
for (unsigned i = min_spi; i <= _max_irq; i++) {
|
||||
_distr.write<Distributor::Icfgr::Edge_triggered>(0, i);
|
||||
_distr.write<Distributor::Ipriorityr::Priority>(0, i);
|
||||
_distr.write<Distributor::Icenabler::Clear_enable>(1, i);
|
||||
}
|
||||
/* enable device */
|
||||
_distr.write<Distributor::Ctlr::Enable>(1);
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* \brief Interrupt controller definitions for ARM
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-22
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__PIC_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__PIC_H_
|
||||
|
||||
#include <hw/spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap { struct Pic; }
|
||||
|
||||
struct Bootstrap::Pic : Hw::Pic
|
||||
{
|
||||
void init_cpu_local();
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__PIC_H_ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* \brief Arndale specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-03
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
|
||||
#include <hw/spec/arm/cortex_a15.h>
|
||||
#include <hw/spec/arm/lpae.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
class L2_cache;
|
||||
|
||||
using Serial = Genode::Exynos_uart_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::UART_2_MMIO_BASE,
|
||||
UART_CLOCK = Genode::Board_base::UART_2_CLOCK,
|
||||
CPU_MMIO_BASE = Genode::Board_base::IRQ_CONTROLLER_BASE,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */
|
||||
|
|
@ -15,89 +15,6 @@
|
|||
#include <cpu.h>
|
||||
#include <translation_table.h>
|
||||
|
||||
static unsigned char hyp_mode_stack[1024];
|
||||
|
||||
|
||||
static inline void prepare_nonsecure_world()
|
||||
{
|
||||
using Nsacr = Genode::Cpu::Nsacr;
|
||||
using Cpsr = Genode::Cpu::Psr;
|
||||
using Scr = Genode::Cpu::Scr;
|
||||
|
||||
/* if we are already in HYP mode we're done (depends on u-boot version) */
|
||||
if (Cpsr::M::get(Cpsr::read()) == Cpsr::M::HYP)
|
||||
return;
|
||||
|
||||
/* ARM generic timer counter freq needs to be set in secure mode */
|
||||
volatile unsigned long * mct_control = (unsigned long*) 0x101C0240;
|
||||
*mct_control = 0x100;
|
||||
asm volatile ("mcr p15, 0, %0, c14, c0, 0" :: "r" (24000000));
|
||||
|
||||
/*
|
||||
* enable coprocessor 10 + 11 access and SMP bit access in auxiliary control
|
||||
* register for non-secure world
|
||||
*/
|
||||
Nsacr::access_t nsacr = 0;
|
||||
Nsacr::Cpnsae10::set(nsacr, 1);
|
||||
Nsacr::Cpnsae11::set(nsacr, 1);
|
||||
Nsacr::Ns_smp::set(nsacr, 1);
|
||||
Nsacr::write(nsacr);
|
||||
|
||||
asm volatile (
|
||||
"msr sp_mon, sp \n" /* copy current mode's sp */
|
||||
"msr lr_mon, lr \n" /* copy current mode's lr */
|
||||
"cps #22 \n" /* switch to monitor mode */
|
||||
);
|
||||
|
||||
Scr::access_t scr = 0;
|
||||
Scr::Ns::set(scr, 1);
|
||||
Scr::Fw::set(scr, 1);
|
||||
Scr::Aw::set(scr, 1);
|
||||
Scr::Scd::set(scr, 1);
|
||||
Scr::Hce::set(scr, 1);
|
||||
Scr::Sif::set(scr, 1);
|
||||
Scr::write(scr);
|
||||
}
|
||||
|
||||
|
||||
static inline void prepare_hypervisor(Genode::Translation_table & table)
|
||||
{
|
||||
using Genode::Cpu;
|
||||
|
||||
/* set hypervisor exception vector */
|
||||
Cpu::hyp_exception_entry_at((void*)0xfff00000); /* FIXME */
|
||||
|
||||
/* set hypervisor's translation table */
|
||||
Cpu::Httbr::translation_table((Genode::addr_t)&table);
|
||||
|
||||
/* prepare MMU usage by hypervisor code */
|
||||
Cpu::Htcr::write(Cpu::Ttbcr::init_virt_kernel());
|
||||
Cpu::Hcptr::write(Cpu::Hcptr::init());
|
||||
Cpu::Hmair0::write(Cpu::Mair0::init_virt_kernel());
|
||||
Cpu::Vtcr::write(Cpu::Vtcr::init());
|
||||
Cpu::Hsctlr::write(Cpu::Sctlr::init_value());
|
||||
}
|
||||
|
||||
|
||||
static inline void switch_to_supervisor_mode()
|
||||
{
|
||||
using Psr = Genode::Cpu::Psr;
|
||||
|
||||
Psr::access_t psr = 0;
|
||||
Psr::M::set(psr, Psr::M::SVC);
|
||||
Psr::F::set(psr, 1);
|
||||
Psr::I::set(psr, 1);
|
||||
|
||||
asm volatile (
|
||||
"msr sp_svc, sp \n" /* copy current mode's sp */
|
||||
"msr lr_svc, lr \n" /* copy current mode's lr */
|
||||
"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
|
||||
"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
|
||||
"msr spsr_cxfs, %[psr] \n" /* set psr for supervisor mode */
|
||||
"adr lr, 1f \n" /* load exception return address */
|
||||
"eret \n" /* exception return */
|
||||
"1:":: [psr] "r" (psr), [stack] "r" (&hyp_mode_stack));
|
||||
}
|
||||
|
||||
|
||||
void Genode::Cpu::init(Genode::Translation_table & table)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* \brief Programmable interrupt controller for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <hw/spec/arm/cortex_a15.h>
|
||||
#include <spec/arm/pic.h>
|
||||
#include <platform.h>
|
||||
|
||||
using Memory_map = Hw::Cpu_memory_map<Bootstrap::CPU_MMIO_BASE>;
|
||||
using Bootstrap::Platform;
|
||||
|
||||
void Bootstrap::Pic::init_cpu_local()
|
||||
{
|
||||
_cpui.write<Cpu_interface::Ctlr>(0);
|
||||
|
||||
/* mark software-generated IRQs as being non-secure */
|
||||
for (unsigned i = 0; i < min_spi; i++)
|
||||
_distr.write<Distributor::Igroupr::Group_status>(1, i);
|
||||
|
||||
/* disable the priority filter */
|
||||
_cpui.write<Cpu_interface::Pmr::Priority>(_distr.min_priority());
|
||||
|
||||
/* disable preemption of IRQ handling by other IRQs */
|
||||
_cpui.write<Cpu_interface::Bpr::Binary_point>(~0);
|
||||
|
||||
/* enable device */
|
||||
Cpu_interface::Ctlr::access_t v = 0;
|
||||
Cpu_interface::Ctlr::Enable_grp0::set(v, 1);
|
||||
Cpu_interface::Ctlr::Enable_grp1::set(v, 1);
|
||||
Cpu_interface::Ctlr::Fiq_en::set(v, 1);
|
||||
_cpui.write<Cpu_interface::Ctlr>(v);
|
||||
}
|
||||
|
||||
|
||||
Hw::Pic::Pic()
|
||||
: _distr(Memory_map::IRQ_CONTROLLER_DISTR_BASE),
|
||||
_cpui(Memory_map::IRQ_CONTROLLER_CPU_BASE),
|
||||
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
|
||||
_max_irq(_distr.max_irq())
|
||||
{
|
||||
/* disable device */
|
||||
_distr.write<Distributor::Ctlr>(0);
|
||||
|
||||
/* configure every shared peripheral interrupt */
|
||||
for (unsigned i = min_spi; i <= _max_irq; i++) {
|
||||
/* mark as non-secure */
|
||||
_distr.write<Distributor::Igroupr::Group_status>(1, i);
|
||||
_distr.write<Distributor::Icfgr::Edge_triggered>(0, i);
|
||||
_distr.write<Distributor::Ipriorityr::Priority>(0, i);
|
||||
_distr.write<Distributor::Icenabler::Clear_enable>(1, i);
|
||||
}
|
||||
/* enable device */
|
||||
Distributor::Ctlr::access_t v = 0;
|
||||
Distributor::Ctlr::Enable_grp0::set(v, 1);
|
||||
Distributor::Ctlr::Enable_grp1::set(v, 1);
|
||||
_distr.write<Distributor::Ctlr>(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* \brief Parts of platform that are specific to Arndale
|
||||
* \author Martin Stein
|
||||
* \date 2012-04-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
|
||||
static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
|
||||
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE },
|
||||
Memory_region { MCT_MMIO_BASE, MCT_MMIO_SIZE },
|
||||
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
static inline void prepare_nonsecure_world()
|
||||
{
|
||||
using Cpu = Hw::Arm_cpu;
|
||||
|
||||
/* if we are already in HYP mode we're done (depends on u-boot version) */
|
||||
if (Cpu::Psr::M::get(Cpu::Cpsr::read()) == Cpu::Psr::M::HYP)
|
||||
return;
|
||||
|
||||
/* ARM generic timer counter freq needs to be set in secure mode */
|
||||
volatile unsigned long * mct_control = (unsigned long*) 0x101C0240;
|
||||
*mct_control = 0x100;
|
||||
Cpu::Cntfrq::write(24000000);
|
||||
|
||||
/*
|
||||
* enable coprocessor 10 + 11 access and SMP bit access in auxiliary control
|
||||
* register for non-secure world
|
||||
*/
|
||||
Cpu::Nsacr::access_t nsacr = 0;
|
||||
Cpu::Nsacr::Cpnsae10::set(nsacr, 1);
|
||||
Cpu::Nsacr::Cpnsae11::set(nsacr, 1);
|
||||
Cpu::Nsacr::Ns_smp::set(nsacr, 1);
|
||||
Cpu::Nsacr::write(nsacr);
|
||||
|
||||
asm volatile (
|
||||
"msr sp_mon, sp \n" /* copy current mode's sp */
|
||||
"msr lr_mon, lr \n" /* copy current mode's lr */
|
||||
"cps #22 \n" /* switch to monitor mode */
|
||||
);
|
||||
|
||||
Cpu::Scr::access_t scr = 0;
|
||||
Cpu::Scr::Ns::set(scr, 1);
|
||||
Cpu::Scr::Fw::set(scr, 1);
|
||||
Cpu::Scr::Aw::set(scr, 1);
|
||||
Cpu::Scr::Scd::set(scr, 1);
|
||||
Cpu::Scr::Hce::set(scr, 1);
|
||||
Cpu::Scr::Sif::set(scr, 1);
|
||||
Cpu::Scr::write(scr);
|
||||
}
|
||||
|
||||
|
||||
static inline void prepare_hypervisor(Genode::addr_t table)
|
||||
{
|
||||
using Cpu = Hw::Arm_cpu;
|
||||
|
||||
/* set hypervisor exception vector */
|
||||
Cpu::Hvbar::write(0xfff00000); /* FIXME */
|
||||
|
||||
/* set hypervisor's translation table */
|
||||
Cpu::Httbr_64bit::write(table);
|
||||
|
||||
Cpu::Ttbcr::access_t ttbcr = 0;
|
||||
Cpu::Ttbcr::Irgn0::set(ttbcr, 1);
|
||||
Cpu::Ttbcr::Orgn0::set(ttbcr, 1);
|
||||
Cpu::Ttbcr::Sh0::set(ttbcr, 2);
|
||||
Cpu::Ttbcr::Eae::set(ttbcr, 1);
|
||||
|
||||
/* prepare MMU usage by hypervisor code */
|
||||
Cpu::Htcr::write(ttbcr);
|
||||
|
||||
/* don't trap on cporocessor 10 + 11, but all others */
|
||||
Cpu::Hcptr::access_t hcptr = 0;
|
||||
Cpu::Hcptr::Tcp<0>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<1>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<2>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<3>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<4>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<5>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<6>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<7>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<8>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<9>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<12>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcp<13>::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tta::set(hcptr, 1);
|
||||
Cpu::Hcptr::Tcpac::set(hcptr, 1);
|
||||
Cpu::Hcptr::write(hcptr);
|
||||
|
||||
enum Memory_attributes {
|
||||
DEVICE_MEMORY = 0x04,
|
||||
NORMAL_MEMORY_UNCACHED = 0x44,
|
||||
NORMAL_MEMORY_CACHED = 0xff,
|
||||
};
|
||||
|
||||
Cpu::Mair0::access_t mair0 = 0;
|
||||
Cpu::Mair0::Attr0::set(mair0, NORMAL_MEMORY_UNCACHED);
|
||||
Cpu::Mair0::Attr1::set(mair0, DEVICE_MEMORY);
|
||||
Cpu::Mair0::Attr2::set(mair0, NORMAL_MEMORY_CACHED);
|
||||
Cpu::Mair0::Attr3::set(mair0, DEVICE_MEMORY);
|
||||
Cpu::Hmair0::write(mair0);
|
||||
|
||||
Cpu::Vtcr::access_t vtcr = ttbcr;
|
||||
Cpu::Vtcr::Sl0::set(vtcr, 1); /* set to starting level 1 */
|
||||
Cpu::Vtcr::write(vtcr);
|
||||
|
||||
Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read();
|
||||
Cpu::Sctlr::C::set(sctlr, 1);
|
||||
Cpu::Sctlr::I::set(sctlr, 1);
|
||||
Cpu::Sctlr::V::set(sctlr, 1);
|
||||
Cpu::Sctlr::A::set(sctlr, 0);
|
||||
Cpu::Sctlr::M::set(sctlr, 1);
|
||||
Cpu::Sctlr::Z::set(sctlr, 1);
|
||||
Cpu::Hsctlr::write(sctlr);
|
||||
}
|
||||
|
||||
|
||||
static inline void switch_to_supervisor_mode()
|
||||
{
|
||||
using Cpsr = Hw::Arm_cpu::Psr;
|
||||
|
||||
Cpsr::access_t cpsr = 0;
|
||||
Cpsr::M::set(cpsr, Cpsr::M::SVC);
|
||||
Cpsr::F::set(cpsr, 1);
|
||||
Cpsr::I::set(cpsr, 1);
|
||||
|
||||
asm volatile (
|
||||
"msr sp_svc, sp \n" /* copy current mode's sp */
|
||||
"msr lr_svc, lr \n" /* copy current mode's lr */
|
||||
"msr elr_hyp, lr \n" /* copy current mode's lr to hyp lr */
|
||||
"msr sp_hyp, %[stack] \n" /* copy to hyp stack pointer */
|
||||
"msr spsr_cxfs, %[cpsr] \n" /* set psr for supervisor mode */
|
||||
"adr lr, 1f \n" /* load exception return address */
|
||||
"eret \n" /* exception return */
|
||||
"1:":: [cpsr] "r" (cpsr), [stack] "r" (&hyp_mode_stack));
|
||||
}
|
||||
|
||||
|
||||
void Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
static volatile bool primary_cpu = true;
|
||||
pic.init_cpu_local();
|
||||
|
||||
prepare_nonsecure_world();
|
||||
prepare_hypervisor((addr_t)core_pd->table_base);
|
||||
switch_to_supervisor_mode();
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::Cpsr::init();
|
||||
|
||||
cpu.invalidate_data_cache();
|
||||
|
||||
/* primary cpu wakes up all others */
|
||||
if (primary_cpu && NR_OF_CPUS > 1) {
|
||||
primary_cpu = false;
|
||||
cpu.wake_up_all_cpus(&_start_setup_stack);
|
||||
}
|
||||
|
||||
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
|
||||
}
|
||||
|
||||
|
||||
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
|
||||
{
|
||||
*(void * volatile *)Genode::Board_base::IRAM_BASE = ip;
|
||||
asm volatile("dsb; sev;");
|
||||
}
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* \brief Specific core implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-01-27
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <platform.h>
|
||||
#include <drivers/trustzone.h>
|
||||
|
||||
using Genode::Memory_region;
|
||||
|
||||
Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { Trustzone::SECURE_RAM_BASE,
|
||||
Trustzone::SECURE_RAM_SIZE }),
|
||||
core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
|
||||
Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { CSU_BASE, CSU_SIZE }) {
|
||||
init(); }
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* \brief Specific i.MX53 bootstrap implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <platform.h>
|
||||
#include <cpu.h>
|
||||
|
||||
|
||||
void Platform::enable_mmu()
|
||||
{
|
||||
Genode::Cpu::Sctlr::init();
|
||||
|
||||
cpu.enable_mmu_and_caches((addr_t)core_pd->table_base);
|
||||
}
|
||||
|
||||
|
||||
void Genode::Cpu::translation_added(Genode::addr_t const addr,
|
||||
Genode::size_t const size) { }
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* \brief i.MX53 Quickstart board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-03-22
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/imx_tzic.h>
|
||||
|
||||
#include <spec/arm/cortex_a8_page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
using Hw::Pic;
|
||||
using Serial = Genode::Imx_uart_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::UART_1_MMIO_BASE,
|
||||
UART_CLOCK = 0, /* ignored value */
|
||||
};
|
||||
|
||||
bool secure_irq(unsigned irq);
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_ */
|
||||
|
|
@ -1,25 +1,29 @@
|
|||
/*
|
||||
* \brief Specific bootstrap implementations
|
||||
* \brief Specific i.MX53 bootstrap implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-01-27
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
#include <board.h>
|
||||
#include <spec/arm/imx_aipstz.h>
|
||||
|
||||
using Genode::Memory_region;
|
||||
bool Bootstrap::secure_irq(unsigned i) { return true; }
|
||||
|
||||
Platform::Board::Board()
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM0_BASE, RAM0_SIZE },
|
||||
Memory_region { RAM1_BASE, RAM1_SIZE }),
|
||||
core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
|
||||
Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE }) {
|
||||
init(); }
|
||||
Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE })
|
||||
{
|
||||
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
|
||||
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* \brief Specific i.MX53 bootstrap implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
#include <spec/imx53/drivers/trustzone.h>
|
||||
#include <spec/arm/imx_aipstz.h>
|
||||
#include <spec/arm/imx_csu.h>
|
||||
|
||||
bool Bootstrap::secure_irq(unsigned i)
|
||||
{
|
||||
using Board = Genode::Board_base;
|
||||
|
||||
if (i == Board::EPIT_1_IRQ) return true;
|
||||
if (i == Board::EPIT_2_IRQ) return true;
|
||||
if (i == Board::I2C_2_IRQ) return true;
|
||||
if (i == Board::I2C_3_IRQ) return true;
|
||||
if (i >= Board::GPIO1_IRQL && i <= Board::GPIO4_IRQH) return true;
|
||||
if (i >= Board::GPIO5_IRQL && i <= Board::GPIO7_IRQH) return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { Trustzone::SECURE_RAM_BASE,
|
||||
Trustzone::SECURE_RAM_SIZE }),
|
||||
core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
|
||||
Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { CSU_BASE, CSU_SIZE })
|
||||
{
|
||||
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
|
||||
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
|
||||
|
||||
/* set exception vector entry */
|
||||
Cpu::Mvbar::write(0xfff00000);
|
||||
|
||||
/* enable coprocessor 10 + 11 access for TZ VMs */
|
||||
Cpu::Nsacr::access_t v = 0;
|
||||
Cpu::Nsacr::Cpnsae10::set(v, 1);
|
||||
Cpu::Nsacr::Cpnsae11::set(v, 1);
|
||||
Cpu::Nsacr::write(v);
|
||||
|
||||
/* configure central security unit */
|
||||
Csu csu(Genode::Board_base::CSU_BASE, false, true, false, true);
|
||||
}
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* \brief Specific bootstrap implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \author Josef Soentgen
|
||||
* \author Martin Stein
|
||||
* \date 2014-02-25
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2014-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <platform.h>
|
||||
#include <cpu.h>
|
||||
|
||||
using namespace Genode;
|
||||
|
||||
Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM0_BASE, RAM0_SIZE }),
|
||||
core_mmio(Memory_region { UART_1_MMIO_BASE,
|
||||
UART_1_MMIO_SIZE },
|
||||
Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
CORTEX_A9_PRIVATE_MEM_SIZE },
|
||||
Memory_region { PL310_MMIO_BASE,
|
||||
PL310_MMIO_SIZE }) { init(); }
|
||||
|
||||
|
||||
bool Cortex_a9::Board::errata(Cortex_a9::Board::Errata err)
|
||||
{
|
||||
switch (err) {
|
||||
case Cortex_a9::Board::ARM_754322:
|
||||
case Cortex_a9::Board::ARM_764369:
|
||||
case Cortex_a9::Board::ARM_775420:
|
||||
case Cortex_a9::Board::PL310_588369:
|
||||
case Cortex_a9::Board::PL310_727915:
|
||||
case Cortex_a9::Board::PL310_769419:
|
||||
return true;
|
||||
};
|
||||
return false;
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* \brief Odroid XU specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-03
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
|
||||
#include <hw/spec/arm/cortex_a15.h>
|
||||
#include <hw/spec/arm/lpae.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
class L2_cache;
|
||||
|
||||
using Serial = Genode::Exynos_uart_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::UART_2_MMIO_BASE,
|
||||
UART_CLOCK = Genode::Board_base::UART_2_CLOCK,
|
||||
CPU_MMIO_BASE = Genode::Board_base::IRQ_CONTROLLER_BASE,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/*
|
||||
* \brief Cpu-specific code for Cortex A15
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2016-01-07
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <cpu.h>
|
||||
|
||||
void Genode::Cpu::init(Genode::Translation_table&) {}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* \brief Parts of platform that are specific to Arndale
|
||||
* \brief Parts of platform that are specific to Odroid XU
|
||||
* \author Martin Stein
|
||||
* \date 2012-04-27
|
||||
*/
|
||||
|
|
@ -13,10 +13,7 @@
|
|||
|
||||
#include <platform.h>
|
||||
|
||||
/* entrypoint for non-boot CPUs */
|
||||
extern "C" void * _start_setup_stack;
|
||||
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
|
||||
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_VT_CTRL_BASE, IRQ_CONTROLLER_VT_CTRL_SIZE },
|
||||
|
|
@ -24,25 +21,11 @@ Platform::Board::Board()
|
|||
Memory_region { UART_2_MMIO_BASE, UART_2_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
void Platform::enable_mmu()
|
||||
void Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
using Genode::Cpu;
|
||||
|
||||
static volatile bool primary_cpu = true;
|
||||
pic.init_cpu_local();
|
||||
|
||||
cpu.init(*reinterpret_cast<Genode::Translation_table*>(core_pd->table_base));
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::Psr::write(Cpu::Psr::init_kernel());
|
||||
|
||||
cpu.invalidate_inner_data_cache();
|
||||
|
||||
/* primary cpu wakes up all others */
|
||||
if (primary_cpu && NR_OF_CPUS > 1) {
|
||||
primary_cpu = false;
|
||||
board.wake_up_all_cpus(&_start_setup_stack);
|
||||
}
|
||||
|
||||
Cpu::Cpsr::init();
|
||||
cpu.invalidate_data_cache();
|
||||
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
|
||||
}
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* \brief Pbxa9 specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/cortex_a9.h>
|
||||
#include <hw/spec/arm/pl310.h>
|
||||
#include <hw/spec/arm/panda_trustzone_firmware.h>
|
||||
|
||||
#include <spec/arm/cortex_a9_page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
class L2_cache;
|
||||
|
||||
using Serial = Genode::Tl16c750_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::TL16C750_3_MMIO_BASE,
|
||||
UART_CLOCK = Genode::Board_base::TL16C750_CLOCK,
|
||||
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
};
|
||||
|
||||
struct Actlr;
|
||||
}
|
||||
|
||||
|
||||
struct Bootstrap::Actlr
|
||||
{
|
||||
static void enable_smp() {
|
||||
Hw::call_panda_firmware(Hw::CPU_ACTLR_SMP_BIT_RAISE, 0); }
|
||||
};
|
||||
|
||||
|
||||
class Bootstrap::L2_cache : Hw::Pl310
|
||||
{
|
||||
private:
|
||||
|
||||
unsigned long _init_value()
|
||||
{
|
||||
Aux::access_t v = 0;
|
||||
Aux::Associativity::set(v, 1);
|
||||
Aux::Way_size::set(v, 3);
|
||||
Aux::Share_override::set(v, 1);
|
||||
Aux::Reserved::set(v, 1);
|
||||
Aux::Ns_lockdown::set(v, 1);
|
||||
Aux::Ns_irq_ctrl::set(v, 1);
|
||||
Aux::Data_prefetch::set(v, 1);
|
||||
Aux::Inst_prefetch::set(v, 1);
|
||||
Aux::Early_bresp::set(v, 1);
|
||||
return v;
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio) {
|
||||
Hw::call_panda_firmware(Hw::L2_CACHE_AUX_REG, _init_value()); }
|
||||
|
||||
using Hw::Pl310::invalidate;
|
||||
|
||||
void enable()
|
||||
{
|
||||
Hw::call_panda_firmware(Hw::L2_CACHE_ENABLE_REG, 1);
|
||||
Pl310::mask_interrupts();
|
||||
}
|
||||
|
||||
void disable() {
|
||||
Hw::call_panda_firmware(Hw::L2_CACHE_ENABLE_REG, 0); }
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_ */
|
||||
|
|
@ -12,9 +12,8 @@
|
|||
*/
|
||||
|
||||
#include <platform.h>
|
||||
#include <cortex_a9_wugen.h>
|
||||
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
|
||||
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
CORTEX_A9_PRIVATE_MEM_SIZE },
|
||||
|
|
@ -24,28 +23,28 @@ Platform::Board::Board()
|
|||
PL310_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
void Cortex_a9::Board::wake_up_all_cpus(void * const ip)
|
||||
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
|
||||
return false; }
|
||||
|
||||
|
||||
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
|
||||
{
|
||||
Genode::Cortex_a9_wugen wugen;
|
||||
wugen.init_cpu_1(ip);
|
||||
struct Wakeup_generator : Genode::Mmio
|
||||
{
|
||||
struct Aux_core_boot_0 : Register<0x800, 32> {
|
||||
struct Cpu1_status : Bitfield<2, 2> { }; };
|
||||
|
||||
struct Aux_core_boot_1 : Register<0x804, 32> { };
|
||||
|
||||
Wakeup_generator(void * const ip)
|
||||
: Mmio(Genode::Board_base::CORTEX_A9_WUGEN_MMIO_BASE)
|
||||
{
|
||||
write<Aux_core_boot_1>((addr_t)ip);
|
||||
write<Aux_core_boot_0::Cpu1_status>(1);
|
||||
}
|
||||
};
|
||||
|
||||
Wakeup_generator wgen(ip);
|
||||
asm volatile("dsb\n"
|
||||
"sev\n");
|
||||
}
|
||||
|
||||
|
||||
bool Cortex_a9::Board::errata(Cortex_a9::Board::Errata err)
|
||||
{
|
||||
switch (err) {
|
||||
case Cortex_a9::Board::PL310_588369:
|
||||
case Cortex_a9::Board::PL310_727915: return true;
|
||||
default: ;
|
||||
};
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
void Genode::Cpu::Actlr::enable_smp(Genode::Board & board)
|
||||
{
|
||||
Board::Secure_monitor monitor;
|
||||
monitor.call(Board::Secure_monitor::CPU_ACTLR_SMP_BIT_RAISE, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* \brief Pbxa9 specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/cortex_a9.h>
|
||||
#include <hw/spec/arm/pl310.h>
|
||||
|
||||
#include <spec/arm/cortex_a9_actlr.h>
|
||||
#include <spec/arm/cortex_a9_page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
using L2_cache = Hw::Pl310;
|
||||
using Serial = Genode::Pl011_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::PL011_0_MMIO_BASE,
|
||||
UART_CLOCK = Genode::Board_base::PL011_0_CLOCK,
|
||||
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_ */
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
/* bootstrap includes */
|
||||
#include <platform.h>
|
||||
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE },
|
||||
Memory_region { RAM_1_BASE, RAM_1_SIZE }),
|
||||
core_mmio(Memory_region { Board::CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
|
|
@ -25,11 +25,11 @@ Platform::Board::Board()
|
|||
Board::PL310_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
bool Cortex_a9::Board::errata(Cortex_a9::Board::Errata err) {
|
||||
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
|
||||
return false; }
|
||||
|
||||
|
||||
void Cortex_a9::Board::wake_up_all_cpus(void * const ip)
|
||||
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
|
||||
{
|
||||
/**
|
||||
* set the entrypoint for the other CPUs via the flags register
|
||||
|
|
@ -43,7 +43,7 @@ void Cortex_a9::Board::wake_up_all_cpus(void * const ip)
|
|||
struct Flagsclr : Register<0x34, 32> { };
|
||||
|
||||
System_control(void * const ip)
|
||||
: Mmio(SYSTEM_CONTROL_MMIO_BASE)
|
||||
: Mmio(Genode::Board_base::SYSTEM_CONTROL_MMIO_BASE)
|
||||
{
|
||||
write<Flagsclr>(~0UL);
|
||||
write<Flagsset>(reinterpret_cast<Flagsset::access_t>(ip));
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* \brief Riscv spike specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_
|
||||
|
||||
#include <hw/spec/riscv/page_table.h>
|
||||
#include <hw/spec/riscv/uart.h>
|
||||
|
||||
namespace Genode { struct Board_base {}; }
|
||||
|
||||
namespace Bootstrap {
|
||||
struct Cpu {};
|
||||
struct Pic {};
|
||||
|
||||
enum { UART_BASE, UART_CLOCK };
|
||||
struct Serial : Hw::Riscv_uart {
|
||||
Serial(unsigned, unsigned, unsigned) {} };
|
||||
}
|
||||
|
||||
template <typename E, unsigned B, unsigned S>
|
||||
void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t addr,
|
||||
size_t size)
|
||||
{ }
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_ */
|
||||
|
|
@ -12,7 +12,6 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <cpu.h>
|
||||
|
||||
void Genode::Cpu::translation_added(addr_t const addr, size_t const size) {
|
||||
|
|
|
|||
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* \brief Exception vector initialization
|
||||
* \author Sebastian Sumpf
|
||||
* \date 2015-07-12
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* Core includes */
|
||||
#include <kernel/cpu.h>
|
||||
|
||||
extern int _machine_begin, _machine_end;
|
||||
|
||||
extern "C" void setup_riscv_exception_vector()
|
||||
{
|
||||
using namespace Genode;
|
||||
|
||||
/* retrieve exception vector */
|
||||
addr_t vector;
|
||||
asm volatile ("csrr %0, mtvec\n" : "=r"(vector));
|
||||
|
||||
/* copy machine mode exception vector */
|
||||
memcpy((void *)vector,
|
||||
&_machine_begin, (addr_t)&_machine_end - (addr_t)&_machine_begin);
|
||||
}
|
||||
|
|
@ -12,31 +12,30 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <util/string.h>
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
Platform::Board::Board()
|
||||
: early_ram_regions(Genode::Memory_region { 0, 128 * 1024 * 1024 } ) {}
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { 0, 128 * 1024 * 1024 } ) {}
|
||||
|
||||
|
||||
struct Mstatus : Genode::Register<64>
|
||||
void Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
enum {
|
||||
USER = 0,
|
||||
SUPERVISOR = 1,
|
||||
Sv39 = 9,
|
||||
struct Mstatus : Genode::Register<64>
|
||||
{
|
||||
enum {
|
||||
USER = 0,
|
||||
SUPERVISOR = 1,
|
||||
Sv39 = 9,
|
||||
};
|
||||
struct Ie : Bitfield<0, 1> { };
|
||||
struct Priv : Bitfield<1, 2> { };
|
||||
struct Ie1 : Bitfield<3, 1> { };
|
||||
struct Priv1 : Bitfield<4, 2> { };
|
||||
struct Fs : Bitfield<12, 2> { enum { INITIAL = 1 }; };
|
||||
struct Vm : Bitfield<17, 5> { };
|
||||
};
|
||||
struct Ie : Bitfield<0, 1> { };
|
||||
struct Priv : Bitfield<1, 2> { };
|
||||
struct Ie1 : Bitfield<3, 1> { };
|
||||
struct Priv1 : Bitfield<4, 2> { };
|
||||
struct Fs : Bitfield<12, 2> { enum { INITIAL = 1 }; };
|
||||
struct Vm : Bitfield<17, 5> { };
|
||||
};
|
||||
|
||||
|
||||
void Platform::enable_mmu()
|
||||
{
|
||||
using Genode::Cpu;
|
||||
|
||||
/* read status register */
|
||||
Mstatus::access_t mstatus = 0;
|
||||
|
|
@ -57,3 +56,19 @@ void Platform::enable_mmu()
|
|||
"r" (mstatus)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
|
||||
extern int _machine_begin, _machine_end;
|
||||
|
||||
extern "C" void setup_riscv_exception_vector()
|
||||
{
|
||||
using namespace Genode;
|
||||
|
||||
/* retrieve exception vector */
|
||||
addr_t vector;
|
||||
asm volatile ("csrr %0, mtvec\n" : "=r"(vector));
|
||||
|
||||
/* copy machine mode exception vector */
|
||||
memcpy((void *)vector,
|
||||
&_machine_begin, (addr_t)&_machine_end - (addr_t)&_machine_begin);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* \brief Raspberry PI specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/page_table.h>
|
||||
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
using Serial = Genode::Pl011_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::PL011_0_MMIO_BASE,
|
||||
UART_CLOCK = Genode::Board_base::PL011_0_CLOCK,
|
||||
};
|
||||
|
||||
struct Pic {};
|
||||
}
|
||||
|
||||
|
||||
constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() {
|
||||
return 0; }
|
||||
|
||||
|
||||
constexpr bool Hw::Page_table::Descriptor_base::_smp() { return false; }
|
||||
|
||||
|
||||
void Hw::Page_table::_translation_added(unsigned long addr,
|
||||
unsigned long size) {
|
||||
Bootstrap::Cpu::clean_invalidate_data_cache(); }
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_ */
|
||||
|
|
@ -12,15 +12,14 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <hw/assert.h>
|
||||
#include <platform.h>
|
||||
|
||||
using Genode::Memory_region;
|
||||
|
||||
/**
|
||||
* Leave out the first page (being 0x0) from bootstraps RAM allocator,
|
||||
* some code does not feel happy with addresses being zero
|
||||
*/
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
|
||||
RAM_0_SIZE - 0x1000 }),
|
||||
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
|
||||
|
|
@ -34,13 +33,58 @@ Platform::Board::Board()
|
|||
USB_DWC_OTG_SIZE }) {}
|
||||
|
||||
|
||||
void Platform::enable_mmu()
|
||||
void Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
Genode::Cpu::Sctlr::init();
|
||||
Genode::Cpu::Psr::write(Genode::Cpu::Psr::init_kernel());
|
||||
struct Sctlr : Cpu::Sctlr
|
||||
{
|
||||
struct W : Bitfield<3,1> { }; /* enable write buffer */
|
||||
struct Dt : Bitfield<16,1> { }; /* global data TCM enable */
|
||||
struct It : Bitfield<18,1> { }; /* global instruction TCM enable */
|
||||
struct U : Bitfield<22,1> { }; /* enable unaligned data access */
|
||||
struct Xp : Bitfield<23,1> { }; /* disable subpage AP bits */
|
||||
};
|
||||
|
||||
Cpu::Sctlr::init();
|
||||
Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read();
|
||||
Sctlr::W::set(sctlr, 1);
|
||||
Sctlr::Dt::set(sctlr, 1);
|
||||
Sctlr::It::set(sctlr, 1);
|
||||
Sctlr::U::set(sctlr, 1);
|
||||
Sctlr::Xp::set(sctlr, 1);
|
||||
Cpu::Sctlr::write(sctlr);
|
||||
|
||||
Cpu::Cpsr::init();
|
||||
|
||||
struct Ctr : Cpu::Ctr {
|
||||
struct P : Bitfield<23, 1> { }; /* page mapping restriction on */
|
||||
};
|
||||
|
||||
/* check for mapping restrictions */
|
||||
assert(!Genode::Cpu::restricted_page_mappings());
|
||||
assert(!Ctr::P::get(Cpu::Ctr::read()));
|
||||
|
||||
cpu.enable_mmu_and_caches((addr_t)core_pd->table_base);
|
||||
/* invalidate TLB */
|
||||
Cpu::Tlbiall::write(0);
|
||||
|
||||
/* address space ID to zero */
|
||||
Cpu::Cidr::write(0);
|
||||
|
||||
/* do not use domains, but permission bits in table */
|
||||
Cpu::Dacr::write(Cpu::Dacr::D0::bits(1));
|
||||
|
||||
Cpu::Ttbcr::write(0);
|
||||
|
||||
Genode::addr_t table = (Genode::addr_t)core_pd->table_base;
|
||||
Cpu::Ttbr::access_t ttbr0 = Cpu::Ttbr::Ba::masked(table);
|
||||
Cpu::Ttbr::Rgn::set(ttbr0, Cpu::Ttbr::CACHEABLE);
|
||||
Cpu::Ttbr::C::set(ttbr0, 1);
|
||||
Cpu::Ttbr0::write(ttbr0);
|
||||
|
||||
sctlr = Cpu::Sctlr::read();
|
||||
Cpu::Sctlr::C::set(sctlr, 1);
|
||||
Cpu::Sctlr::I::set(sctlr, 1);
|
||||
Cpu::Sctlr::M::set(sctlr, 1);
|
||||
Cpu::Sctlr::write(sctlr);
|
||||
|
||||
/* invalidate branch predictor */
|
||||
Cpu::Bpiall::write(0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* \brief i.MX53 Quickstart board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-03-22
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/imx_tzic.h>
|
||||
|
||||
#include <spec/arm/cortex_a8_page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
using Hw::Pic;
|
||||
using Serial = Genode::Imx_uart_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::UART_1_MMIO_BASE,
|
||||
UART_CLOCK = 0, /* ignored value */
|
||||
};
|
||||
|
||||
bool secure_irq(unsigned irq);
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_ */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* \brief Specific i.MX53 bootstrap implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
#include <spec/imx53/drivers/trustzone.h>
|
||||
#include <spec/arm/imx_aipstz.h>
|
||||
#include <spec/arm/imx_csu.h>
|
||||
|
||||
bool Bootstrap::secure_irq(unsigned i)
|
||||
{
|
||||
using Board = Genode::Board_base;
|
||||
|
||||
if (i == Board::EPIT_1_IRQ) return true;
|
||||
if (i == Board::EPIT_2_IRQ) return true;
|
||||
if (i == Board::SDHC_IRQ) return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { Trustzone::SECURE_RAM_BASE,
|
||||
Trustzone::SECURE_RAM_SIZE }),
|
||||
core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
|
||||
Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
|
||||
Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
|
||||
Memory_region { CSU_BASE, CSU_SIZE })
|
||||
{
|
||||
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
|
||||
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
|
||||
|
||||
/* set exception vector entry */
|
||||
Cpu::Mvbar::write(0xfff00000); //FIXME
|
||||
|
||||
/* enable coprocessor 10 + 11 access for TZ VMs */
|
||||
Cpu::Nsacr::access_t v = 0;
|
||||
Cpu::Nsacr::Cpnsae10::set(v, 1);
|
||||
Cpu::Nsacr::Cpnsae11::set(v, 1);
|
||||
Cpu::Nsacr::write(v);
|
||||
|
||||
/* configure central security unit */
|
||||
Csu csu(Genode::Board_base::CSU_BASE, true, false, true, false);
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* \brief Pbxa9 specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/cortex_a9.h>
|
||||
#include <hw/spec/arm/pl310.h>
|
||||
|
||||
#include <spec/arm/cortex_a9_actlr.h>
|
||||
#include <spec/arm/cortex_a9_page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
using L2_cache = Hw::Pl310;
|
||||
using Serial = Genode::Imx_uart_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::UART_1_MMIO_BASE,
|
||||
UART_CLOCK = 0, /* dummy value, not used */
|
||||
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_ */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* \brief Specific bootstrap implementations
|
||||
* \author Stefan Kalkowski
|
||||
* \author Josef Soentgen
|
||||
* \author Martin Stein
|
||||
* \date 2014-02-25
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2014-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
#include <spec/arm/imx_aipstz.h>
|
||||
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM0_BASE, RAM0_SIZE }),
|
||||
core_mmio(Memory_region { UART_1_MMIO_BASE,
|
||||
UART_1_MMIO_SIZE },
|
||||
Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
CORTEX_A9_PRIVATE_MEM_SIZE },
|
||||
Memory_region { PL310_MMIO_BASE,
|
||||
PL310_MMIO_SIZE })
|
||||
{
|
||||
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
|
||||
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
|
||||
}
|
||||
|
||||
|
||||
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
|
||||
return (err == ARM_764369) ? true : false; }
|
||||
|
||||
|
||||
void Bootstrap::Cpu::wake_up_all_cpus(void * const entry)
|
||||
{
|
||||
struct Src : Genode::Mmio
|
||||
{
|
||||
struct Scr : Register<0x0, 32>
|
||||
{
|
||||
struct Core_1_reset : Bitfield<14,1> {};
|
||||
struct Core_2_reset : Bitfield<15,1> {};
|
||||
struct Core_3_reset : Bitfield<16,1> {};
|
||||
struct Core_1_enable : Bitfield<22,1> {};
|
||||
struct Core_2_enable : Bitfield<23,1> {};
|
||||
struct Core_3_enable : Bitfield<24,1> {};
|
||||
};
|
||||
struct Gpr1 : Register<0x20, 32> {}; /* ep core 0 */
|
||||
struct Gpr3 : Register<0x28, 32> {}; /* ep core 1 */
|
||||
struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
|
||||
struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
|
||||
|
||||
Src(void * const entry)
|
||||
: Genode::Mmio(Genode::Board_base::SRC_MMIO_BASE)
|
||||
{
|
||||
write<Gpr3>((Gpr3::access_t)entry);
|
||||
write<Gpr5>((Gpr5::access_t)entry);
|
||||
write<Gpr7>((Gpr7::access_t)entry);
|
||||
Scr::access_t v = read<Scr>();
|
||||
Scr::Core_1_enable::set(v,1);
|
||||
Scr::Core_1_reset::set(v,1);
|
||||
Scr::Core_2_enable::set(v,1);
|
||||
Scr::Core_2_reset::set(v,1);
|
||||
Scr::Core_3_enable::set(v,1);
|
||||
Scr::Core_3_reset::set(v,1);
|
||||
write<Scr>(v);
|
||||
}
|
||||
};
|
||||
|
||||
Src src(entry);
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* \brief PC specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-04-03
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_
|
||||
|
||||
#include <drivers/uart_base.h>
|
||||
|
||||
#include <hw/spec/x86_64/page_table.h>
|
||||
#include <hw/spec/x86_64/cpu.h>
|
||||
#include <hw/spec/x86_64/x86_64.h>
|
||||
|
||||
namespace Genode { struct Board_base {}; }
|
||||
|
||||
namespace Bootstrap {
|
||||
|
||||
struct Serial;
|
||||
struct Pic {};
|
||||
|
||||
using Cpu = Hw::X86_64_cpu;
|
||||
|
||||
enum Dummies { UART_BASE, UART_CLOCK };
|
||||
}
|
||||
|
||||
|
||||
struct Bootstrap::Serial : Genode::X86_uart_base
|
||||
{
|
||||
Serial(Genode::addr_t, Genode::size_t, unsigned);
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_ */
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
.include "macros.s"
|
||||
.include "hw/spec/x86_64/gdt.s"
|
||||
|
||||
.section ".text.crt0"
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
.include "macros.s"
|
||||
.set MIN_PAGE_SIZE_LOG2, 12
|
||||
|
||||
.data
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
.include "macros.s"
|
||||
.set MIN_PAGE_SIZE_LOG2, 12
|
||||
|
||||
.data
|
||||
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _MULTIBOOT_H_
|
||||
#define _MULTIBOOT_H_
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__X86_64__MULTIBOOT_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__X86_64__MULTIBOOT_H_
|
||||
|
||||
/* base includes */
|
||||
#include <util/mmio.h>
|
||||
|
|
@ -82,4 +82,4 @@ class Genode::Multiboot_info : Mmio
|
|||
}
|
||||
};
|
||||
|
||||
#endif /* _MULTIBOOT_H_ */
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__X86_64__MULTIBOOT_H_ */
|
||||
|
|
@ -14,7 +14,6 @@
|
|||
|
||||
/* core includes */
|
||||
#include <bios_data_area.h>
|
||||
#include <cpu.h>
|
||||
#include <platform.h>
|
||||
#include <multiboot.h>
|
||||
|
||||
|
|
@ -23,12 +22,12 @@ using namespace Genode;
|
|||
/* contains physical pointer to multiboot */
|
||||
extern "C" Genode::addr_t __initial_bx;
|
||||
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: core_mmio(Memory_region { 0, 0x1000 },
|
||||
Memory_region { Board::MMIO_LAPIC_BASE,
|
||||
Board::MMIO_LAPIC_SIZE },
|
||||
Memory_region { Board::MMIO_IOAPIC_BASE,
|
||||
Board::MMIO_IOAPIC_SIZE },
|
||||
Memory_region { Hw::Cpu_memory_map::MMIO_LAPIC_BASE,
|
||||
Hw::Cpu_memory_map::MMIO_LAPIC_SIZE },
|
||||
Memory_region { Hw::Cpu_memory_map::MMIO_IOAPIC_BASE,
|
||||
Hw::Cpu_memory_map::MMIO_IOAPIC_SIZE },
|
||||
Memory_region { __initial_bx & ~0xFFFUL,
|
||||
get_page_size() })
|
||||
{
|
||||
|
|
@ -68,8 +67,12 @@ Platform::Board::Board()
|
|||
}
|
||||
|
||||
|
||||
void Platform::enable_mmu() {
|
||||
Cpu::Cr3::write(Cpu::Cr3::init((addr_t)core_pd->table_base)); }
|
||||
void Bootstrap::Platform::enable_mmu() {
|
||||
Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base)); }
|
||||
|
||||
|
||||
addr_t Bios_data_area::_mmio_base_virt() { return 0x1ff000; }
|
||||
|
||||
|
||||
Bootstrap::Serial::Serial(addr_t, size_t, unsigned baudrate)
|
||||
:X86_uart_base(Bios_data_area::singleton()->serial_port(), 0, baudrate) {}
|
||||
|
|
|
|||
|
|
@ -12,15 +12,22 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <cpu.h>
|
||||
#include <platform.h>
|
||||
#include <muen/sinfo.h>
|
||||
|
||||
using namespace Genode;
|
||||
using Sinfo = Genode::Sinfo;
|
||||
|
||||
enum {
|
||||
TIMER_BASE_ADDR = 0xe00010000,
|
||||
TIMER_SIZE = 0x1000,
|
||||
TIMER_PREEMPT_BASE_ADDR = 0xe00011000,
|
||||
TIMER_PREEMPT_SIZE = 0x1000,
|
||||
|
||||
COM1_PORT = 0x3f8,
|
||||
};
|
||||
|
||||
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: core_mmio(Memory_region { Sinfo::PHYSICAL_BASE_ADDR, Sinfo::SIZE },
|
||||
Memory_region { TIMER_BASE_ADDR, TIMER_SIZE },
|
||||
Memory_region { TIMER_PREEMPT_BASE_ADDR, TIMER_PREEMPT_SIZE })
|
||||
|
|
@ -29,11 +36,15 @@ Platform::Board::Board()
|
|||
|
||||
Sinfo sinfo(Sinfo::PHYSICAL_BASE_ADDR);
|
||||
if (!sinfo.get_memregion_info("ram", ®ion))
|
||||
error("Unable to retrieve base-hw ram region");
|
||||
Genode::error("Unable to retrieve base-hw ram region");
|
||||
else
|
||||
early_ram_regions.add(Memory_region { region.address, region.size });
|
||||
}
|
||||
|
||||
|
||||
void Platform::enable_mmu() {
|
||||
Cpu::Cr3::write(Cpu::Cr3::init((addr_t)core_pd->table_base)); }
|
||||
void Bootstrap::Platform::enable_mmu() {
|
||||
Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base)); }
|
||||
|
||||
|
||||
Bootstrap::Serial::Serial(addr_t, size_t, unsigned baudrate)
|
||||
:X86_uart_base(COM1_PORT, 0, baudrate) {}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* \brief Zynq specific board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2017-02-20
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_
|
||||
|
||||
#include <drivers/board_base.h>
|
||||
#include <drivers/uart_base.h>
|
||||
#include <hw/spec/arm/cortex_a9.h>
|
||||
#include <hw/spec/arm/pl310.h>
|
||||
|
||||
#include <spec/arm/cortex_a9_actlr.h>
|
||||
#include <spec/arm/cortex_a9_page_table.h>
|
||||
#include <spec/arm/cpu.h>
|
||||
#include <spec/arm/pic.h>
|
||||
|
||||
namespace Bootstrap {
|
||||
using L2_cache = Hw::Pl310;
|
||||
using Serial = Genode::Xilinx_uartps_base;
|
||||
|
||||
enum {
|
||||
UART_BASE = Genode::Board_base::UART_0_MMIO_BASE,
|
||||
UART_CLOCK = Genode::Board_base::UART_CLOCK,
|
||||
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_ */
|
||||
|
|
@ -15,18 +15,17 @@
|
|||
/* core includes */
|
||||
#include <platform.h>
|
||||
|
||||
|
||||
Platform::Board::Board()
|
||||
Bootstrap::Platform::Board::Board()
|
||||
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
|
||||
RAM_0_SIZE - 0x1000 }),
|
||||
late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
|
||||
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
|
||||
CORTEX_A9_PRIVATE_MEM_SIZE },
|
||||
Memory_region { KERNEL_UART_BASE,
|
||||
KERNEL_UART_SIZE },
|
||||
Memory_region { UART_0_MMIO_BASE,
|
||||
UART_SIZE },
|
||||
Memory_region { PL310_MMIO_BASE,
|
||||
PL310_MMIO_SIZE }) { }
|
||||
|
||||
|
||||
bool Cortex_a9::Board::errata(Cortex_a9::Board::Errata err) {
|
||||
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
|
||||
return false; }
|
||||
|
|
|
|||
|
|
@ -11,11 +11,8 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* base includes */
|
||||
#include <base/thread.h>
|
||||
|
||||
/* local includes */
|
||||
#include <assert.h>
|
||||
#include <hw/assert.h>
|
||||
|
||||
|
||||
Genode::Thread * Genode::Thread::myself()
|
||||
|
|
|
|||
|
|
@ -57,6 +57,8 @@ Core_region_map::attach(Dataspace_capability ds_cap, size_t size,
|
|||
return nullptr;
|
||||
}
|
||||
|
||||
using namespace Hw;
|
||||
|
||||
/* map the dataspace's physical pages to corresponding virtual addresses */
|
||||
unsigned num_pages = page_rounded_size >> get_page_size_log2();
|
||||
Page_flags const flags { ds->writable() ? RW : RO, NO_EXEC, USER,
|
||||
|
|
|
|||
|
|
@ -11,11 +11,8 @@
|
|||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* Genode includes */
|
||||
#include <assert.h>
|
||||
|
||||
/* base-internal includes */
|
||||
#include <base/internal/native_env.h>
|
||||
#include <assertion.h>
|
||||
|
||||
|
||||
void Genode::upgrade_pd_quota_non_blocking(Genode::size_t quota) { assert(false); }
|
||||
void Genode::upgrade_pd_quota_non_blocking(Genode::size_t quota) {
|
||||
ASSERT_NEVER_CALLED; }
|
||||
|
|
|
|||
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* \brief Boot information
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2016-10-26
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _BOOTINFO_H_
|
||||
#define _BOOTINFO_H_
|
||||
|
||||
#include <core_mmio.h>
|
||||
#include <translation_table.h>
|
||||
#include <translation_table_allocator_tpl.h>
|
||||
|
||||
namespace Genode { struct Bootinfo; }
|
||||
|
||||
struct Genode::Bootinfo
|
||||
{
|
||||
using Table = Translation_table;
|
||||
static constexpr size_t COUNT = Table::CORE_TRANS_TABLE_COUNT;
|
||||
using Table_allocator = Translation_table_allocator_tpl<COUNT>;
|
||||
using Mapping_pool = Array<Mapping, 32>;
|
||||
|
||||
Table * const table;
|
||||
Table_allocator * const table_allocator;
|
||||
Mapping_pool const elf_mappings;
|
||||
Core_mmio const core_mmio;
|
||||
Memory_region_array ram_regions;
|
||||
|
||||
Bootinfo(Table * const table,
|
||||
Table_allocator * const table_alloc,
|
||||
Mapping_pool const elf_mappings,
|
||||
Core_mmio const core_mmio)
|
||||
: table(table), table_allocator(table_alloc),
|
||||
elf_mappings(elf_mappings), core_mmio(core_mmio) {}
|
||||
};
|
||||
|
||||
#endif /* _BOOTINFO_H_ */
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
#include <kernel/cpu_scheduler.h>
|
||||
#include <kernel/irq.h>
|
||||
|
||||
namespace Genode { class Translation_table; }
|
||||
namespace Hw { class Page_table; }
|
||||
|
||||
namespace Kernel
|
||||
{
|
||||
|
|
@ -80,7 +80,7 @@ class Kernel::Cpu_context : public Genode::Cpu::Context
|
|||
*
|
||||
* \param table mode-transition table
|
||||
*/
|
||||
Cpu_context(Genode::Translation_table * const table);
|
||||
Cpu_context(Hw::Page_table * const table);
|
||||
};
|
||||
|
||||
class Kernel::Cpu_domain_update : public Double_list_item
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue