86 lines
2.4 KiB
C++
86 lines
2.4 KiB
C++
/*
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* \brief Driver for Freescale's AIPSTZ bridge
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* \author Stefan Kalkowski
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* \author Martin Stein
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_
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#define _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_
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#include <util/mmio.h>
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namespace Bootstrap
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{
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/**
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* AHB to IP Bridge
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*
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* Interface between the system bus and lower bandwidth IP Slave (IPS)
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* bus peripherals.
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*/
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class Aipstz;
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}
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class Bootstrap::Aipstz : public Genode::Mmio
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{
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private:
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/*
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* Configuration of the masters
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*/
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struct Mpr { enum { ALL_UNBUFFERED_AND_FULLY_TRUSTED = 0x77777777 }; };
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struct Mpr1 : Register<0x0, 32>, Mpr { };
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struct Mpr2 : Register<0x4, 32>, Mpr { };
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/*
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* Configuration of the platform peripherals
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*/
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struct Pacr { enum { ALL_UNBUFFERED_AND_FULLY_UNPROTECTED = 0 }; };
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struct Pacr1 : Register<0x20, 32>, Pacr { };
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struct Pacr2 : Register<0x24, 32>, Pacr { };
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struct Pacr3 : Register<0x28, 32>, Pacr { };
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struct Pacr4 : Register<0x2c, 32>, Pacr { };
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/*
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* Configuration of the off-platform peripherals
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*/
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struct Opacr1 : Register<0x40, 32>, Pacr { };
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struct Opacr2 : Register<0x44, 32>, Pacr { };
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struct Opacr3 : Register<0x48, 32>, Pacr { };
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struct Opacr4 : Register<0x4c, 32>, Pacr { };
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struct Opacr5 : Register<0x50, 32>, Pacr { };
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public:
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/**
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* Configure this module appropriately for the first kernel run
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*/
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Aipstz(Genode::addr_t const base) : Genode::Mmio(base)
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{
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/* avoid AIPS intervention at any memory access */
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write<Mpr1>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
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write<Mpr2>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
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write<Pacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Pacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Pacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Pacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Opacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Opacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Opacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Opacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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write<Opacr5>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
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}
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};
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#endif /* _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_ */
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