parent
0e208c3d3d
commit
58c4f1585b
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@ -213,7 +213,7 @@ extern "C" void init_kernel_multiprocessor()
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/* synchronize data view of all processors */
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/* synchronize data view of all processors */
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Processor::invalidate_data_caches();
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Processor::invalidate_data_caches();
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Processor::invalidate_instruction_caches();
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Processor::invalidate_instr_caches();
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Processor::invalidate_control_flow_predictions();
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Processor::invalidate_control_flow_predictions();
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Processor::data_synchronization_barrier();
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Processor::data_synchronization_barrier();
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@ -543,6 +543,19 @@ void Thread::_call_update_pd()
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void Thread::_call_update_data_region()
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void Thread::_call_update_data_region()
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{
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{
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/*
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* FIXME: If the caller is not a core thread, the kernel operates in a
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* different address space than the caller. Combined with the fact
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* that at least ARMv7 doesn't provide cache operations by physical
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* address, this prevents us from selectively maintaining caches.
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* The future solution will be a kernel that is mapped to every
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* address space so we can use virtual addresses of the caller. Up
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* until then we apply operations to caches as a whole instead.
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*/
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if (!_core()) {
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Processor::flush_data_caches();
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return;
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}
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auto base = (addr_t)user_arg_1();
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auto base = (addr_t)user_arg_1();
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auto const size = (size_t)user_arg_2();
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auto const size = (size_t)user_arg_2();
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Processor::flush_data_caches_by_virt_region(base, size);
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Processor::flush_data_caches_by_virt_region(base, size);
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@ -551,6 +564,20 @@ void Thread::_call_update_data_region()
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void Thread::_call_update_instr_region()
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void Thread::_call_update_instr_region()
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{
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{
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/*
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* FIXME: If the caller is not a core thread, the kernel operates in a
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* different address space than the caller. Combined with the fact
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* that at least ARMv7 doesn't provide cache operations by physical
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* address, this prevents us from selectively maintaining caches.
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* The future solution will be a kernel that is mapped to every
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* address space so we can use virtual addresses of the caller. Up
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* until then we apply operations to caches as a whole instead.
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*/
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if (!_core()) {
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Processor::flush_data_caches();
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Processor::invalidate_instr_caches();
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return;
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}
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auto base = (addr_t)user_arg_1();
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auto base = (addr_t)user_arg_1();
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auto const size = (size_t)user_arg_2();
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auto const size = (size_t)user_arg_2();
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Processor::flush_data_caches_by_virt_region(base, size);
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Processor::flush_data_caches_by_virt_region(base, size);
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@ -625,7 +625,7 @@ namespace Arm
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* Invalidate all entries of all instruction caches
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* Invalidate all entries of all instruction caches
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*/
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*/
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__attribute__((always_inline))
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__attribute__((always_inline))
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static void invalidate_instruction_caches()
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static void invalidate_instr_caches()
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{
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{
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asm volatile ("mcr p15, 0, %[rd], c7, c5, 0" :: [rd]"r"(0) : );
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asm volatile ("mcr p15, 0, %[rd], c7, c5, 0" :: [rd]"r"(0) : );
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}
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}
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@ -646,7 +646,7 @@ namespace Arm
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static void flush_caches()
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static void flush_caches()
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{
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{
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flush_data_caches();
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flush_data_caches();
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invalidate_instruction_caches();
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invalidate_instr_caches();
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}
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}
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/**
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/**
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