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hw: fix gicv3 implementation of clear/set regs 

In addition use uniformly enums for interupt count in register declarations.

Fix #3532
This commit is contained in:
Stefan Kalkowski 2019-09-23 09:45:29 +02:00 committed by Christian Helmuth
parent f6435d91fc
commit 105b2c9b7a
1 changed files with 9 additions and 9 deletions
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18
repos/base-hw/src/include/hw/spec/arm/gicv3.h
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@ -60,35 +60,35 @@ class Hw::Pic
struct Typer : Register<0x004, 32> { struct Typer : Register<0x004, 32> {
struct It_lines_number : Bitfield<0,5> { }; }; struct It_lines_number : Bitfield<0,5> { }; };
struct Igroup0r : Register_array<0x80, 32, 32*32, 1> { struct Igroup0r : Register_array<0x80, 32, nr_of_irq, 1> {
struct Group1 : Bitfield<0, 1> { }; }; struct Group1 : Bitfield<0, 1> { }; };
/** /**
* Interrupt Set-Enable register * Interrupt Set-Enable register
*/ */
struct Isenabler : Register_array<0x100, 32, 32*32, 1, true> { struct Isenabler : Register_array<0x100, 32, nr_of_irq, 1, true> {
struct Set_enable : Bitfield<0, 1> { }; }; struct Set_enable : Bitfield<0, 1> { }; };
/** /**
* Interrupt clear enable registers * Interrupt clear enable registers
*/ */
struct Icenabler : Register_array<0x180, 32, 32*32, 1, true> { struct Icenabler : Register_array<0x180, 32, nr_of_irq, 1, true> {
struct Clear_enable : Bitfield<0, 1> { }; }; struct Clear_enable : Bitfield<0, 1> { }; };
/** /**
* Interrupt clear pending registers * Interrupt clear pending registers
*/ */
struct Icpendr : Register_array<0x280, 32, 32*32, 1, true> { struct Icpendr : Register_array<0x280, 32, nr_of_irq, 1, true> {
struct Clear_pending : Bitfield<0, 1> { }; }; struct Clear_pending : Bitfield<0, 1> { }; };
/** /**
* Interrupt priority level registers * Interrupt priority level registers
*/ */
struct Ipriorityr : Register_array<0x400, 32, 255*4, 8> { struct Ipriorityr : Register_array<0x400, 32, nr_of_irq, 8> {
struct Priority : Bitfield<0, 8> { }; }; struct Priority : Bitfield<0, 8> { }; };
struct Icfgr : Register_array<0xc00, 32, 64*16, 2> { struct Icfgr : Register_array<0xc00, 32, nr_of_irq, 2> {
struct Edge_triggered : Bitfield<1, 1> { }; }; struct Edge_triggered : Bitfield<1, 1> { }; };
struct Irouter : Register_array<0x6000, 64, 1020, 64, true> { }; struct Irouter : Register_array<0x6000, 64, 1020, 64, true> { };
@ -132,13 +132,13 @@ class Hw::Pic
{ {
struct Igroupr0 : Register<0x80, 32> { }; struct Igroupr0 : Register<0x80, 32> { };
struct Isenabler0 : Register_array<0x100, 32, 32, 1> struct Isenabler0 : Register_array<0x100, 32, min_spi, 1, true>
{ }; { };
struct Icenabler0 : Register_array<0x180, 32, 32, 1> struct Icenabler0 : Register_array<0x180, 32, min_spi, 1, true>
{ }; { };
struct Icactiver0 : Register<0x380, 32> { }; struct Icactiver0 : Register<0x380, 32, true> { };
struct Ipriorityr : Register_array<0x400, 32, min_spi, 8> { struct Ipriorityr : Register_array<0x400, 32, min_spi, 8> {
struct Priority : Bitfield<0, 8> { }; }; struct Priority : Bitfield<0, 8> { }; };