2013-01-25 16:56:39 +01:00
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/*
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* \brief Programmable interrupt controller for core
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* \author Martin stein
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2015-02-09 11:36:38 +01:00
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* \author Stefan Kalkowski
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2013-01-25 16:56:39 +01:00
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* \date 2011-10-26
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*/
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/*
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2017-02-20 13:23:52 +01:00
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* Copyright (C) 2011-2017 Genode Labs GmbH
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2013-01-25 16:56:39 +01:00
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*
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* This file is part of the Genode OS framework, which is distributed
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2017-02-20 13:23:52 +01:00
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* under the terms of the GNU Affero General Public License version 3.
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2013-01-25 16:56:39 +01:00
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*/
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2017-04-12 10:06:29 +02:00
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#ifndef _CORE__SPEC__ARM_GIC__PIC_H_
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#define _CORE__SPEC__ARM_GIC__PIC_H_
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2013-01-25 16:56:39 +01:00
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2017-02-21 13:46:59 +01:00
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#include <hw/spec/arm/pic.h>
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2013-12-17 18:10:02 +01:00
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2017-02-21 13:46:59 +01:00
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namespace Genode { class Pic; }
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2015-02-09 11:36:38 +01:00
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namespace Kernel { using Pic = Genode::Pic; }
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2017-02-21 13:46:59 +01:00
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class Genode::Pic : public Hw::Pic
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2014-07-15 14:51:27 +02:00
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{
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2015-02-18 14:23:54 +01:00
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public:
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enum { IPI = 1 };
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2014-03-10 15:37:20 +01:00
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/**
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2014-08-08 14:38:27 +02:00
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* Raise inter-processor IRQ of the CPU with kernel name 'cpu_id'
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2014-03-10 15:37:20 +01:00
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*/
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2016-01-11 11:02:52 +01:00
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void send_ipi(unsigned const cpu_id)
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2014-03-10 15:37:20 +01:00
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{
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2017-02-21 13:46:59 +01:00
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using Sgir = Distributor::Sgir;
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2014-03-10 15:37:20 +01:00
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Sgir::access_t sgir = 0;
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2015-02-18 14:23:54 +01:00
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Sgir::Sgi_int_id::set(sgir, IPI);
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2014-08-08 14:38:27 +02:00
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Sgir::Cpu_target_list::set(sgir, 1 << cpu_id);
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2014-03-10 15:37:20 +01:00
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_distr.write<Sgir>(sgir);
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}
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2016-01-11 11:02:52 +01:00
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/**
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* Raise inter-processor interrupt on all other cores
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*/
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void send_ipi()
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{
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2017-02-21 13:46:59 +01:00
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using Sgir = Distributor::Sgir;
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2016-01-11 11:02:52 +01:00
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Sgir::access_t sgir = 0;
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Sgir::Sgi_int_id::set(sgir, IPI);
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Sgir::Target_list_filter::set(sgir,
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Sgir::Target_list_filter::ALL_OTHER);
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_distr.write<Sgir>(sgir);
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}
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2017-10-06 12:02:36 +02:00
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static constexpr bool fast_interrupts() { return false; }
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2013-12-17 18:10:02 +01:00
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};
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2013-01-25 16:56:39 +01:00
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2017-04-12 10:06:29 +02:00
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#endif /* _CORE__SPEC__ARM_GIC__PIC_H_ */
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