No Description

Trinamic_TMC2130_registers.h 12KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319
  1. /**************************************************************************/
  2. /*!
  3. @file Trinamic_TMC2130_registers.h
  4. @author Moritz Walter
  5. @license GPLv3 (see license.txt)
  6. SPI configuration tool for Trinamic TMC2130 Motor Drivers
  7. @section HISTORY
  8. v0.1 - it works
  9. */
  10. /**************************************************************************/
  11. #ifndef TRINAMIC_TMC2130_REGISTERS_H
  12. #define TRINAMIC_TMC2130_REGISTERS_H
  13. #if ARDUINO >= 100
  14. #include "Arduino.h"
  15. #else
  16. #include "WProgram.h"
  17. #endif
  18. #include <SPI.h>
  19. // SPI
  20. #define TMC_SPI_CLOCK_DIVIDER SPI_CLOCK_DIV8
  21. #define TMC_SPI_DATA_MODE SPI_MODE3
  22. #define TMC_SPI_BIT_ORDER MSBFIRST
  23. // RW
  24. #define TMC_READ (0x00)
  25. #define TMC_WRITE (0x80)
  26. // SPISTATUS MASKS
  27. #define TMC_SPISTATUS_RESET_MASK (0x01)
  28. #define TMC_SPISTATUS_ERROR_MASK (0x02)
  29. #define TMC_SPISTATUS_STALLGUARD_MASK (0x04)
  30. #define TMC_SPISTATUS_STANDSTILL_MASK (0x08)
  31. // REGISTERS
  32. #define TMC_REG_GCONF (0x00) // RW // 17 // Global configuration flags
  33. #define TMC_REG_GSTAT (0x01) // RC // 3 // Global status flags
  34. #define TMC_REG_IOIN (0x04) // R // 8+8 // Reads the state of all input pins available
  35. #define TMC_REG_IHOLD_IRUN (0x10) // W // 5+5+4 // Driver current control
  36. #define TMC_REG_TPOWERDOWN (0x11) // W // 8 // sets delay time after stand still (stst) to motor current power down (0-4 seconds) 0_((2^8)-1) * 2^18 tclk
  37. #define TMC_REG_TSTEP (0x12) // R // 20 // Actual measured time between two 1/256 microsteps derived from the step input frequency in units of 1/fCLK. Measured value is (2^20)-1 in case of overflow or stand still
  38. #define TMC_REG_TPWMTHRS (0x13) // W // 20 // Upper velocity threshold for stealthChop voltage PWM mode
  39. #define TMC_REG_TCOOLTHRS (0x14) // W // 20 // Lower threshold velocity for switching on smart energy coolStep and stallGuard feature (unsigned)
  40. #define TMC_REG_THIGH (0x15) // W // 20 // Velocity dependend switching into different chopper mode and fullstepping to maximize torque (unsigned)
  41. #define TMC_REG_XDIRECT (0x2D) // RW // 32 // specifies motor coil currents and polarity directly programmed via SPI. Use signed, two's complement numbers. In this mode, the current is scaled by IHOLD. Velocity based current regulation of voltage PWM is not available in this mode. +- 255 for both coils
  42. #define TMC_REG_VDCMIN (0x33) // W // 23 // automatic commutation dcStep becomes enabled by the external signal DCEN. VDCMIN is used as the minimum step velocity when the motor is heavily loaded. Hint: Also set DCCTRL parameters in order to operate dcStep
  43. #define TMC_REG_MSLUT0 (0x60) // W // 32 // Each bit gives the difference between entry x and entry x+1 when combined with the corresponding MSLUTSEL W bits. Differential coding for the first quarter of a wave. Start values for CUR_A and CUR_B are stored for MSCNT position 0 in START_SIN and START_SIN90.
  44. #define TMC_REG_MSLUT1 (0x61) // W // 32 //
  45. #define TMC_REG_MSLUT2 (0x62) // W // 32 //
  46. #define TMC_REG_MSLUT3 (0x63) // W // 32 //
  47. #define TMC_REG_MSLUT4 (0x64) // W // 32 //
  48. #define TMC_REG_MSLUT5 (0x65) // W // 32 //
  49. #define TMC_REG_MSLUT6 (0x66) // W // 32 //
  50. #define TMC_REG_MSLUT7 (0x67) // W // 32 //
  51. #define TMC_REG_MSLUTSEL (0x68) // W // 32 // defines four segments within each quarter MSLUT wave. Four 2 bit entries determine the meaning of a 0 and a 1 bit in the corresponding segment of MSLUT
  52. #define TMC_REG_MSLUTSTART (0x69) // W // 8+8 //
  53. #define TMC_REG_MSCNT (0x6A) // R // 10 //
  54. #define TMC_REG_MSCURACT (0x6B) // R // 9+9 //
  55. #define TMC_REG_CHOPCONF (0x6C) // RW // 32 //
  56. #define TMC_REG_COOLCONF (0x6D) // W // 25 //
  57. #define TMC_REG_DCCTRL (0x6E) // W // 24 //
  58. #define TMC_REG_DRV_STATUS (0x6F) // R // 22 //
  59. #define TMC_REG_PWMCONF (0x70) // W // 8 //
  60. #define TMC_REG_PWM_SCALE (0x71) // R // 8 //
  61. #define TMC_REG_ENCM_CTRL (0x72) // W // 2 //
  62. #define TMC_REG_LOST_STEPS (0x73) // R // 20 //
  63. // GCONF OFFSETS
  64. // for shifting incoming values to the right register position
  65. #define TMC_GCONF_I_SCALE_ANALOG (0) // 0: Internal, 1: AIN
  66. #define TMC_GCONF_INTERNAL_RSENSE (1) // 0: Normal, 1: Internal
  67. #define TMC_GCONF_EN_PWM_MODE (2) // 0: Disable, 1: Enable
  68. #define TMC_GCONF_ENC_COMMUTATION (3) // 0: Disable, 1: Enable
  69. #define TMC_GCONF_SHAFT (4) // 0: Normal, 1: Invert
  70. #define TMC_GCONF_DIAG0_ERROR (5) // 0: Disable, 1: Enable
  71. #define TMC_GCONF_DIAG0_OTPW (6) // 0: Disable, 1: Enable
  72. #define TMC_GCONF_DIAG0_STALL (7) // 0: Disable, 1: Enable
  73. #define TMC_GCONF_DIAG1_STALL (8) // 0: Disable, 1: Enable
  74. #define TMC_GCONF_DIAG1_INDEX (9) // 0: Disable, 1: Enable
  75. #define TMC_GCONF_DIAG1_ONSTATE (10) // 0: Disable, 1: Enable
  76. #define TMC_GCONF_DIAG1_STEPS_SKIPPED (11) // 0: Disable, 1: Enable
  77. #define TMC_GCONF_DIAG0_INT_PUSHPULL (12) // 0: Open Collector, 1: Push Pull
  78. #define TMC_GCONF_DIAG1_INT_PUSHPULL (13) // 0: Open Collector, 1: Push Pull
  79. #define TMC_GCONF_SMALL_HYSTERESIS (14) // 0: 1/16, 1: 1/32
  80. #define TMC_GCONF_STOP_ENABLE (15) // 0: Normal, 1: Emergency Stop
  81. #define TMC_GCONF_DIRECT_MODE (16) // 0: Normal, 1: XDIRECT
  82. #define TMC_GCONF_TEST_MODE (17) // 0: Normal, 1: Enable, Don't use!
  83. // GCONF MASKS
  84. // not required, all 1 bit
  85. // IHOLD_IRUN OFFSETS
  86. // for shifting incoming values to the right register position
  87. #define TMC_IHOLD (0)
  88. #define TMC_IRUN (8)
  89. #define TMC_IHOLDDELAY (16)
  90. // IHOLD IRUN MASKS
  91. #define TMC_IHOLD_MASK (0b11111UL)
  92. #define TMC_IRUN_MASK (0b11111UL)
  93. #define TMC_IHOLDDELAY_MASK (0b1111UL)
  94. // TPOWERDOWN
  95. // no offsets required
  96. #define TMC_TPOWERDOWN_MASK (0b11111111UL)
  97. // TSTEP
  98. // no offsets required
  99. #define TMC_TSTEP_MASK (0b11111111111111111111UL)
  100. // TPWMTHRS
  101. // no offsets required
  102. #define TMC_TPWMTHRS_MASK (0b11111111111111111111UL)
  103. // TCOOLTHRS
  104. #define TMC_TCOOLTHRS_MASK (0b11111111111111111111UL)
  105. // THIGH
  106. // no offsets required
  107. #define TMC_THIGH_MASK (0b11111111111111111111UL)
  108. // XDIRECT OFFSETS
  109. // for shifting incoming values to the right register position
  110. #define TMC_XDIRECT_COIL_A (0)
  111. #define TMC_XDIRECT_COIL_B (16)
  112. // XDIRECT MASKS
  113. // mask the bits from the values we want to set
  114. #define TMC_XDIRECT_MASK (0xFFFFFFFFUL)
  115. #define TMC_XDIRECT_COIL_A_MASK (0xFFFFUL)
  116. #define TMC_XDIRECT_COIL_B_MASK (0xFFFFUL)
  117. // no offsets required
  118. // needs no mask
  119. // VDCMIN
  120. // no offsets required
  121. #define TMC_VDCMIN_MASK (0b11111111111111111111111UL)
  122. // MSLUT
  123. // no offsets required
  124. // needs no mask
  125. // MSLUTSEL
  126. // no offsets required
  127. // needs no mask
  128. // MSLUTSTART OFFSETS
  129. #define TMC_MSLUTSTART_START_SIN (0)
  130. #define TMC_MSLUTSTART_START_SIN90 (8)
  131. // MSLUTSTART MASKS
  132. #define TMC_MSLUTSTART_MASK (0xFFFFUL)
  133. #define TMC_MSLUTSTART_START_SIN_MASK (0xFF)
  134. #define TMC_MSLUTSTART_START_SIN90_MASK (0xFF)
  135. // MSCNT
  136. // no offsets required
  137. #define TMC_MSCNT_MASK (0b1111111111)
  138. // MSCURACT
  139. // no offsets required
  140. #define TMC_MSCURACT_MASK (0b111111111111111111UL)
  141. // CHOPCONF MASKS
  142. // mask the bits from the values we want to set
  143. const uint32_t TMC_CHOPCONF_MASKS[] = {
  144. 0b1111UL, // 0 TOFF
  145. 0b111UL, // 1
  146. 0b11UL, // 2
  147. 0b1UL, // 3
  148. 0b111UL, // 4 HYSTERESIS_START
  149. 0b11UL, // 5
  150. 0b1UL, // 6
  151. 0b0001UL, // 7 HYSTERESIS_LOW
  152. 0b001UL, // 8
  153. 0b01UL, // 9
  154. 0b1UL, // 10
  155. 0b1UL, // 11 FAST_DECAY_TIMING
  156. 0b1UL, // 12 FAST_DECAY_MODE
  157. 0b1UL, // 13 RANDOM_TOFF
  158. 0b1UL, // 14 CHOPPER_MODE
  159. 0b11UL, // 15 TBL
  160. 0b1UL, // 16
  161. 0b1UL, // 17 SENSE_CURRENT_SCALING
  162. 0b1UL, // 18 HIGH_VELOCITY_STEPS
  163. 0b1UL, // 19 HIGH_VELOCITY_CHOPPER
  164. 0b1111UL, // 20 SYNC_PWM
  165. 0b111UL, // 21
  166. 0b11UL, // 22
  167. 0b1UL, // 23
  168. 0b1111UL, // 24 MRES
  169. 0b111UL, // 25
  170. 0b11UL, // 26
  171. 0b1UL, // 27
  172. 0b1UL, // 28 INTERPOLATE
  173. 0b1UL, // 29 DOUBLE_EDGE_PULSES
  174. 0b1UL, // 30 SHORT_PROTECTION
  175. 0b1UL // 31
  176. };
  177. // CHOPCONF OFFSETS
  178. // for shifting incoming values to the right register position
  179. #define TMC_CHOPCONF_DISS2G (30)
  180. #define TMC_CHOPCONF_DEDGE (29)
  181. #define TMC_CHOPCONF_INTPOL (28)
  182. #define TMC_CHOPCONF_MRES (24)
  183. #define TMC_CHOPCONF_SYNC (20)
  184. #define TMC_CHOPCONF_VHIGHCHM (19)
  185. #define TMC_CHOPCONF_VHIGHFS (18)
  186. #define TMC_CHOPCONF_VSENSE (17)
  187. #define TMC_CHOPCONF_TBL (15)
  188. #define TMC_CHOPCONF_CHM (14)
  189. #define TMC_CHOPCONF_RNDTF (13)
  190. #define TMC_CHOPCONF_DISFDCC (12)
  191. #define TMC_CHOPCONF_FD (11)
  192. #define TMC_CHOPCONF_HEND (7)
  193. #define TMC_CHOPCONF_HSTRT (4)
  194. #define TMC_CHOPCONF_TOFF (0)
  195. // COOLCONF BIT OFFSETS
  196. // for shifting incoming values to the right register position
  197. #define TMC_COOLCONF_SFILT (24)
  198. #define TMC_COOLCONF_SGT (16)
  199. #define TMC_COOLCONF_SEIMIN (15)
  200. #define TMC_COOLCONF_SEDN (13)
  201. #define TMC_COOLCONF_SEMAX (8)
  202. #define TMC_COOLCONF_SEUP (5)
  203. #define TMC_COOLCONF_SEMIN (0)
  204. // COOLCONF MASKS
  205. // mask the bits from the values we want to set
  206. const int TMC_COOLCONF_MASKS[] = {
  207. 0b1111UL, // 0 TMC_COOLCONF_SEMIN
  208. 0b111UL, // 1
  209. 0b11UL, // 2
  210. 0b1UL, // 3
  211. 0b0UL, // 4
  212. 0b11UL, // 5 TMC_COOLCONF_SEUP
  213. 0b1UL, // 6
  214. 0b0UL, // 7
  215. 0b1111UL, // 8 TMC_COOLCONF_SEMAX
  216. 0b111UL, // 9
  217. 0b11UL, // 10
  218. 0b1UL, // 11
  219. 0b0UL, // 12
  220. 0b11UL, // 13 TMC_COOLCONF_SEDN
  221. 0b1UL, // 14
  222. 0b1UL, // 15 TMC_COOLCONF_SEIMIN
  223. 0b1111111UL, // 16 TMC_COOLCONF_SGT
  224. 0b111111UL, // 17
  225. 0b11111UL, // 18
  226. 0b1111UL, // 19
  227. 0b111UL, // 20
  228. 0b11UL, // 21
  229. 0b1UL, // 22
  230. 0b0UL, // 23
  231. 0b1UL, // 24 TMC_COOLCONF_SFILT
  232. };
  233. // DCCTRL OFFSETS
  234. // for shifting incoming values to the right register position
  235. #define TMC_DCCTRL_DC_TIME (0)
  236. #define TMC_DCCTRL_DC_SG (16)
  237. // DCCTRL MASKS
  238. // mask the bits from the values we want to set
  239. #define TMC_DCCTRL_MASK (0b1111111111UL)
  240. #define TMC_DCCTRL_DC_TIME_MASK (0b11111111UL)
  241. #define TMC_DCCTRL_DC_SG_MASK (0b111111110000001111111111UL)
  242. // PWMCONF OFFSETS
  243. // for shifting incoming values to the right register position
  244. #define TMC_PWMCONF_FREEWHEEL (20)
  245. #define TMC_PWMCONF_PWM_SYMMETRIC (19)
  246. #define TMC_PWMCONF_PWM_AUTOSCALE (18)
  247. #define TMC_PWMCONF_PWM_FREQ (16)
  248. #define TMC_PWMCONF_PWM_GRAD (8)
  249. #define TMC_PWMCONF_PWM_AMPL (0)
  250. // PWMCONF MASKS
  251. // mask the bits from the values we want to set
  252. const int TMC_PWMCONF_MASKS[] = {
  253. 0b11111111UL, // 0 TMC_PWMCONF_PWM_AMPL
  254. 0b1111111UL, // 1
  255. 0b111111UL, // 2
  256. 0b11111UL, // 3
  257. 0b1111UL, // 4
  258. 0b111UL, // 5
  259. 0b11UL, // 6
  260. 0b1UL, // 7
  261. 0b11111111UL, // 8 TMC_PWMCONF_PWM_GRAD
  262. 0b1111111UL, // 9
  263. 0b111111UL, // 10
  264. 0b11111UL, // 11
  265. 0b1111UL, // 12
  266. 0b111UL, // 13
  267. 0b11UL, // 14
  268. 0b1UL, // 15
  269. 0b11UL, // 16 TMC_PWMCONF_PWM_FREQ
  270. 0b1UL, // 17
  271. 0b1UL, // 18 TMC_PWMCONF_PWM_AUTOSCALE
  272. 0b1UL, // 19 TMC_PWMCONF_PWM_SYMMETRIC
  273. 0b11UL, // 20 TMC_PWMCONF_FREEWHEEL
  274. 0b1UL, // 21
  275. };
  276. // ENCM_CTRL MASK
  277. // mask the bits from the values we want to set
  278. #define TMC_ENCM_CTRL_MASK (0b11);
  279. #endif // TRINAMIC_TMC2130_REGISTERS_H