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Demo for single-bit colors with LED on UP5K Devboard

master
JonathanS 1 year ago
commit
a394cfdbc8
4 changed files with 170 additions and 0 deletions
  1. 36
    0
      hdl/Makefile
  2. 2
    0
      hdl/README
  3. 15
    0
      hdl/rgb.pcf
  4. 117
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      hdl/rgb.v

+ 36
- 0
hdl/Makefile View File

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+PROJ = rgb
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+PIN_DEF = rgb.pcf
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+DEVICE = up5k
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+
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+ARACHNE = arachne-pnr 
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+ARACHNE_ARGS = 
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+ICEPACK = icepack
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+ICETIME = icetime
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+ICEPROG = iceprog
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+
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+all: $(PROJ).bin
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+
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+%.blif: %.v
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+	yosys -p 'synth_ice40 -top top -blif $@' $<
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+
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+%.asc: $(PIN_DEF) %.blif
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+	$(ARACHNE) $(ARACHNE_ARGS) -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^
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+
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+%.bin: %.asc
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+	$(ICEPACK) $< $@
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+
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+%.rpt: %.asc
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+	$(ICETIME) -d $(DEVICE) -mtr $@ $<
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+
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+prog: $(PROJ).bin
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+	$(ICEPROG) -S $<
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+
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+sudo-prog: $(PROJ).bin
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+	@echo 'Executing prog as root!!!'
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+	sudo $(ICEPROG) -S $<
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+
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+clean:
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+	rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
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+
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+.SECONDARY:
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+.PHONY: all prog clean

+ 2
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hdl/README View File

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+Simple RGB LED demo for UP5K boards, such as the Lattice "iCE40 UltraPlus Breakout Board" and
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+the Lattice "iCE40 UltraPlus Mobile Development Platform".

+ 15
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hdl/rgb.pcf View File

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+set_io RGB0 39
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+set_io RGB1 40
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+set_io RGB2 41
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+
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+set_io D_VSYNC 6 # IOB_13B
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+set_io D_HSYNC 9 #// IOB_16A
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+
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+set_io D_DEN 10  #// 18A
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+set_io D_CLK 11 #// 20A
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+
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+
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+set_io D_R 12	#// 22A
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+set_io D_G 21	#// 23B
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+set_io D_B 13	#// 24A
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+

+ 117
- 0
hdl/rgb.v View File

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+module top(
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+  output RGB0, RGB1, RGB2,
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+
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+  input D_R, D_G, D_B, D_VSYNC, D_HSYNC, D_DEN, D_CLK
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+);
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+
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+wire clk;
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+
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+SB_HFOSC inthosc (
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+  .CLKHFPU(1'b1),
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+  .CLKHFEN(1'b1),
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+  .CLKHF(clk)
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+);
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+
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+localparam  counter_width = 32;
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+
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+reg [counter_width-1:0] ctr;
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+
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+always@(posedge clk)
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+begin
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+  ctr <= ctr + 1;
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+end
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+
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+
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+localparam  pwm_width = 12;
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+
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+localparam pwm_max = (2**pwm_width) - 1;
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+localparam pwm_max_div4 = (2**(pwm_width-2)) - 1;
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+
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+
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+wire [1:0] phase = ctr[counter_width - 1 : counter_width - 2];
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+wire [pwm_width-1:0] fade = ctr[counter_width - 3 : counter_width - (2 + pwm_width)];
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+wire [pwm_width-1:0] fade_div4 = ctr[counter_width - 3 : counter_width - (pwm_width)];
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+
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+wire [pwm_width-1:0] r_val, g_val, b_val;
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+
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+
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+wire [pwm_width-1:0] r_acc, g_acc, b_acc;
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+
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+wire foo = D_R;
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+
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+reg last_VSYNC;
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+
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+always@(negedge D_CLK)
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+begin
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+  last_VSYNC <= D_VSYNC;
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+  if (D_VSYNC == 0 && last_VSYNC == 1) begin
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+    r_acc <= 12'd0;
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+    g_acc <= 12'd0;
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+    b_acc <= 12'd0;
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+    
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+    r_val <= r_acc;
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+    g_val <= g_acc;
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+    b_val <= b_acc;
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+  end else begin
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+    if ((D_HSYNC == 0)) begin
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+      r_acc <= r_acc + D_R;
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+      g_acc <= g_acc + D_G;
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+      b_acc <= b_acc + D_B;
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+    end
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+  end
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+end
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+
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+
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+//  Fade R->G->B->W->
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+/*assign r_val = (phase == 0) ? pwm_max_div4 + (3 * fade_div4) :
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+               (phase == 1) ? pwm_max - fade :
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+               (phase == 3) ? fade_div4 :
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+               0;
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+*/
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+
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+/*
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+assign r_val = D_Rin;
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+              
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+assign g_val = (phase == 0) ? pwm_max_div4 - fade_div4:
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+               (phase == 1) ? fade :
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+               (phase == 2) ? pwm_max - fade :
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+               (phase == 3) ? fade_div4 :
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+               0;
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+
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+assign b_val = (phase == 0) ? pwm_max_div4 - fade_div4:
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+               (phase == 2) ? fade :
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+               (phase == 3) ? pwm_max - (3 * fade_div4) :
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+               0;
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+               */
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+
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+reg [pwm_width-1:0] pwm_ctr;
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+
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+reg pwm_r, pwm_g, pwm_b;
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+
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+always@(posedge clk)
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+begin
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+  pwm_ctr <= pwm_ctr + 1;
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+  pwm_r <= (pwm_ctr < r_val) ? 1'b1 : 1'b0;
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+  pwm_g <= (pwm_ctr < g_val) ? 1'b1 : 1'b0;
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+  pwm_b <= (pwm_ctr < b_val) ? 1'b1 : 1'b0;
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+end
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+
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+SB_RGBA_DRV RGBA_DRIVER (
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+  .CURREN(1'b1),
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+  .RGBLEDEN(1'b1),
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+  .RGB0PWM(pwm_g),
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+  .RGB1PWM(pwm_b),
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+  .RGB2PWM(pwm_r),
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+  .RGB0(RGB0),
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+  .RGB1(RGB1),
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+  .RGB2(RGB2)
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+);
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+
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+
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+defparam RGBA_DRIVER.CURRENT_MODE = "0b1";
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+defparam RGBA_DRIVER.RGB0_CURRENT = "0b000111";
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+defparam RGBA_DRIVER.RGB1_CURRENT = "0b000111";
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+defparam RGBA_DRIVER.RGB2_CURRENT = "0b000111";
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+
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+
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+endmodule

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