669d07bdd4
As stated in commit 555c2585bf, the
Xtensa architecture has been introduced in 2009 and never changed
since its initial introduction. It requires some special handling that
is a bit annoying, and despite our call to the initial developers, and
the announcement of the deprecation of the architecture during the
2012.05, nothing has happened. Therefore, drop support for this
architecture.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: me
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
823 lines
21 KiB
Plaintext
823 lines
21 KiB
Plaintext
config BR2_ARCH_IS_64
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bool
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choice
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prompt "Target Architecture"
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default BR2_i386
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help
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Select the target architecture family to build for.
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config BR2_arm
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bool "ARM (little endian)"
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help
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ARM is a 32-bit reduced instruction set computer (RISC) instruction
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set architecture (ISA) developed by ARM Holdings. Little endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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config BR2_armeb
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bool "ARM (big endian)"
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help
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ARM is a 32-bit reduced instruction set computer (RISC) instruction
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set architecture (ISA) developed by ARM Holdings. Big endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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config BR2_avr32
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bool "AVR32"
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select BR2_SOFT_FLOAT
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help
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The AVR32 is a 32-bit RISC microprocessor architecture designed by
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Atmel.
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http://www.atmel.com/
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http://en.wikipedia.org/wiki/Avr32
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config BR2_bfin
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bool "Blackfin"
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help
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The Blackfin is a family of 16 or 32-bit microprocessors developed,
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manufactured and marketed by Analog Devices.
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http://www.analog.com/
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http://en.wikipedia.org/wiki/Blackfin
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config BR2_i386
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bool "i386"
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help
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Intel i386 architecture compatible microprocessor
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http://en.wikipedia.org/wiki/I386
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config BR2_m68k
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bool "m68k"
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depends on BROKEN # ice in uclibc / inet_ntoa_r
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help
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Motorola 68000 family microprocessor
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http://en.wikipedia.org/wiki/M68k
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config BR2_microblazeel
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bool "Microblaze AXI (little endian)"
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
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based architecture (little endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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config BR2_microblazebe
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bool "Microblaze non-AXI (big endian)"
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
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based architecture (non-AXI, big endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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config BR2_mips
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bool "MIPS (big endian)"
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mipsel
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bool "MIPS (little endian)"
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mips64
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bool "MIPS64 (big endian)"
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select BR2_ARCH_IS_64
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mips64el
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bool "MIPS64 (little endian)"
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select BR2_ARCH_IS_64
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_powerpc
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bool "PowerPC"
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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config BR2_sh
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bool "SuperH"
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help
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SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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config BR2_sh64
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bool "SuperH64"
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help
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SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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config BR2_sparc
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bool "SPARC"
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help
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SPARC (from Scalable Processor Architecture) is a RISC instruction
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set architecture (ISA) developed by Sun Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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config BR2_x86_64
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bool "x86_64"
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select BR2_ARCH_IS_64
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help
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x86-64 is an extension of the x86 instruction set (Intel i386
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architecture compatible microprocessor).
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http://en.wikipedia.org/wiki/X86_64
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endchoice
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config BR2_microblaze
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bool
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default y if BR2_microblazeel || BR2_microblazebe
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#
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# Keep the variants separate, there's no need to clutter everything else.
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# sh is fairly "special" in this regard, as virtually everyone else has
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# things kept down to a _sensible_ number of target variants. No such
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# luck for sh..
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#
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choice
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prompt "Target Architecture Variant"
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depends on BR2_arm || BR2_armeb
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default BR2_generic_arm
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help
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Specific CPU variant to use
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config BR2_generic_arm
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bool "generic_arm"
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config BR2_arm7tdmi
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bool "arm7tdmi"
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config BR2_arm610
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bool "arm610"
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config BR2_arm710
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bool "arm710"
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config BR2_arm720t
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bool "arm720t"
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config BR2_arm920t
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bool "arm920t"
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config BR2_arm922t
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bool "arm922t"
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config BR2_arm926t
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bool "arm926t"
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config BR2_arm10t
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bool "arm10t"
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config BR2_arm1136jf_s
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bool "arm1136jf_s"
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config BR2_arm1176jz_s
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bool "arm1176jz-s"
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config BR2_arm1176jzf_s
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bool "arm1176jzf-s"
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config BR2_cortex_a8
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bool "cortex-A8"
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config BR2_cortex_a9
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bool "cortex-A9"
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config BR2_sa110
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bool "sa110"
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config BR2_sa1100
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bool "sa1100"
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config BR2_xscale
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bool "xscale"
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config BR2_iwmmxt
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bool "iwmmxt"
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endchoice
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choice
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prompt "Target ABI"
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depends on BR2_arm || BR2_armeb
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default BR2_ARM_EABI
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help
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Application Binary Interface to use
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Note:
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Using OABI is discouraged.
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config BR2_ARM_EABI
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bool "EABI"
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config BR2_ARM_OABI
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bool "OABI"
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depends on !BR2_GCC_VERSION_4_7_X
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endchoice
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choice
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prompt "Target ABI"
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depends on BR2_bfin
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default BR2_BFIN_FDPIC
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config BR2_BFIN_FDPIC
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bool "FDPIC"
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config BR2_BFIN_FLAT
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bool "FLAT"
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select BR2_PREFER_STATIC_LIB
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endchoice
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choice
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prompt "Target Architecture Variant"
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depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
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default BR2_mips_3 if BR2_mips
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default BR2_mips_1 if BR2_mipsel
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default BR2_mips_64 if BR2_mips64 || BR2_mips64el
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help
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Specific CPU variant to use
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64bit cabable: 3, 4, 64, 64r2
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non-64bit capable: 1, 2, 32, 32r2
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config BR2_mips_1
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bool "mips I (generic)"
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depends on !BR2_ARCH_IS_64
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config BR2_mips_2
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bool "mips II"
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depends on !BR2_ARCH_IS_64
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config BR2_mips_3
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bool "mips III"
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config BR2_mips_4
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bool "mips IV"
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config BR2_mips_32
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bool "mips 32"
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depends on !BR2_ARCH_IS_64
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config BR2_mips_32r2
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bool "mips 32r2"
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depends on !BR2_ARCH_IS_64
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config BR2_mips_64
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bool "mips 64"
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config BR2_mips_64r2
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bool "mips 64r2"
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endchoice
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choice
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prompt "Target ABI"
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depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
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default BR2_MIPS_OABI32 if !BR2_ARCH_IS_64
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default BR2_MIPS_NABI32 if BR2_ARCH_IS_64
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help
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Application Binary Interface to use
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config BR2_MIPS_OABI32
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bool "o32"
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config BR2_MIPS_NABI32
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bool "n32"
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depends on BR2_ARCH_IS_64
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config BR2_MIPS_NABI64
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bool "n64"
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depends on BR2_ARCH_IS_64
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endchoice
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choice
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prompt "Target Architecture Variant"
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depends on BR2_sh
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default BR2_sh4
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help
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Specific CPU variant to use
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config BR2_sh2
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bool "sh2 (SH2 big endian)"
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config BR2_sh2a
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bool "sh2a (SH2A big endian)"
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config BR2_sh3
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bool "sh3 (SH3 little endian)"
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config BR2_sh3eb
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bool "sh3eb (SH3 big endian)"
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config BR2_sh4
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bool "sh4 (SH4 little endian)"
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config BR2_sh4eb
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bool "sh4eb (SH4 big endian)"
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config BR2_sh4a
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bool "sh4a (SH4A little endian)"
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config BR2_sh4aeb
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bool "sh4aeb (SH4A big endian)"
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endchoice
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#
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# gcc builds libstdc++ differently depending on the
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# host tuplet given to it, so let people choose
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#
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# i386/x86_64 cpu features
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config BR2_X86_CPU_HAS_MMX
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bool
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config BR2_X86_CPU_HAS_SSE
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bool
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config BR2_X86_CPU_HAS_SSE2
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bool
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config BR2_X86_CPU_HAS_SSE3
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bool
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config BR2_X86_CPU_HAS_SSSE3
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bool
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choice
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prompt "Target Architecture Variant"
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depends on BR2_i386 || BR2_x86_64
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default BR2_x86_i586 if BR2_i386
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default BR2_x86_generic if BR2_x86_64
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help
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Specific CPU variant to use
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config BR2_x86_generic
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bool "generic"
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config BR2_x86_i386
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bool "i386"
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depends on !BR2_x86_64
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config BR2_x86_i486
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bool "i486"
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depends on !BR2_x86_64
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config BR2_x86_i586
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bool "i586"
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depends on !BR2_x86_64
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config BR2_x86_i686
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bool "i686"
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depends on !BR2_x86_64
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config BR2_x86_pentiumpro
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bool "pentium pro"
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depends on !BR2_x86_64
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config BR2_x86_pentium_mmx
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bool "pentium MMX"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_pentium_m
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bool "pentium mobile"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_pentium2
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bool "pentium2"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_pentium3
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bool "pentium3"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_pentium4
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bool "pentium4"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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depends on !BR2_x86_64
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config BR2_x86_prescott
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bool "prescott"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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depends on !BR2_x86_64
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config BR2_x86_nocona
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bool "nocona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_core2
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bool "core2"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_atom
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bool "atom"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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select BR2_X86_CPU_HAS_SSSE3
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config BR2_x86_k6
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bool "k6"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_k6_2
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bool "k6-2"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_athlon
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bool "athlon"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_athlon_4
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bool "athlon-4"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_opteron
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bool "opteron"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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config BR2_x86_opteron_sse3
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bool "opteron w/ SSE3"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_barcelona
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bool "barcelona"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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select BR2_X86_CPU_HAS_SSE2
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select BR2_X86_CPU_HAS_SSE3
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config BR2_x86_geode
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bool "geode"
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# Don't include MMX support because there several variant of geode
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# processor, some with MMX support, some without.
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# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
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depends on !BR2_x86_64
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config BR2_x86_c3
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bool "Via/Cyrix C3 (Samuel/Ezra cores)"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_c32
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bool "Via C3-2 (Nehemiah cores)"
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select BR2_X86_CPU_HAS_MMX
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select BR2_X86_CPU_HAS_SSE
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depends on !BR2_x86_64
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config BR2_x86_winchip_c6
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bool "IDT Winchip C6"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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config BR2_x86_winchip2
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bool "IDT Winchip 2"
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select BR2_X86_CPU_HAS_MMX
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depends on !BR2_x86_64
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endchoice
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choice
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prompt "Target Architecture Variant"
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depends on BR2_sparc
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default BR2_sparc_v7
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help
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Specific CPU variant to use
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config BR2_sparc_v7
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bool "v7"
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config BR2_sparc_cypress
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bool "cypress"
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config BR2_sparc_v8
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bool "v8"
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config BR2_sparc_sparchfleon
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bool "hfleon"
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config BR2_sparc_sparchfleonv8
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bool "hfleonv8"
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config BR2_sparc_sparcsfleon
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bool "sfleon"
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config BR2_sparc_sparcsfleonv8
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bool "sfleonv8"
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config BR2_sparc_supersparc
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bool "supersparc"
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config BR2_sparc_sparclite
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bool "sparclite"
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config BR2_sparc_f930
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bool "f930"
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config BR2_sparc_f934
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bool "f934"
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config BR2_sparc_hypersparc
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bool "hypersparc"
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config BR2_sparc_sparclite86x
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bool "sparclite86x"
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config BR2_sparc_sparclet
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bool "sparclet"
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config BR2_sparc_tsc701
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bool "tsc701"
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endchoice
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choice
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prompt "Target Architecture Variant"
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depends on BR2_powerpc
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default BR2_generic_powerpc
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help
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Specific CPU variant to use
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config BR2_generic_powerpc
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bool "generic"
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config BR2_powerpc_401
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bool "401"
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config BR2_powerpc_403
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bool "403"
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config BR2_powerpc_405
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bool "405"
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config BR2_powerpc_405fp
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bool "405 with FPU"
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config BR2_powerpc_440
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bool "440"
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config BR2_powerpc_440fp
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bool "440 with FPU"
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config BR2_powerpc_505
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bool "505"
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config BR2_powerpc_601
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bool "601"
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config BR2_powerpc_602
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bool "602"
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config BR2_powerpc_603
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bool "603"
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config BR2_powerpc_603e
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bool "603e"
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config BR2_powerpc_604
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bool "604"
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config BR2_powerpc_604e
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bool "604e"
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config BR2_powerpc_620
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bool "620"
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config BR2_powerpc_630
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bool "630"
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config BR2_powerpc_740
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bool "740"
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config BR2_powerpc_7400
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bool "7400"
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config BR2_powerpc_7450
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bool "7450"
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config BR2_powerpc_750
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bool "750"
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config BR2_powerpc_801
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bool "801"
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config BR2_powerpc_821
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bool "821"
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config BR2_powerpc_823
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bool "823"
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config BR2_powerpc_860
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bool "860"
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config BR2_powerpc_970
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bool "970"
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config BR2_powerpc_8540
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bool "8540 / e500v1"
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config BR2_powerpc_8548
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bool "8548 / e500v2"
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config BR2_powerpc_e300c2
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bool "e300c2"
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config BR2_powerpc_e300c3
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bool "e300c3"
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config BR2_powerpc_e500mc
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bool "e500mc"
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endchoice
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choice
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prompt "Target ABI"
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depends on BR2_powerpc
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default BR2_powerpc_SPE if BR2_powerpc_8540 || BR2_powerpc_8548
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default BR2_powerpc_CLASSIC
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help
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Application Binary Interface to use
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config BR2_powerpc_CLASSIC
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bool "Classic"
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depends on !(BR2_powerpc_8540 || BR2_powerpc_8548)
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config BR2_powerpc_SPE
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bool "SPE"
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depends on BR2_powerpc_8540 || BR2_powerpc_8548
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endchoice
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config BR2_ARCH
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string
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default "arm" if BR2_arm
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default "armeb" if BR2_armeb
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default "avr32" if BR2_avr32
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default "bfin" if BR2_bfin
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default "i386" if BR2_x86_i386
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default "i486" if BR2_x86_i486
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default "i586" if BR2_x86_i586
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default "i586" if BR2_x86_pentium_mmx
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default "i586" if BR2_x86_geode
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default "i586" if BR2_x86_c3
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default "i686" if BR2_x86_c32
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default "i586" if BR2_x86_winchip_c6
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default "i586" if BR2_x86_winchip2
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default "i686" if BR2_x86_i686
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default "i686" if BR2_x86_pentium2
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default "i686" if BR2_x86_pentium3
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default "i686" if BR2_x86_pentium4
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default "i686" if BR2_x86_pentium_m
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default "i686" if BR2_x86_pentiumpro
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default "i686" if BR2_x86_prescott
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default "i686" if BR2_x86_nocona && BR2_i386
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default "i686" if BR2_x86_core2 && BR2_i386
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default "i686" if BR2_x86_atom && BR2_i386
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default "i686" if BR2_x86_opteron && BR2_i386
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default "i686" if BR2_x86_opteron_sse3 && BR2_i386
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default "i686" if BR2_x86_barcelona && BR2_i386
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default "i686" if BR2_x86_k6
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default "i686" if BR2_x86_k6_2
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default "i686" if BR2_x86_athlon
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default "i686" if BR2_x86_athlon_4
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default "x86_64" if BR2_x86_64
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default "m68k" if BR2_m68k
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default "microblaze" if BR2_microblaze
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default "mips" if BR2_mips
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default "mipsel" if BR2_mipsel
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default "mips64" if BR2_mips64
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default "mips64el" if BR2_mips64el
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default "powerpc" if BR2_powerpc
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default "sh2" if BR2_sh2
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default "sh2a" if BR2_sh2a
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default "sh3" if BR2_sh3
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default "sh3eb" if BR2_sh3eb
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default "sh4" if BR2_sh4
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default "sh4eb" if BR2_sh4eb
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default "sh4a" if BR2_sh4a
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default "sh4aeb" if BR2_sh4aeb
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default "sh64" if BR2_sh64
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default "sparc" if BR2_sparc
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config BR2_ENDIAN
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string
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default "LITTLE" if BR2_arm || BR2_bfin || BR2_i386 || BR2_mipsel || BR2_mips64el || \
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BR2_sh3 || BR2_sh4 || BR2_sh4a || BR2_x86_64 || BR2_sh64 || \
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BR2_microblazeel
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default "BIG" if BR2_armeb || BR2_avr32 || BR2_m68k || BR2_mips || BR2_mips64 || \
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BR2_powerpc || BR2_sh2 || BR2_sh2a || \
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BR2_sh3eb || BR2_sh4eb || BR2_sh4aeb || BR2_sparc || \
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BR2_microblazebe
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config BR2_GCC_TARGET_TUNE
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string
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default i386 if BR2_x86_i386
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default i486 if BR2_x86_i486
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default i586 if BR2_x86_i586
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default pentium-mmx if BR2_x86_pentium_mmx
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default i686 if BR2_x86_i686
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default pentiumpro if BR2_x86_pentiumpro
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default pentium-m if BR2_x86_pentium_m
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default pentium2 if BR2_x86_pentium2
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default pentium3 if BR2_x86_pentium3
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default pentium4 if BR2_x86_pentium4
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default prescott if BR2_x86_prescott
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default nocona if BR2_x86_nocona
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default core2 if BR2_x86_core2
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default atom if BR2_x86_atom
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default k8 if BR2_x86_opteron
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default k8-sse3 if BR2_x86_opteron_sse3
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default barcelona if BR2_x86_barcelona
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default k6 if BR2_x86_k6
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default k6-2 if BR2_x86_k6_2
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default athlon if BR2_x86_athlon
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default athlon-4 if BR2_x86_athlon_4
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default winchip-c6 if BR2_x86_winchip_c6
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default winchip2 if BR2_x86_winchip2
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default c3 if BR2_x86_c3
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default c3-2 if BR2_x86_c32
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default geode if BR2_x86_geode
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default generic if BR2_x86_generic
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default arm600 if BR2_arm600
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default arm610 if BR2_arm610
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default arm620 if BR2_arm620
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default arm7tdmi if BR2_arm7tdmi
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default arm7tdmi if BR2_arm720t
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default arm7tdmi if BR2_arm740t
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default arm920 if BR2_arm920
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default arm920t if BR2_arm920t
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default arm922t if BR2_arm922t
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default arm926ej-s if BR2_arm926t
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default arm1136j-s if BR2_arm1136j_s
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default arm1136jf-s if BR2_arm1136jf_s
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default arm1176jz-s if BR2_arm1176jz_s
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default arm1176jzf-s if BR2_arm1176jzf_s
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default cortex-a8 if BR2_cortex_a8
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default cortex-a9 if BR2_cortex_a9
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default strongarm110 if BR2_sa110
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default strongarm1100 if BR2_sa1100
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default xscale if BR2_xscale
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default iwmmxt if BR2_iwmmxt
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default 68000 if BR2_m68k_68000
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default 68010 if BR2_m68k_68010
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default 68020 if BR2_m68k_68020
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default 68030 if BR2_m68k_68030
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default 68040 if BR2_m68k_68040
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default 68060 if BR2_m68k_68060
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default mips1 if BR2_mips_1
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default mips2 if BR2_mips_2
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default mips3 if BR2_mips_3
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default mips4 if BR2_mips_4
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default mips32 if BR2_mips_32
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default mips32r2 if BR2_mips_32r2
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default mips64 if BR2_mips_64
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default mips64r2 if BR2_mips_64r2
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default 401 if BR2_powerpc_401
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default 403 if BR2_powerpc_403
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default 405 if BR2_powerpc_405
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default 405fp if BR2_powerpc_405fp
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default 440 if BR2_powerpc_440
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default 440fp if BR2_powerpc_440fp
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default 505 if BR2_powerpc_505
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default 601 if BR2_powerpc_601
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default 602 if BR2_powerpc_602
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default 603 if BR2_powerpc_603
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default 603e if BR2_powerpc_603e
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default 604 if BR2_powerpc_604
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default 604e if BR2_powerpc_604e
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default 620 if BR2_powerpc_620
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default 630 if BR2_powerpc_630
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default 740 if BR2_powerpc_740
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default 7400 if BR2_powerpc_7400
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default 7450 if BR2_powerpc_7450
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default 750 if BR2_powerpc_750
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default 801 if BR2_powerpc_801
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default 821 if BR2_powerpc_821
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default 823 if BR2_powerpc_823
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default 860 if BR2_powerpc_860
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default 970 if BR2_powerpc_970
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default 8540 if BR2_powerpc_8540
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default 8548 if BR2_powerpc_8548
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default e300c2 if BR2_powerpc_e300c2
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default e300c3 if BR2_powerpc_e300c3
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default e500mc if BR2_powerpc_e500mc
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default v7 if BR2_sparc_v7
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default cypress if BR2_sparc_cypress
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default v8 if BR2_sparc_v8
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default supersparc if BR2_sparc_supersparc
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default hypersparc if BR2_sparc_hypersparc
|
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default sparclite if BR2_sparc_sparclite
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default f930 if BR2_sparc_f930
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default f934 if BR2_sparc_f934
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default sparclite86x if BR2_sparc_sparclite86x
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default sparclet if BR2_sparc_sparclet
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default tsc701 if BR2_sparc_tsc701
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default v9 if BR2_sparc_v9
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default v9 if BR2_sparc_v9a
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default v9 if BR2_sparc_v9b
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default ultrasparc if BR2_sparc_ultrasparc
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default ultrasparc3 if BR2_sparc_ultrasparc3
|
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default niagara if BR2_sparc_niagara
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|
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config BR2_GCC_TARGET_ARCH
|
|
string
|
|
default i386 if BR2_x86_i386
|
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default i486 if BR2_x86_i486
|
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default i586 if BR2_x86_i586
|
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default pentium-mmx if BR2_x86_pentium_mmx
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default i686 if BR2_x86_i686
|
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default pentiumpro if BR2_x86_pentiumpro
|
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default pentium-m if BR2_x86_pentium_m
|
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default pentium2 if BR2_x86_pentium2
|
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default pentium3 if BR2_x86_pentium3
|
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default pentium4 if BR2_x86_pentium4
|
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default prescott if BR2_x86_prescott
|
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default nocona if BR2_x86_nocona
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default core2 if BR2_x86_core2
|
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default atom if BR2_x86_atom
|
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default k8 if BR2_x86_opteron
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default k8-sse3 if BR2_x86_opteron_sse3
|
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default barcelona if BR2_x86_barcelona
|
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default k6 if BR2_x86_k6
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default k6-2 if BR2_x86_k6_2
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default athlon if BR2_x86_athlon
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default athlon-4 if BR2_x86_athlon_4
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default winchip-c6 if BR2_x86_winchip_c6
|
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default winchip2 if BR2_x86_winchip2
|
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default c3 if BR2_x86_c3
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default c3-2 if BR2_x86_c32
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default geode if BR2_x86_geode
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default armv4t if BR2_arm7tdmi
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default armv3 if BR2_arm610
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default armv3 if BR2_arm710
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default armv4t if BR2_arm720t
|
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default armv4t if BR2_arm920t
|
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default armv4t if BR2_arm922t
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default armv5te if BR2_arm926t
|
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default armv5t if BR2_arm10t
|
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default armv6j if BR2_arm1136jf_s
|
|
default armv6zk if BR2_arm1176jz_s
|
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default armv6zk if BR2_arm1176jzf_s
|
|
default armv7-a if BR2_cortex_a8
|
|
default armv7-a if BR2_cortex_a9
|
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default armv4 if BR2_sa110
|
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default armv4 if BR2_sa1100
|
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default armv5te if BR2_xscale
|
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default iwmmxt if BR2_iwmmxt
|
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default 68000 if BR2_m68k_68000
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default 68010 if BR2_m68k_68010
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default 68020 if BR2_m68k_68020
|
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default 68030 if BR2_m68k_68030
|
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default 68040 if BR2_m68k_68040
|
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default 68060 if BR2_m68k_68060
|
|
|
|
config BR2_GCC_TARGET_ABI
|
|
string
|
|
default apcs-gnu if BR2_ARM_OABI
|
|
default aapcs-linux if BR2_ARM_EABI
|
|
default 32 if BR2_MIPS_OABI32
|
|
default n32 if BR2_MIPS_NABI32
|
|
default 64 if BR2_MIPS_NABI64
|
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default altivec if BR2_powerpc && BR2_PPC_ABI_altivec
|
|
default no-altivec if BR2_powerpc && BR2_PPC_ABI_no-altivec
|
|
default spe if BR2_powerpc && BR2_PPC_ABI_spe
|
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default no-spe if BR2_powerpc && BR2_PPC_ABI_no-spe
|
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default ibmlongdouble if BR2_powerpc && BR2_PPC_ABI_ibmlongdouble
|
|
default ieeelongdouble if BR2_powerpc && BR2_PPC_ABI_ieeelongdouble
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|
|
|
config BR2_GCC_TARGET_CPU
|
|
string
|
|
default sparchfleon if BR2_sparc_sparchfleon
|
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default sparchfleonv8 if BR2_sparc_sparchfleonv8
|
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default sparcsfleon if BR2_sparc_sparcsfleon
|
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default sparcsfleonv8 if BR2_sparc_sparcsfleonv8
|